JP5110807B2 - Multilayer capacitor - Google Patents

Description

  The present invention relates to a multilayer capacitor, and is particularly advantageously used in, for example, a high-frequency circuit in the field of optical communication, and is mounted in a state in which the surface direction of the internal electrode is oriented so as to be orthogonal to the mounting surface. The present invention relates to a multilayer capacitor.

  In recent years, along with the expansion of high-speed communication, high-speed optical communication represented by optical fiber communication and the like is rapidly progressing. Such electronic components for high-speed optical communication are required to exhibit good pass characteristics in a wide frequency band such as 10 kHz to 40 GHz.

  A device that performs high-speed transmission by optical communication requires an E / O module that converts an electrical signal and an optical signal, and an amplifier that amplifies a high-frequency signal in a wide band. Capacitors used in circuits using such devices are required to have a broadband coupling capability.

  Conventionally, a single-chip microchip capacitor has been used for this type of high-frequency circuit. However, according to the microchip capacitor having a single plate structure, the inductance can be set low due to the structure, but there is a problem that the capacitance cannot be increased. In addition, since a wire or a metal plate is required for connection to the wiring on the substrate, a large inductance is brought about as a result.

  On the other hand, various multilayer capacitors having a structure in which a dielectric layer and internal electrodes are laminated are provided. According to the multilayer capacitor, a large capacitance can be secured. However, the multilayer capacitor generally has a problem that the inductance cannot be made very low. Measures have been proposed to reduce the inductance by using a multi-terminal structure for the input / output terminals, but the wiring of the board becomes complicated, which causes a new problem that the inductance in the wiring of the board increases. is doing. Therefore, it is desired to realize a multilayer capacitor having a simple structure such as two terminals and having a high capacity and a low inductance.

  As a multilayer capacitor that can satisfy the above-described demand, for example, a capacitor as described in Patent Document 1 has been proposed. This multilayer capacitor is mounted in a state in which the surface direction of the internal electrode is oriented so as to be orthogonal to the mounting surface. FIG. 5 shows such a multilayer capacitor 1. 5A is a front view showing the appearance of the multilayer capacitor 1, and FIG. 5B is a front view showing a cross section through which a specific internal electrode passes in order to show the internal structure of the multilayer capacitor 1. (C) is sectional drawing which follows the line CC of (b).

  The multilayer capacitor 1 has a plurality of laminated dielectric layers 2 and a specific interface between the dielectric layers 2 so as to form a capacitance by facing each other through the specific dielectric layer 2. A rectangular parallelepiped capacitor body 5 including a plurality of sets of first and second internal electrodes 3 and 4 respectively formed is provided.

  In FIG. 5B, the first internal electrode 3 indicated by a solid line and the second internal electrode 4 indicated by a broken line are illustrated in a state slightly shifted from each other. And only the convenient means for enabling the illustration of both the second internal electrodes 3 and 4, and in fact, the first internal electrode 3 and the second internal electrode 4 are completely overlapped. Ideally.

  The multilayer capacitor 1 also includes first and second terminal electrodes 6 and 7 formed on the outer surface of the capacitor body 5. The first and second internal electrodes 3 and 4 respectively include first and second capacitance forming portions 8 and 9 that contribute to capacitance formation, and first and second capacitance forming portions 8 and 9, respectively. And first and second lead portions 10 and 11 that are led out from and electrically connected to the first and second terminal electrodes 6 and 7, respectively.

  5A and 5B, the mounting surface 12 is indicated by an imaginary line. The mounting surface 12 is formed on a wiring board on which the multilayer capacitor 1 is to be mounted, and the terminal electrodes 6 and 7 are positioned on the facing surface 13 of the capacitor body 5 that faces the mounting surface 12. Yes. When the multilayer capacitor 1 is mounted on the mounting surface 12, the capacitor body 5 is oriented such that the surface directions of the first and second internal electrodes 3 and 4 are orthogonal to the mounting surface 12.

In the multilayer capacitor 1 described in Patent Document 1, the distance between the first and second lead portions 10 and 11 is a [mm], and the lead length of the first lead portion 10 is b ₁ [mm]. When the drawer length of the second drawer part 11 is b ₂ [mm],
1.64a + (b ₁ + b ₂ ) ≦ 0.85
By satisfying this condition, the inductance is reduced. In short, in the multilayer capacitor 1, when the length direction dimension of the capacitor body 5 is L and the height direction dimension is H, a surface defined by the length direction dimension L and the height direction dimension H, that is, By reducing the current loop generated in the direction of the LH plane, an attempt is made to reduce the inductance.

However, in the multilayer capacitor 1, it has been found that when the dimension H in the height direction of the capacitor body 5 is larger than a predetermined value, the pass characteristic in the high frequency region is deteriorated. More specifically, it has been found that when the height dimension H is larger than 0.50 mm, the loss of the S21 pass characteristic is increased, for example, in a high frequency region exceeding 25 GHz.
JP 2004-140183 A

  Accordingly, an object of the present invention is to provide a multilayer capacitor that can solve the above-described problems.

  The multilayer capacitor according to the present invention includes a plurality of laminated dielectric layers and a specific interface between the dielectric layers so as to form a capacitance by facing each other through the specific dielectric layer. Each of the main parts is formed only on a rectangular parallelepiped capacitor main body constituted by a plurality of sets of first and second internal electrodes formed, and on an opposing surface facing the mounting surface of the capacitor main body, and the first And first and second terminal electrodes that are electrically connected to the first and second internal electrodes, respectively.

  In the multilayer capacitor according to the present invention, the capacitor body is oriented such that the surface direction of the first and second internal electrodes is orthogonal to the mounting surface, and the first and second terminal electrodes are on the mounting surface. The first and second signal lines formed in the above are used for surface mounting in an electrically connected state.

In such a multilayer capacitor, in order to solve the technical problem described above, in the present invention, the first internal electrode is drawn from the first capacitance forming portion, the first capacitance forming portion, and the first terminal. A first lead portion connected to the electrode, and the second internal electrode is drawn from the second capacitance forming portion and the second capacitance forming portion and connected to the second terminal electrode. 2 lead portions, and in the length direction of the capacitor body, of the two end portions of the first terminal electrode, the position of the end portion far from the second terminal electrode, and the second capacitance forming portion Of the four corners of the first terminal electrode and the corner of the second terminal electrode in the length direction of the capacitor body in the length direction of the capacitor body. The position of the end portion far from the terminal electrode and the four corners of the first capacitance forming portion A position closest corner to the second terminal electrode, are aligned, further characterized in that the height dimension of the capacitor body and 0.30Mm～0.50Mm.
The dimension of the capacitor body in the height direction is preferably 0.30 mm to 0.35 mm.

  According to the present invention, as described above, by reducing the height dimension of the capacitor body to 0.30 mm to 0.50 mm, for example, the loss of pass characteristics in a high frequency range exceeding 25 GHz is suppressed to a low level. Can do. This is due to the following reason.

  For example, a current flows around the internal electrode in a high frequency range exceeding 25 GHz. Typically, this current includes a current that flows between the first and second terminal electrodes in the shortest time, and the first and second internal electrodes. There is a current that flows around each of them (including a current that flows around the internal electrode away from the mounting surface). Here, regarding the current flowing around the inner electrode, as described above, the distance through which this current flows can be shortened by reducing the height direction dimension of the capacitor body to 0.50 mm or less. As a result, the loss of pass characteristics in the high frequency range can be reduced.

  In addition, the reason why the lower limit of the dimension in the height direction of the capacitor body is set to 0.30 mm is that if it is less than this, it is difficult to design for obtaining a capacitance of a predetermined value or more.

  FIG. 1 is a view corresponding to FIG. 5 described above, and shows a multilayer capacitor 21 according to an embodiment of the present invention. More specifically, in FIG. 1, (a) is a front view showing the appearance of the multilayer capacitor 21, and (b) shows a cross section through which a specific internal electrode passes in order to show the internal structure of the multilayer capacitor 1. (C) is sectional drawing which follows the line CC of (b).

  As in the case of the multilayer capacitor 1 shown in FIG. 5, the multilayer capacitor 21 forms a capacitance by facing a plurality of stacked dielectric layers 22 and a specific dielectric layer 22. The capacitor body 25 has a rectangular parallelepiped shape and includes a plurality of sets of first and second internal electrodes 23 and 24 respectively formed along a specific interface between the dielectric layers 22. When the multilayer capacitor 21 is a multilayer ceramic capacitor, the above-described dielectric layer 22 is made of a dielectric ceramic.

  In FIG. 1 (b), as in FIG. 5 (b), the first internal electrode 23 indicated by a solid line and the second internal electrode 24 indicated by a broken line are shown in a slightly shifted state. However, this is only a convenient means for allowing the illustration of both the first and second internal electrodes 23 and 24, and in practice the first internal electrode 23 and the second internal electrode 23 Ideally, the electrode 24 completely overlaps.

The multilayer capacitor 21 also includes first and second terminal electrodes 26 and 27 formed on the outer surface of the capacitor body 25. The first and second internal electrodes 23 and 24 are respectively the first and second capacitance forming portions 28 and 29 that contribute to capacitance formation, and the first and second capacitance forming portions 28 and 29, respectively. And first and second lead portions 30 and 31 which are drawn from the terminal and connected to the first and second terminal electrodes 26 and 27, respectively.
Further, as can be seen from FIG. 1 and FIGS. 2 and 3 to be described later, in the length direction of the capacitor body 25, the end on the side farther from the second terminal electrode 27 out of the two ends of the first terminal electrode 26. And the position of the corner closest to the first terminal electrode 26 among the four corners of the second capacitance forming portion 29 are aligned, and in the length direction of the capacitor body 25, Of the two end portions of the second terminal electrode 27, the position of the end portion far from the first terminal electrode 26 and the second terminal electrode 27 among the four corner portions of the first capacitance forming portion 28. The nearest corner position is aligned.

  1A and 1B, the mounting surface 32 is indicated by an imaginary line. The main portions of the first and second terminal electrodes 26 and 27 are formed only on the facing surface 33 of the capacitor body 25 facing the mounting surface 32. In this embodiment, each of the first and second terminal electrodes 26 and 27 is formed only on the facing surface 33, and on the facing surface 33, one end to the other end in the stacking direction of the capacitor body 21. It is formed so that it may extend to.

  The present invention is characterized in that, in the multilayer capacitor 21 as described above, the height dimension H of the capacitor body 25 is reduced to 0.30 mm to 0.50 mm. Thus, by reducing the height dimension H of the capacitor body 25 to 0.30 mm to 0.50 mm, it is possible to reduce the loss of the pass characteristic in the high frequency range. This will be described with reference to FIG.

  FIG. 2 shows the multilayer capacitor 21 shown in FIG. 1 and the conventional multilayer capacitor 1 shown in FIG. 5 in comparison. In FIG. 2, elements corresponding to those shown in FIG. 1 or FIG.

  As indicated by arrows in FIGS. 2A and 2B, current flows around the internal electrodes 23 and 24 (or 3 and 4), for example, in a high frequency region exceeding 25 GHz. This current is the current 35 that flows between the first and second terminal electrodes 26 and 27 (or 6 and 7) in the shortest and the internal electrodes 23 and 24 (or 3 and 4) including the region away from the mounting surface. ) And a current 36 flowing around. Here, with respect to the latter current 36, the distance through which the capacitor body 25 (or 5) flows changes depending on the height dimension of the capacitor body 25 (or 5). Therefore, if the height dimension H is reduced to 0.50 mm or less, the distance through which the current 36 flows can be shortened, and as a result, the loss of pass characteristics in the high frequency region can be reduced.

  Next, experimental examples carried out to confirm the effect of the multilayer capacitor according to the present invention will be described.

  FIG. 3 is an LH cross section for explaining the multilayer capacitor 50 according to the sample manufactured in this experimental example. 3 shows a multilayer capacitor 50, a capacitor main body 51 provided therein, an internal electrode 54 having a capacitance forming portion 52 and a lead-out portion 53, and a terminal electrode 55.

  Also, in FIG. 3, numerical values (unit: mm) indicating the dimensions of each part of the sample produced in this experimental example are entered. In this experimental example, five types of samples were produced in which the height dimension H of the capacitor body 51 was changed to 0.30 mm, 0.35 mm, 0.40 mm, 0.50 mm, and 0.80 mm. In this experimental example, the width direction dimension of the capacitor body 51 (the dimension in the direction orthogonal to the paper surface of FIG. 3) is 0.45 mm and the relative dielectric constant of the dielectric constituting the dielectric layer is set for each sample. 2500, nickel was used as the conductive component of the internal electrode 54, the material of the terminal electrode 55 was a copper base with nickel plating and gold plating, and the number of internal electrodes was 87.

  The multilayer capacitor 50 according to each sample as described above was mounted so as to be connected to a microstrip line having a width of 0.45 mm, and the characteristics as a DC cut capacitor were measured. Here, the microstrip line was formed on a wiring board having a relative dielectric constant of 2.6 and a thickness of 0.2 mm so as to have a characteristic impedance of 50Ω. Moreover, the characteristic of a DC cut capacitor measured the S21 passage characteristic in the frequency range of 5-40 GHz using the high frequency measuring device of the network analyzer.

  The result is shown in FIG.

As can be seen from FIG. 4, in the frequency range below 30 GHz, a significant difference due to the difference in the dimension H in the height direction of the capacitor body 51 does not appear particularly in the S21 passing characteristics, but in the high frequency range above 30 GHz, A sample having a height dimension H of 51 in a range of 0.30 mm to 0.50 mm (particularly a sample in a range of 0.30 mm to 0.35 mm) and a sample having a height dimension H of 0.80 mm. There is a significant difference in the S21 passing characteristics. And according to the sample whose height direction dimension H of the former exists in the range of 0.30 mm-0.50 mm (especially the sample which exists in the range of 0.30 mm-0.35 mm) , the latter height direction dimension H is Compared with the 0.80 mm sample, the loss in the S21 pass characteristic can be reduced by about 0.5 dB.

  In this experimental example, when a preferable range of the dimension L in the length direction of the capacitor body 51 was obtained, it was 0.5 mm to 1.5 mm. Here, when the length direction dimension L is increased, the current flowing distance in the length direction of the internal electrode 54 is increased, and the loss of the S21 passing characteristic is increased. On the other hand, when the length direction dimension L is reduced, the loss of the S21 pass characteristic can be reduced, but the acquisition capacity is reduced.

  Moreover, when the preferable range of the width direction dimension (dimension of the direction orthogonal to FIG. 3 paper surface) of the capacitor | condenser main body 51 was calculated | required, it was set to 0.2 mm-0.7 mm. Here, when the dimension in the width direction becomes large, the dimension in the width direction of the capacitor body 51 becomes wider than the signal line width (usually 0.7 mm or less) at the time of mounting, current reflection occurs on the mounting surface in the high frequency region, and S21 passing characteristics. The loss of On the other hand, when the width direction dimension of the capacitor body 51 is small, the acquired capacity is small.

1 shows a multilayer capacitor 21 according to an embodiment of the present invention, in which (a) is a front view showing an appearance of the multilayer capacitor 21, and (b) shows a specific internal structure in order to show an internal structure of the multilayer capacitor 21. It is the front view shown with the section which electrode 23 passes, and (c) is a sectional view which meets line CC of (b). It is a figure corresponded to Fig.1 (a) for demonstrating the effect | action and effect of this invention. It is a figure corresponded to Fig.1 (a) for demonstrating the sample produced in the experiment example implemented in order to confirm the effect by this invention. It is a figure which shows S21 passage characteristic about the multilayer capacitor which concerns on each sample produced in the experiment example. FIG. 1 shows a conventional multilayer capacitor 1 of interest to the present invention, in which (a) is a surface view showing the appearance of the multilayer capacitor 1 and (b) shows a specific internal structure to show the internal structure of the multilayer capacitor 1. It is the front view shown with the cross section which the electrode 3 passes, (c) is sectional drawing which follows the line CC of (b).

Explanation of symbols

21 multilayer capacitor 22 dielectric layer 23, 24 internal electrode 25 capacitor body 26, 27 terminal electrode 32 mounting surface H height dimension of capacitor body

Claims (2)

A plurality of sets of dielectric layers that are stacked, and a plurality of sets each formed along a specific interface between the dielectric layers so as to form a capacitance by facing each other through the specific dielectric layer A rectangular parallelepiped capacitor body composed of first and second internal electrodes;
First and second terminal electrodes, each of which is formed only on a facing surface facing the mounting surface of the capacitor body, and is electrically connected to the first and second internal electrodes, respectively. With
The capacitor body is oriented so that the surface direction of the first and second internal electrodes is orthogonal to the mounting surface, and the first and second terminal electrodes are formed on the mounting surface. A multilayer capacitor directed to a surface-mounted application electrically connected to each of the first and second signal lines,
The first internal electrode includes a first capacitance forming portion, and a first lead portion drawn from the first capacitance forming portion and connected to the first terminal electrode,
The second internal electrode includes a second capacitance forming portion, and a second lead portion drawn from the second capacitance forming portion and connected to the second terminal electrode,
In the length direction of the capacitor body, of the two end portions of the first terminal electrode, the position of the end portion far from the second terminal electrode and the four corner portions of the second capacitance forming portion And the position of the corner closest to the first terminal electrode is aligned,
In the length direction of the capacitor body, of the two end portions of the second terminal electrode, the position of the end portion far from the first terminal electrode and the four corner portions of the first capacitance forming portion And the position of the corner closest to the second terminal electrode is aligned,
A multilayer capacitor characterized in that a height dimension of the capacitor body is 0.30 mm to 0.50 mm. A multilayer capacitor, wherein a dimension of the capacitor body in a height direction is set to 0.30 mm to 0.35 mm.

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