JP5141715B2 - Multilayer capacitor - Google Patents

Description

  The present invention relates to a multilayer capacitor, and more particularly to a multilayer capacitor that is mounted in a state in which the surface direction of an internal electrode is oriented so as to be orthogonal to the mounting surface.

  As a multilayer capacitor that is of interest to the present invention, there is a multilayer capacitor that is mounted in a state in which the surface direction of the internal electrode is oriented so as to be orthogonal to the mounting surface (see, for example, Patent Document 1). FIG. 6 shows such a multilayer capacitor 1. 6A is a front view showing the appearance of the multilayer capacitor 1, and FIG. 6B is a front view showing a cross section through which a specific internal electrode passes in order to show the internal structure of the multilayer capacitor 1. (C) is sectional drawing which follows the line CC of (b).

  The multilayer capacitor 1 has a plurality of laminated dielectric layers 2 and a specific interface between the dielectric layers 2 so as to form a capacitance by facing each other through the specific dielectric layer 2. A rectangular parallelepiped capacitor body 5 including a plurality of sets of first and second internal electrodes 3 and 4 respectively formed is provided.

  In FIG. 6B, the first internal electrode 3 indicated by a solid line and the second internal electrode 4 indicated by a broken line are illustrated as being slightly shifted from each other. And only the convenient means for enabling the illustration of both the second internal electrodes 3 and 4, and in fact, the first internal electrode 3 and the second internal electrode 4 are completely overlapped. Ideally.

  The multilayer capacitor 1 also includes first and second terminal electrodes 6 and 7 formed on the outer surface of the capacitor body 5. The first and second internal electrodes 3 and 4 respectively include first and second capacitance forming portions 8 and 9 that contribute to capacitance formation, and first and second capacitance forming portions 8 and 9, respectively. And first and second lead portions 10 and 11 that are led out from and electrically connected to the first and second terminal electrodes 6 and 7, respectively.

  6A and 6B, the mounting surface 12 is indicated by an imaginary line. The mounting surface 12 is formed on a wiring board on which the multilayer capacitor 1 is to be mounted, and the terminal electrodes 6 and 7 are provided on at least one of the opposing surfaces 13 of the capacitor body 5 facing the mounting surface 12. The part is located. When the multilayer capacitor 1 is mounted on the mounting surface 12, the capacitor body 5 is oriented such that the surface directions of the first and second internal electrodes 3 and 4 are orthogonal to the mounting surface 12.

  In the following description, as shown in FIG. 6, the length dimension L of the capacitor body 5 is L, the thickness dimension T is T, and the width dimension (that is, the stacking direction) is W. A surface defined by the thickness direction dimension T is referred to as an LT surface, and a surface defined by the length direction dimension L and the width direction dimension W is defined as an LW surface.

  According to the technique described in Patent Document 1, an attempt is made to reduce the equivalent series inductance (ESL) by shortening the current loop generated in the LT plane direction as much as possible. However, Patent Document 1 does not describe any behavior of current on the LW plane.

  FIG. 7 is a plan view illustrating an example of a mounted state of the multilayer capacitor 1. In FIG. 7, elements corresponding to those shown in FIG. 6 are denoted by the same reference numerals, and redundant description is omitted.

  Referring to FIG. 7, a wiring board 14 that provides the mounting surface 12 is illustrated. First and second signal lines 15 and 16 are formed on the mounting surface 12 of the wiring board 14. As described above, while the capacitor body 5 is oriented so that the surface direction of the first and second internal electrodes 3 and 4 is orthogonal to the mounting surface 12, the first and second terminal electrodes 6 and The multilayer capacitor 1 is surface-mounted in a state where 7 is electrically connected to the first and second signal lines 15 and 16, respectively. In FIG. 7, in particular, in order to clearly illustrate the positional relationship between the signal lines 15 and 16 and the internal electrodes 3 and 4, the elements included in the multilayer capacitor 1 are shown with the signal lines 15 and 16 in a state where they are seen through. It is shown.

  Conventionally, the terminal electrode of an electronic component was generally smaller than the conductive land on the wiring board side, but recently, due to reasons such as high-density mounting, both sizes have become similar, The width of the signal line and the width of the conductive land are about the same. Therefore, also in the configuration shown in FIG. 7, the widths of the first and second conductive lands 17 and 18 formed in the first and second signal lines 15 and 16, respectively, and the first and second terminals The widths of the electrodes 6 and 7 are substantially the same as the widths of the first and second signal lines 15 and 16.

  In such a configuration, when the number of the internal electrodes 3 and 4 included in the multilayer capacitor 1 is relatively small, the distribution region D of the internal electrodes 3 and 4 in the stacking direction of the capacitor body 5 is different from that of the terminal electrodes 6 and 7. The width is considerably narrower than any of the widths of the signal lines 15 and 16 and the widths of the conductive lands 17 and 18.

  As a result, when an internal electrode group composed of a plurality of internal electrodes 3 and 4 is viewed as one signal line, the width of this signal line, that is, the above-described distribution region D is equal to the signal line 15 on the wiring board 14 side. Since the width is extremely narrow compared to the widths of 16, the current concentration occurs at the connection portion between the terminal electrodes 6 and 7 of the multilayer capacitor 1 and the internal electrodes 3 and 4. Therefore, impedance matching cannot be achieved, and signal reflection occurs, which becomes a loss, and deteriorates, for example, the S21 pass characteristic.

JP 2004-140183 A

  Accordingly, an object of the present invention is to provide a multilayer capacitor that can solve the above-described problems.

  The multilayer capacitor according to the present invention includes a plurality of laminated dielectric layers and a specific interface between the dielectric layers so as to form a capacitance by facing each other through the specific dielectric layer. A rectangular parallelepiped capacitor body composed of a plurality of sets of first and second internal electrodes formed, and formed on the outer surface of the capacitor body and electrically connected to the first and second internal electrodes, respectively. And first and second terminal electrodes connected to each other.

  In the multilayer capacitor according to the present invention, the capacitor body is oriented such that the surface direction of the first and second internal electrodes is orthogonal to the mounting surface, and the first and second terminal electrodes are on the mounting surface. The first and second signal lines formed in the above are used for surface mounting in an electrically connected state.

  In order to solve the above-described technical problem, the multilayer capacitor having such a configuration is characterized by having the following configuration.

That is, the plurality of sets of first and second internal electrodes constitute a plurality of capacitor units respectively provided by at least one set of first and second internal electrodes, and the plurality of capacitor units are mutually connected. Between the first and second internal electrodes constituting each capacitor unit, with a distance wider than the distance between the first and second internal electrodes constituting each capacitor unit. And the outer surface of the capacitor body has first and second surfaces parallel to the surface facing the mounting surface and the surface directions of the first and second internal electrodes. a second end surface, the spacing between the plurality of capacitor units, as compared to the spacing between the first nearest capacitor unit on the end face and the first end surface, a second As compared to the spacing between the nearest capacitor unit and said second end face to end face, broadly, the first and second terminal electrodes are formed on opposite sides, first and second terminals Each of the electrodes is formed so as to reach from the opposing surface to the end surface.

  In the multilayer capacitor according to the present invention, the plurality of sets of first and second internal electrodes constitute two capacitor units, and each capacitor unit is disposed at each end in the stacking direction of the capacitor body. It is preferable that

  According to the present invention, the plurality of capacitor units respectively provided by at least one set of the first and second internal electrodes, the first and second internal electrodes constituting each capacitor unit between each other. The first and second internal electrodes as a whole in the stacking direction of the capacitor body are widened by being spaced apart from each other by a wider distance. Therefore, when an internal electrode group including a plurality of internal electrodes is regarded as one signal line, the width of the signal line can be increased. Therefore, current concentration at the connection portion between the terminal electrode and the internal electrode is alleviated, and as a result, good impedance matching is obtained, signal reflection is reduced, and loss due to this reflection can be reduced. Further, when the multilayer capacitor according to the present invention is used as a DC cut capacitor, it is possible to suppress the deterioration of the S21 pass characteristic in a frequency range of 10 GHz or less.

  In the present invention, the plurality of capacitor units positioned at a relatively wide interval constitute one signal line including the dielectric layer positioned therebetween. Usually, the current in the signal line tends to concentrate at the edge of the line. Therefore, even if a dielectric layer exists in a relatively wide space between a plurality of capacitor units, there is little influence on the current flow. Rather, the line width is widened, so that impedance matching is achieved and reflection occurs. The effect of reducing loss is obtained.

1 shows a multilayer capacitor 21 according to an embodiment of the present invention, in which (a) is a front view showing an appearance of the multilayer capacitor 21, and (b) shows a specific internal structure in order to show an internal structure of the multilayer capacitor 21. It is the front view shown with the section which electrode 23 passes, and (c) is a sectional view which meets line CC of (b). FIG. 2 is a plan view illustrating an example of a mounted state of the multilayer capacitor 21 illustrated in FIG. 1. FIG. 7 is a diagram for explaining samples according to an example and a comparative example manufactured in an experimental example carried out to confirm the effect of the present invention, and (a) shows an LT of the capacitor main body 51 common to the example and the comparative example. It is a figure which shows a cross section, (b1) is a figure which shows the LW cross section of the capacitor | condenser main body 51 which concerns on an Example, (b2) is a figure which shows the LW cross section of the capacitor | condenser main body 51 which concerns on a comparative example. It is a figure which shows the S21 passage characteristic about the multilayer capacitor which concerns on each of the Example produced in the experiment example, and a comparative example. It is a figure corresponding to Drawing 1 (c) showing multilayer capacitor 61 by other embodiments of this invention. FIG. 1 shows a conventional multilayer capacitor 1 of interest to the present invention, in which (a) is a surface view showing the appearance of the multilayer capacitor 1 and (b) shows a specific internal structure to show the internal structure of the multilayer capacitor 1. It is the front view shown with the cross section which the electrode 3 passes, (c) is sectional drawing which follows the line CC of (b). It is a top view which shows an example of the mounting state of the multilayer capacitor 1 shown in FIG.

  FIG. 1 is a view corresponding to FIG. 6 described above, and shows a multilayer capacitor 21 according to an embodiment of the present invention. More specifically, in FIG. 1, (a) is a front view showing the appearance of the multilayer capacitor 21, and (b) shows a cross section through which a specific internal electrode passes in order to show the internal structure of the multilayer capacitor 1. (C) is sectional drawing which follows the line CC of (b).

  As in the case of the multilayer capacitor 1 shown in FIG. 6, the multilayer capacitor 21 forms a capacitance by facing a plurality of stacked dielectric layers 22 and a specific dielectric layer 22 therebetween. The capacitor body 25 has a rectangular parallelepiped shape and includes a plurality of sets of first and second internal electrodes 23 and 24 respectively formed along a specific interface between the dielectric layers 22. When the multilayer capacitor 21 is a multilayer ceramic capacitor, the above-described dielectric layer 22 is made of a dielectric ceramic.

  In FIG. 1B, as in FIG. 6B, the first internal electrode 23 indicated by a solid line and the second internal electrode 24 indicated by a broken line are shown in a slightly shifted state. However, this is only a convenient means for allowing the illustration of both the first and second internal electrodes 23 and 24, and in practice the first internal electrode 23 and the second internal electrode 23 Ideally, the electrode 24 completely overlaps.

  The multilayer capacitor 21 also includes first and second terminal electrodes 26 and 27 formed on the outer surface of the capacitor body 25. The first and second internal electrodes 23 and 24 are respectively the first and second capacitance forming portions 28 and 29 that contribute to capacitance formation, and the first and second capacitance forming portions 28 and 29, respectively. And first and second lead portions 30 and 31 which are drawn from the terminal and connected to the first and second terminal electrodes 26 and 27, respectively.

1A and 1B, the mounting surface 32 is indicated by an imaginary line. At least a part of each of the first and second terminal electrodes 26 and 27 is formed on a facing surface 33 of the capacitor body 25 that faces the mounting surface 32. When the surface parallel to the surface direction of the first and second internal electrodes 23 and 24 on the outer surface of the capacitor body 25 is the end surface 42, each of the first and second terminal electrodes 26 and 27 is As shown in FIG. 1 (c), it is formed so as to reach from the facing surface 33 to the end surface 42. In this embodiment, each of the first and second terminal electrodes 26 and 27 is formed on the facing surface 33 so as to extend from one end to the other end in the stacking direction of the capacitor body 21.

As well shown in FIG. 1 (c), a plurality of sets of first and second internal electrodes 23 and 24 are provided by at least one set of first and second internal electrodes 23 and 24, respectively. The capacitor units 34 and 35 are configured. The two capacitor units 34 and 35 are located between each other with a gap 36 wider than the gap between the first and second internal electrodes 23 and 2 constituting each capacitor unit 34 and 35, Thereby, the distribution region D as a whole of the first and second internal electrodes 23 and 24 in the stacking direction of the capacitor body 25 is expanded. In this embodiment, the capacitor units 34 and 35 are disposed at respective end portions of the capacitor body 25 in the stacking direction. The distance 36 between the two capacitor units 34 and 35 is the largest on the second end face 43 compared to the distance between the capacitor unit 34 closest to the first end face 42 and the first end face 42. The distance between the near capacitor unit 35 and the second end face 43 is also wide.

  FIG. 2 is a diagram corresponding to FIG. 7 described above, and is a plan view showing an example of a mounted state of the multilayer capacitor 21. FIG. In FIG. 2, the multilayer capacitor 21 is illustrated with the same expression method as the multilayer capacitor 1 in FIG. 7.

  The mounting surface 32 described above is provided by the wiring substrate 37, and first and second signal lines 38 and 39 are formed on the mounting surface 32.

  The multilayer capacitor 21 has a posture in which the capacitor body 25 is directed so that the surface direction of the first and second internal electrodes 23 and 24 is orthogonal to the mounting surface 32, and the first and second terminal electrodes 26 and 27 are arranged. Are surface-mounted while being electrically connected to first and second conductive lands 40 and 41 formed at the ends of the first and second signal lines 38 and 39, respectively. In particular, in the configuration shown in FIG. 2, the dimensions of the first and second conductive lands 40 and 41 are the dimensions of the first and second terminal electrodes 26 and 27 with respect to the dimensions measured in the stacking direction of the capacitor body 25. It is almost equivalent to the dimensions.

  As described above, since the distribution region D as the whole of the internal electrodes 23 and 24 is widened, when the internal electrode group composed of the plurality of internal electrodes 23 and 24 is regarded as one signal line, this signal line The width of becomes wide. Therefore, the current concentration at the connection portion between each of the terminal electrodes 26 and 27 and the internal electrodes 23 and 24 is alleviated. As a result, a good impedance matching state is obtained, and reflection of the signal here is suppressed. Loss due to reflection can be reduced.

  Next, experimental examples carried out to confirm the effect of the multilayer capacitor according to the present invention will be described. In this experimental example, a sample according to an example in which a configuration basically similar to that of the multilayer capacitor 21 shown in FIG. 1 was adopted and a configuration in which a configuration basically similar to that of the multilayer capacitor 1 shown in FIG. 6 was adopted was compared. Samples according to examples were prepared.

  In FIG. 3, a capacitor main body 51 provided in the multilayer capacitor, an internal electrode 54 having a capacitance forming portion 52 and a lead portion 53, and a terminal electrode 55 are shown. 3A shows an LT cross section of the capacitor main body 51 common to the examples and the comparative example, FIG. 3B 1 shows an LW cross section of the capacitor main body 51 according to the example, and FIG. The LW section of capacitor body 51 concerning a comparative example is shown. In these FIGS. 3 (a), (b1) and (b2), numerical values (unit: mm) indicating the dimensions of the respective parts are entered.

  In this experimental example, in common with the examples and comparative examples, the dielectric constant of the dielectric constituting the dielectric layer is 2500, nickel is used as the conductive component of the internal electrode 54, and copper is used as the conductive component of the terminal electrode 55. Was used.

  Further, in common with the examples and comparative examples, the number of internal electrodes was set to 12, while in the example, the number of internal electrodes constituting each capacitor unit was set to 6.

  The multilayer capacitors according to each of the examples and comparative examples as described above are mounted so as to be connected to a signal line having a width of 0.45 mm in a state as shown in FIG. 2 or FIG. Characteristics were measured. Here, the signal line was formed on a wiring board having a relative dielectric constant of 2.6 and a thickness of 0.2 mm so as to have a characteristic impedance of 50Ω. The characteristics of the DC cut capacitor were S21 pass characteristics up to 50 GHz using a network analyzer high frequency measuring instrument.

  The result is shown in FIG. In FIG. 4, the characteristics of the example are indicated by solid lines, and the characteristics of the comparative example are indicated by broken lines.

  As can be seen from FIG. 4, in the comparative example, a valley peak of −1.25 dB occurs at 5 GHz. On the other hand, in the example, a valley peak at 5 GHz is not recognized, and has a characteristic of lowering to the right. In addition, at 10 GHz or more, no substantial difference is recognized between the example and the comparative example.

  As is clear from the experimental examples as described above, according to the example, the concentration of current at the connection portion between the internal electrode and the terminal electrode, and further at the connection portion with the conductive land in the signal line is alleviated and good. Since impedance matching is obtained and signal reflection is reduced, the generation of an extreme valley peak at 10 GHz or less can be suppressed in the S21 pass characteristic.

  FIG. 5 is a view corresponding to FIG. 1C, showing a multilayer capacitor 61 according to another embodiment of the present invention. In FIG. 5, elements corresponding to those shown in FIG. 1C are denoted by the same reference numerals, and redundant description is omitted.

The multilayer capacitor 61 shown in FIG. 5 is characterized in that a plurality of sets of first and second internal electrodes 23 and 24 are divided so as to constitute three capacitor units 62, 63 and 64. . In this embodiment, the interval between the three capacitor units 62, 63 and 64 is closer to the end surface 42 than the interval between the capacitor unit 62 closest to the end surface 43 and the end surface 43. The distance between the end face 42 and the end face 42 is also wide.

  As can be seen from the embodiment shown in FIG. 5, the internal electrodes may be divided so as to constitute four or more capacitor units.

21, 61 Multilayer capacitor 22 Dielectric layer 23, 24, 54 Internal electrode 25, 51 Capacitor body 26, 27, 55 Terminal electrode 32 Mounting surface 33 Opposing surface 34, 35, 62, 63, 64, Capacitor unit 36 Distance 38, 39 Signal line 40, 41 Conductive land
42, 43 End face D Distribution region of internal electrodes in stacking direction

Claims (2)

A plurality of sets of dielectric layers that are stacked, and a plurality of sets each formed along a specific interface between the dielectric layers so as to form a capacitance by facing each other through the specific dielectric layer A rectangular parallelepiped capacitor body composed of first and second internal electrodes;
First and second terminal electrodes formed on the outer surface of the capacitor body and electrically connected to the first and second internal electrodes, respectively.
The capacitor body is oriented so that the surface direction of the first and second internal electrodes is orthogonal to the mounting surface, and the first and second terminal electrodes are formed on the mounting surface. A multilayer capacitor directed to a surface-mounted application electrically connected to each of the first and second signal lines,
The plurality of sets of first and second internal electrodes constitute a plurality of capacitor units respectively provided by at least one set of the first and second internal electrodes,
The plurality of capacitor units are positioned at a distance between each other that is wider than the distance between the first and second internal electrodes constituting each of the capacitor units. The distribution area as a whole of the first and second internal electrodes in the stacking direction is widened;
The outer surface of the capacitor body has a facing surface facing the mounting surface and first and second end surfaces parallel to the surface direction of the first and second internal electrodes,
Spacing between the plurality of the capacitor unit, the even compared to the spacing between the first nearest the capacitor unit on the end face and the first end face, nearest the capacitor unit to the second end face Compared to the distance between the second end face and the second end face ,
The first and second terminal electrodes are formed on the facing surface,
Each of the first and second terminal electrodes is formed so as to reach the end surface from the facing surface.
Multilayer capacitor.   The plurality of sets of first and second internal electrodes constitute two capacitor units, and each of the capacitor units is disposed at each end in the stacking direction of the capacitor body, respectively. The multilayer capacitor according to Item 1.

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