TW498373B - Multilayer ceramic capacitor for three-dimensional mounting - Google Patents

Multilayer ceramic capacitor for three-dimensional mounting Download PDF

Info

Publication number
TW498373B
TW498373B TW89128033A TW89128033A TW498373B TW 498373 B TW498373 B TW 498373B TW 89128033 A TW89128033 A TW 89128033A TW 89128033 A TW89128033 A TW 89128033A TW 498373 B TW498373 B TW 498373B
Authority
TW
Taiwan
Prior art keywords
aforementioned
ceramic
capacitor
layer
ceramic layer
Prior art date
Application number
TW89128033A
Other languages
Chinese (zh)
Inventor
Taisuke Ahiko
Masaaki Togashi
Original Assignee
Tdk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tdk Corp filed Critical Tdk Corp
Priority to TW89128033A priority Critical patent/TW498373B/en
Application granted granted Critical
Publication of TW498373B publication Critical patent/TW498373B/en

Links

Landscapes

  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Ceramic Capacitors (AREA)

Abstract

A multiterminal multilayer ceramic capacitor having a capacitor body comprised of first internal electrodes and second internal electrodes alternately stacked via rectangular ceramic layers so that the short sides of the ceramic layers register with the height direction of the capacitor body. First external terminals and/or second external terminals connected to the first internal electrodes and/or second internal electrodes are formed on a top face and bottom face of the capacitor body. The first external terminals and second external terminals are connected directly to different circuit patterns of the circuit board so as to enable three-dimensional mounting of the multilayer ceramic capacitor with circuit boards.

Description

49^/J 五、發明說明(υ _____ 發明領域: 本發明係有關於一種 ^ 用以安裝於個人電腦或里仏^立體安裝之積層陶瓷電容, 為一低等效串聯電感USi、他具有高動作頻率的電子裝置而 旦適用於表面安裝於一今與低等效串聯電阻(ESR)電容, 、 二幾多層印製電路基板。 習知技術說明: 過去,做為多端子 ^ 利第588 0925號中的電容^陶瓷電容,例如揭示於美國專 容本體,具有兩型内部^電糸為已知的。這種電容具有一電 電極,以及積層且夾在其=,即第一内部電極與第二内部 甴延#於縱向在長方形g ^的誘電層。這些内部電極分別 以及從主要部的铡面延伸=層,面上之長方形主要部圖樣 樣所構成。第一内部兩柘乏陶瓷層的侧面之複數導引部圖 導引部圖樣由平面圖=男的導引部圖樣與第二内部電極的 外部電極係構成於此一/,構成於彼此不同的位置。複數 長短倒之谢面。 夕智子積層陶瓷電容之電容本體的 此一多端子積屉49 ^ / J V. Description of the invention (υ _____ Field of the invention: The present invention relates to a multilayer ceramic capacitor which is used for installation in a personal computer or a three-dimensional installation. It is a low equivalent series inductance USi. The electronic device with an operating frequency is suitable for surface-mounted and low-equivalent series resistance (ESR) capacitors, two or more multilayer printed circuit boards. Known technical description: In the past, it was used as a multi-terminal ^ 588 0925 The capacitor ^ ceramic capacitor, for example, is disclosed in the United States of America. It is known that it has two types of internal capacitors. This capacitor has an electrical electrode, and it is laminated and sandwiched between =, that is, the first internal electrode and第二 内 甴 延 # is in the longitudinal direction of the rectangular electromotive layer. These internal electrodes are respectively extended from the main surface of the main surface = layer, and the main surface of the rectangular main portion is composed of patterns. The first two internal ceramic layers are devoid of ceramic layers. The guide pattern on the side of the guide is composed of a plan view = the guide pattern of the male and the external electrode system of the second internal electrode in this one, and is formed at different positions from each other. Thanks for the length of the plural This plot more than one drawer Tokyo Tomoko terminal multilayer ceramic capacitor of the capacitor body,

得外部電極係位於從雷容係位於電路基板的表面,使 電極的積層方向與陶基板的表面之一直立方向。内部 極係以烊接於命=:〜§ '系大體垂直於電路基板。外部電 以將電容C反的電路圖樣之焊墊而結合且固定, 貧了 Ί ;電路基板的表面。 層的積:方:J 2層陶瓷電容中,由於内部電極與陶£ —方间係與用於表面安裝之電容的高度方向一致,The external electrode system is located on the surface of the circuit board from the lightning capacity system, so that the lamination direction of the electrodes is perpendicular to the surface of the ceramic substrate. The internal poles are connected to the electrode =: ~ § 'The system is generally perpendicular to the circuit substrate. The external power is combined and fixed by the pads of the circuit pattern of the capacitor C, which is lean; the surface of the circuit board. Layer Product: Square: In a 2-layer ceramic capacitor, the internal electrode and ceramic are in the same height direction as the capacitor used for surface mounting.

498373 五、發明說明(2) 若積層陶变層 置的南度無法 值得注意 置的高度方向 除了美國專利 示於日本特公 公報、日本特 號公報、曰本 8-1 24800 號公 平6-7228號公 昭62-35257 號 在由使陶瓷層 而羯於表面安 數量由所需之 度保持低的問 然而,在 500 兆赫(MHz) ESL與低ESR的 越小的尺寸, 確實安裝於立 定特性。 然而,若 立體積層印製 樣變得更長, --Ί 的數里由所讀之電性特徵而增加,則電子裝 保持在低的狀況。 的是’由使陶瓷層的積層方向與積層電子裝 一致而做為甩於表面安裝的積層電子裝置, 第5 8 8 0 9 2 5號之外,還有很多習知,例如揭 昭6 4 -1 〇 9 2 7號公報、日本特開平7 — ί 6 ί 5 6 8號 知平7 -1 6 9 6 4 9號公報、日本特開平7 — ί 6 9 6 5 1 特開平7 - 2 7 2 9 7 5號公報、日本特開平 報、曰本特開平9-1 481 74號公報、日本實開 報、曰本特開平7 —丨6 1 568號公報、曰本特公 公報、以及日本特公昭63-38856號公報中。 的積層方向舆積層電子裝置的高度方向一致 ^的積層電子裝置中,有著若積層陶瓷層的 包性特徵而增加,則不可能將電子裝置的高 題。 個人電腦與其他電子裝置中,動作頻率已從 增加至1仟兆赫(G Η z )。電源電路需要一低 ^層,瓷電容。另外,考慮到電子裝置越來 保持高度尺寸較低的多端子積層陶瓷電容可 體印製的電路基板等等,且得到所要求的既 ^體安裝一習知的多端子積層陶瓷電容於一 二路基板等等,構成於電路基板上的電路圖 主而焊墊的繞道變得更長,而對電感元件有498373 V. Description of the invention (2) If the south of the laminated ceramic deformation layer cannot be set to a height direction that is worth noting, except for the US patents shown in Japanese Patent Publication, Japanese Patent Publication, Japanese 8-1 24800 Fair 6-7228 No. Sho 62-35257 keeps the ceramic layer on the surface and the number of amps is kept low by the required degree. However, the smaller the size of the 500 megahertz (MHz) ESL and the low ESR, it is indeed installed in the standing characteristics. However, if the volumetric printed samples become longer, the number of Ί is increased by the electrical characteristics read, and the electronic device remains low. The thing is that the laminated electronic device that is thrown on the surface is made by making the laminated direction of the ceramic layer consistent with the laminated electronic device. There is a lot of knowledge outside No. 5 8 8 0 9 2 5 such as Jie Zhao 6 4 -1 〇9 2 Gazette No. 7, Japanese Patent Laid-Open No. 7 — ί 6 ί 5 6 8 Chihpeung No. 7 -1 6 9 6 4 9 Gazette, Japanese Laid-Open Patent No. 7 — ί 6 9 6 5 1 No. 7 2 9 7 No. 5, Japanese Patent Laid-Open, No. 9-1 481 No. 74, Japan Shikai No. 7, No. 6 1 568, No. 1 568, No. 1 568, and Japanese Patent Publication No. 63-38856. In the laminated electronic device, the height direction of the laminated electronic device is the same. ^ In the laminated electronic device, if the inclusion characteristics of the laminated ceramic layer are increased, it is impossible to make the electronic device a problem. In personal computers and other electronic devices, the operating frequency has been increased from 1 仟 megahertz (G Η z). The power circuit requires a low-layer, ceramic capacitor. In addition, taking into account that electronic devices are increasingly maintaining low-profile multi-terminal multilayer ceramic capacitors that can be printed on circuit boards, etc., and obtain the required multi-layer multilayer ceramic capacitors that are conventionally installed in one or two Circuit boards, etc., the circuit diagrams formed on the circuit board are main and the routing of the bonding pads becomes longer, while the inductance components have

Η 2030-3679-P.ptd 第6頁Η 2030-3679-P.ptd Page 6

498373498373

五、發明說明(3) 不良的影響。特別是包括在上部位置的焊墊與 而 的焊塾之電路圖樣變得更長,的繞道變得更π 電感元件有不良的影響,而無法避免噪音的產生i 一式 另外,若表面安裝習知電容於接近一半導體蓉的嫣 子,以降低ESL,則有由於焊墊的繞道不能省略而造成電 感元件之效應的問題。另外,在習知電容中,如前所述, 無論積層數量為何,電容本身的高度尺寸都無法保持低。 由此可知,習知電容不適用於立體安裝。 值得注意的是’如日本特開昭第57 —6〇827號公報(對 應於美國專利第167191號,198〇年7月9日)與日本特許第 2657953號公報(對應於美國專利第212361號,-} 988年6月 27=)所不,提出一種電容,使陶瓷層的積層方向與積層 肩=電今欲表面安裝之電路基板的平面方向一致。然而5 報中揭示的電容具有電容不能被立體安裝,且連 才文於弘谷之外部電路的ESR與/或esl容易變大的問題。 發明概述: 雷贫1發明之一目的係提供一種用於立體安裝之積層陶瓷 ί ΐ置f Γ於安裝在個人電腦或其他具有高動作頻率的電 量:ί 3傲ί 一低ESL與低esr的電容,且不管陶兗層的數 印製略奋5午局度尺寸保持低,且適用於安裝於一立體積層 • ’电路基板。 層5以一名+ 長方形構 曰的 本發明之第一電容包括一陶瓷 第一内部電極,具有沿陶瓷層之V. Description of the invention (3) Adverse effects. In particular, the circuit pattern including the pads at the upper position and the solder pads becomes longer, and the detour becomes more π. Inductive elements have an adverse effect, and the generation of noise cannot be avoided. In addition, if surface mounting is known If the capacitor is close to a semiconductor chip to reduce ESL, there is a problem that the effect of the inductive element is caused because the routing of the pad cannot be omitted. In addition, in the conventional capacitor, as described above, the height dimension of the capacitor itself cannot be kept low regardless of the number of layers. It can be seen that the conventional capacitor is not suitable for three-dimensional installation. It is worth noting that, for example, Japanese Unexamined Patent Publication No. 57-6827 (corresponding to US Patent No. 167191, July 9, 1980) and Japanese Patent No. 2657953 (corresponding to US Patent No. 212361 ,-} June 27, 988 =) No, a capacitor is proposed to make the direction of lamination of the ceramic layer coincide with the plane direction of the circuit board on which the lamination shoulder = the surface to be mounted. However, the capacitors disclosed in the 5th report have problems that the capacitors cannot be installed three-dimensionally, and the ESR and / or esl connected to the external circuit of Honggu is easily increased. Summary of the Invention: One of the objects of Thunderhead 1 invention is to provide a multilayer ceramic for three-dimensional installation, where f Γ is installed on a personal computer or other electric power with a high operating frequency: 3 A low ESL and low esr Capacitors, regardless of the number of printed layers of the ceramics, are kept slightly smaller, and the dimensions are kept low, and they are suitable for mounting on a single volume layer. The layer 5 is formed by a + rectangle. The first capacitor of the present invention includes a ceramic first internal electrode having

第7頁 498373 五、發明說明(4) ^ 第一面於縱方向延伸的長方形第一主要部,且具有從第一 - ;主要部之長邊延伸至陶瓷層之長邊的複數第一導引部;一 :· * 丨第二内部電極,具有與第一内部電極之第一主要部經由陶 | I瓷層相對並位於與第一面相對的陶瓷層之第二面的長方形jPage 7 498373 V. Description of the invention (4) ^ The first side of the rectangular first main part extending in the longitudinal direction has a plurality of first leads extending from the first side of the main part to the long side of the ceramic layer. Leading part; one: · * 丨 a second internal electrode having a rectangle j opposite to the first main part of the first internal electrode via the ceramic | I ceramic layer and located on the second surface of the ceramic layer opposite the first surface

I第二主要部,旦具有從第二主要部之長邊在與設置於第一 I i内部電極之第一導引部不同位置延伸至陶瓷層之長邊的複 j數第二導引部;一長方形六面體狀電容本體,包括複數第 | I 一内部電極以及第二内部電極藉由陶瓷層積層,使得陶瓷i I層的短邊與電容本體的高度方向一致;第一外部電極,構iThe second main portion has a plurality of second guide portions extending from the long side of the second main portion to the long side of the ceramic layer at a different position from the first guide portion provided on the first internal electrode. ; A rectangular hexahedron-shaped capacitor body, including a plurality of | I internal electrodes and a second internal electrode laminated with ceramics so that the short side of the ceramic i I layer is consistent with the height direction of the capacitor body; the first external electrode, I

5 I j成於電容本體之上面與下面,且分別電性連接於沿陶瓷層 丨 ! i ^ !之積層方向位於同一列的第一導引部;以及第二外部電 丨攀 極,對應於第一外部電極而交替地構成於電容本體之上面 | ·5 I j is formed on the upper and lower sides of the capacitor body, and is electrically connected to the first guide portion located in the same row along the multilayer direction of the ceramic layer 丨! I ^!; And the second external electric pole, corresponding to The first external electrode is alternately formed on the capacitor body |

I 與下面,且分別電性連接於沿陶瓷層之積層方向位於同一 | · 列的第二導引部。 | | 本發明的第一電容中,最好第一外部電極係連接於電 |I and the bottom, and are respectively electrically connected to the second guide portions located in the same | · row along the lamination direction of the ceramic layer. | | In the first capacitor of the present invention, it is preferable that the first external electrode is connected to the electric |

|容本體外侧的第一電路圖樣,旦第二外部電極係連接於與 I| The first circuit pattern on the outside of the main body, once the second external electrode is connected to I

I第一電路圖樣不同的第二電路圖樣。 II The second circuit pattern is different from the first circuit pattern. I

I I 本發明的第一電容中5最好積層陶瓷電容係埋設於一 i立體電路基板中。 ! I 根據本發明之第一電容,可縮短電容本體的高度尺寸 丨| 而不管陶瓷層積層的數量。因此,可縮短構成於電容本體 | ¥ 上面的外部電極與構成於下面的外部電極之間的距離,且 jI I Among the first capacitors of the present invention, five laminated ceramic capacitors are preferably buried in an i-dimensional circuit substrate. ! I According to the first capacitor of the present invention, the height dimension of the capacitor body can be shortened regardless of the number of ceramic laminates. Therefore, the distance between the external electrode formed on the capacitor body | ¥ and the external electrode formed on the lower side can be shortened, and j

丨可減少由於焊墊繞道而產生的總電感,即使電容係位於一 I ί多層基板上。另外,構成於多層基板的焊墊可簡化。因 -丨 can reduce the total inductance due to the pad routing, even if the capacitor is located on a multilayer substrate. In addition, the pads formed on the multilayer substrate can be simplified. Because-

2030-3679-P.ptd 第8頁 498373 i五、發明說明(5) ] I此,電容適兩於安裝於個人電臑或其他具有高動作頻率的 s j電子裝置而為一低ESL與低ESR的電容。另外,電容係構成 j具有一低高度尺寸,且具有在電容上下面的電極5故適用 I於埋設安裝於一立體多層印製電路基板。 i I 本發明之第二電容包括一陶瓷層,以一長方形構成;j I 一第一内部電極,具有沿陶瓷層之第一面於縱方向延伸的j r ί I長方形第一主要部,且具有沿陶瓷層之第一長邊而暴露的 j I第一主要部之第一長邊;一第二内部電極,具有沿與第一 | j面相對的陶瓷層之第二面於縱方向延伸的長方形第二主要| i部,且具有沿陶瓷層之第二長邊而暴露的第二主要部之第|2030-3679-P.ptd Page 8 498373 i V. Description of the invention (5)] Here, the capacitor is suitable for installation in personal electronic devices or other sj electronic devices with high operating frequency, and has a low ESL and low ESR Capacitor. In addition, the capacitor system configuration j has a low height dimension and has electrodes 5 above and below the capacitor, so it is suitable for being embedded and mounted on a three-dimensional multilayer printed circuit board. i I The second capacitor of the present invention includes a ceramic layer composed of a rectangular shape; j I a first internal electrode having a jr rectangular first main portion extending in a longitudinal direction along a first surface of the ceramic layer and having The first long side of the first main part of j I exposed along the first long side of the ceramic layer; a second internal electrode having a longitudinal direction extending along the second side of the ceramic layer opposite to the first | j plane Rectangular second main part | Section i having a second main part exposed along the second long side of the ceramic layer |

i二長邊;一長方形六面體狀電容太體,包括複數第一内部 | 1 ^ j電極以及第二内部電極藉由陶瓷層積層,使得陶瓷層的短 i ;邊與電容本體的高度方向一致;第一外部電極,構成於電 |i two long sides; a rectangular hexahedron-shaped capacitor body including a plurality of first internal | 1 ^ j electrodes and a second internal electrode by ceramic lamination to make the ceramic layer short i; the side and the height direction of the capacitor body Consistent; the first external electrode, constituted by electricity |

容本體之上面或下面,且分别電性連接於沿陶瓷層之第一 I ! _ iAbove or below the container body, and are electrically connected to the first I along the ceramic layer, respectively!

I長邊暴露的第一内部電極;以及第二外部電極,構成於電· I ί ? j容本體之上面或下面,且分别電性連接於沿陶瓷層之第二 | j長邊暴露的第二内部電極。 | I 本發明的第二電容中,最好第一外部電極係連接於電iA first internal electrode exposed on the long side of I; and a second external electrode formed above or below the capacitor body, and are respectively electrically connected to the second | j exposed on the long side of the ceramic layer Two internal electrodes. | I In the second capacitor of the present invention, it is preferable that the first external electrode is connected to the electric i

容本體外側的第一電路圖樣,且第二外部電極係連接於與 第一電路圖樣不同的第二電路圖樣。 本發明的第二電容中,最好積層陶瓷電容係埋設於一 |The first circuit pattern on the outside of the main body is accommodated, and the second external electrode is connected to a second circuit pattern different from the first circuit pattern. In the second capacitor of the present invention, it is preferable that the multilayer ceramic capacitor is buried in a |

i立體電路基板中。 Ii stereo circuit board. I

I 本發明的第二電容顯示與本發明的第一電容類似的動I i作與效應。 丨I The second capacitor of the present invention exhibits similar operation and effects as the first capacitor of the present invention.丨

2030-3679-P.ptd 第9頁 498373 ! ----- I五、發明說明(6) δ ! 本發明之第三電容包括一陶瓷層,以一長方形構成; 一第一内部電極,具有沿陶瓷層之第一面於縱方向延伸的 長方形第一主要部,且具有沿陶瓷層之第一長邊而暴露的 第一主要部之第一長邊;一第二内部電極,具有沿與第一 !面相對的陶瓷層之第二面於縱方向延伸的長方形第二主要 !部,且具有從第二主要部之第二長邊延伸至陶瓷層之第二 長邊的複數導引部;一長方形六面體狀電容本體,包括複 數第一内部電極以及第二内部電極藉由陶瓷層積層,使得 陶瓷層的短邊與電容本體的高度方向一致;一第一外部電 I極,構成於電容本體之上面或下面5且電性連接於沿陶瓷 I層之第一長邊暴露的第一内部電極;以及第二外部電極, I構成於電容本體之上靣或下面,且分別電性連接於沿陶瓷 |層之第二長邊暴露的導引部。 本發明的第三電容中,最好複數第二外部電極係以一 大體相當於陶瓷層的短邊之距離配置於電容本體的上面或 j 下面。 j 本發明的第三電容中,最好第一外部電極係連接於電 1容本體外側的篱一電路圖樣,且第二外部電極係連接於與 1 * !第一電路圖樣不同的第二電路圖樣。 本發明的第三電容中,最好積層陶瓷電容係埋設於一 立體電路基板中。 j 本發明的第三電容顯示與本發明的第一電容類似的動 I作與效應,且由以一大體相當於陶瓷層的短邊之距離配置 丨一對第二外鄯電極於電容本體的上面或下面可容許三端子2030-3679-P.ptd Page 9 498373! ----- I. V. Description of the invention (6) δ! The third capacitor of the present invention includes a ceramic layer formed of a rectangle; a first internal electrode having A rectangular first main portion extending in a longitudinal direction along a first surface of the ceramic layer and having a first long side of the first main portion exposed along the first long side of the ceramic layer; a second internal electrode having The second face of the ceramic layer having a first face opposite to the second face extends in the longitudinal direction and has a plurality of guide portions extending from the second long side of the second main portion to the second long side of the ceramic layer. ; A rectangular hexahedral capacitor body, including a plurality of first internal electrodes and a second internal electrode, which are laminated with ceramics so that the short side of the ceramic layer is consistent with the height direction of the capacitor body; A first internal electrode that is exposed above or below the capacitor body and is electrically connected to the first long side of the ceramic I layer; and a second external electrode, I is formed above or below the capacitor body, and is electrically Connected to the second long-side storm along the ceramic | layer Exposed guide. In the third capacitor of the present invention, it is preferable that the plurality of second external electrodes are arranged above or below the capacitor body at a distance substantially equivalent to the short side of the ceramic layer. j In the third capacitor of the present invention, it is preferable that the first external electrode is connected to a circuit pattern on the outside of the capacitor body, and the second external electrode is connected to a second circuit different from the first circuit pattern. pattern. In the third capacitor of the present invention, it is preferable that the multilayer ceramic capacitor is embedded in a three-dimensional circuit substrate. j The third capacitor of the present invention exhibits similar operations and effects as the first capacitor of the present invention, and is arranged at a distance substantially equivalent to the short side of the ceramic layer. A pair of second outer electrodes are connected to the capacitor body. Three terminals allowed above or below

II

2030-3679-P.ptd 第10頁 498373 ^ j五、發明說明(7) j電容的實現 I第二外部電 裂於一多層 i多,且構成 | 本發明 I 一第一内部 j長方形第一 第一主要部 相對的陶£ 部,且具有 的一對導引 i 一内部電極 |層的短邊舆 j極,構成於 瓷層之長邊 I成於電容本 i邊暴露的導 j * j 本發明 |電容本體的 | 本發明 容本體外側 第一電路圖 I 本發明 。在本電容中,提供於陶瓷本體之相同早面的 極之間的節距可被縮短。因此,即使雷容俟‘ 基板,由於焊墊繞道而產生的總電感可減少^ 於多層基板的焊墊可簡化。 <第四電谷包括一陶曼層,以一長方形構成· 電極,具有沿陶瓷層之第一面於縱方向延伸的 ,要部,且具有沿陶瓷層之長邊而分別暴露的 <兩長邊,一第二内部電極,具有沿與第一荀 層之第二面於縱方向延伸的長方形第二主要 從第二主要部之短邊分別延伸至陶瓷層之短 部;一長方形六面體狀電容本體,包括複數笔 以及第二内部電極藉由陶瓷層積層, 之 電容本體的高度方向一致;一對第—C =本體之上面與下面’且電性連接於朝向陶 =的第-内部電極;以及第二外部電極,璁 ί: 且分別電性連接於朝向陶兗層之起 的第四電容中,最好第二外部電極以一 四侧面之全周面延伸。 Τ狀冷 的第四電容中,最好第一外部電極係達接於恭 的第-電路圖才卜且第二外部電極-接於: 樣不同的第二電路圖樣。 接於與 的第四電容中,最好積層陶瓷電容係埋設 498373 I五、發明說明(8)2030-3679-P.ptd Page 10 498373 ^ j V. Description of the invention (7) The realization of the j capacitor I The second external electric crack is in a multilayer i, and the composition | The present invention I a first internal j rectangle A first main part is opposite to the ceramic part, and has a pair of guides i an internal electrode | the short side of the layer and the j pole, which is formed on the long side I of the ceramic layer and is formed on the side of the capacitor i * j this invention | of the capacitor body | this invention the first circuit diagram of the capacitor body I this invention. In this capacitor, the pitch between the poles provided on the same early side of the ceramic body can be shortened. Therefore, even with Lei Rongjun's substrate, the total inductance due to the pad routing can be reduced ^ the pads on the multilayer substrate can be simplified. < The fourth electric valley includes a Taurman layer, which is composed of a rectangular electrode. The electrode has a main portion extending in a longitudinal direction along the first surface of the ceramic layer, and has a respective portion exposed along the long side of the ceramic layer. < Two long sides, a second internal electrode, having a rectangular shape extending in the longitudinal direction along the second surface of the first sacral layer. The second main portion extends from the short side of the second main portion to the short portion of the ceramic layer. The planar capacitor body includes a plurality of pens and a second internal electrode laminated by ceramics, and the height direction of the capacitor body is the same; a pair of -C = above and below the body, and are electrically connected to the direction of Tao = -An internal electrode; and a second external electrode, which are electrically connected to the fourth capacitor facing the ceramics layer, respectively, and it is preferable that the second external electrode extends on the entire peripheral surface of the four sides. In the T-shaped cold fourth capacitor, it is preferable that the first external electrode is connected to the first circuit diagram of Gong and the second external electrode is connected to the second circuit pattern with a different shape. Connected to the fourth capacitor, the best multilayer ceramic capacitor is buried 498373 I V. Description of the invention (8)

I I 本發明的第四電容中,最好第一外部電極與第二外部 i電極係直接連接於構成於立體電路基板的電路圖樣中。j 本發明的第四電容顯示與本發明的第一電容類似的動| 作與效應,且更可實現三端子電容。另外,當經由立體電 | |路基板的一既定電路圖樣提供電容,且將其做為所謂的通 jI I In the fourth capacitor of the present invention, it is preferable that the first external electrode and the second external i electrode are directly connected to a circuit pattern formed on the three-dimensional circuit substrate. j The fourth capacitor of the present invention shows similar operations and effects as the first capacitor of the present invention, and a three-terminal capacitor can be realized. In addition, when a capacitor is provided via a predetermined circuit pattern of a three-dimensional circuit board, and it is used as a so-called through j

I孔型電容使兩時,構成於電容本體侧面的第二外部電極係I i可直接連接至所經過的電路圖樣。 |The I-hole capacitor allows the second external electrode system I i formed on the side of the capacitor body to be directly connected to the passing circuit pattern. |

I 為使本發明之上述及其他目的、特徵和優點能更明顯 ! 易懂,下文特棗一較佳實施例,並配合所附圖式做詳細說 丨明。 .I In order to make the above and other objects, features, and advantages of the present invention more obvious! It is easy to understand, a preferred embodiment is described below, and described in detail with the accompanying drawings. .

I j圖式簡單說明: 丨I j schema brief description: 丨

I 第1圖係根據本發明第一實施例中周於立體安裝之多 I i端子積層陶瓷電容顯示内部結構狀態的立體圖; j I 第2圖係根據本實施例中構成用於立體安裝之多端子 |I FIG. 1 is a perspective view showing the state of the internal structure of the multi-layered ceramic capacitors in the three-dimensional installation according to the first embodiment of the present invention; j I FIG. Terminal |

積層陶瓷電容的内部電極之圖樣形狀的說明圖; I 第3圖係根據本實施例中包括用於立體安裝之多端子 | 積層陶瓷電容的外部電極之外觀的立體圖; i 1 第4圖係根據本實施例中用於立體安裝之多端子積層 | \ εIllustrative drawing of the shape of the internal electrode of the multilayer ceramic capacitor; I FIG. 3 is a perspective view of the appearance of the external electrode of the multilayer ceramic capacitor including multi-terminal for three-dimensional installation according to this embodiment; i 1 FIG. 4 is based on Multi-terminal laminate for stereo mounting in this embodiment | \ ε

陶瓷電容在一多層基板中夾擠安裝結構的說明圖; |Illustrative drawing of a ceramic capacitor sandwiching a mounting structure in a multilayer substrate; |

第5圖係根據本發明另一實施例中罔於立體安裝之多 I I端子積層陶瓷電容的立體圖; jFIG. 5 is a perspective view of a multi-layer I / I laminated ceramic capacitor in a three-dimensional installation according to another embodiment of the present invention; j

| 第6圖係根據本實施例中構成用於立體安裝之多端子 IFig. 6 shows a multi-terminal for three-dimensional mounting according to the embodiment I

i積層陶瓷電容的内部電極之圖樣形狀的說明圖; Ii An illustration of the shape of the internal electrodes of a multilayer ceramic capacitor; I

2030-3679-P.ptd 第12頁2030-3679-P.ptd Page 12

/J 五、發明說 ~- *---* 篇7圖係根據本實施例中用於立體安裝之多端子積層 究5容在一多層基板中夾擠安裝結構的說明圖; ^ 一 Ϊ8圖係根據本實施例中周於立體安裝之多端子積層 陶九=各在一多層基板中埋設安裝結構的說明圖; $ 7第9圖係根據本發明另一實施例中用於立體安裝之三 端丁 f層陶瓷電容顯示内部結構狀態的立體圖; 第1 0圖係根據本實施例中構成用於立體安裝之三端子 @ S 3 1曼電容的内部電極之圖樣形狀的說明圖; 穑禺It圖係根據本實施例φ包括羯於立體安裝之三端子 、究電容的外部電極之外觀的立體圖; 陶莞雷2 本實施例中周於立體安裝之三端子積層 第η闻,夕層基板中夾擠安裝結構的說明圖; 孔型積層陶€兩& gg f ^ κ施例〒用於立體安裝之通 ^電谷的内部電極之圖樣形狀的传' i儿二 第1。圖係根據本實施例中包〜圖, 積層陶瓷電容的抓却汗上v L知用於立體安裝之竭孔刑 第!觀的立體圖; 陶兗電容在:用於立體安裝之通孔型⑽ '·夕層基板中夾擠安|結構的說明圖。層 符號說明: 2〇〜電容本體; 30〜夕山7 2〜陶瓷層; 夕端子積層陶瓷電容; L〜第一内部電極;/ J V. Invention ~~ * --- * Chapter 7 is an explanatory diagram of a multi-terminal multi-layer laminated structure for three-dimensional mounting in this embodiment, which is a sandwiched mounting structure in a multi-layer substrate; ^ 8 The diagram is a multi-terminal laminated ceramic pottery installed in a three-dimensional installation according to this embodiment = an explanatory diagram of each embedded installation structure in a multi-layer substrate; FIG. 9 is a diagram for three-dimensional installation according to another embodiment of the present invention The three-terminal D-layer ceramic capacitor is a perspective view showing the internal structure state; FIG. 10 is an explanatory diagram of the pattern shape of the internal electrode constituting the three-terminal @S 3 1-man capacitor for three-dimensional installation in this embodiment; 穑禺 It is a perspective view of the external appearance of the three-terminal three-terminally mounted capacitor and the external electrode of the capacitor according to this embodiment; Tao Wanlei 2 In this embodiment, the three-terminal laminated three-dimensionally mounted three-dimensionally mounted substrate is shown in the substrate. Illustrative drawing of the sandwich installation structure; hole-shaped laminated ceramics & gg f ^ κ Example 图 The shape of the internal electrode of the electric valley used for three-dimensional installation is transmitted. The figure is a perspective view of the laminated ceramic capacitor according to this embodiment, and it is a perspective view of the exhaust hole for stereoscopic installation. The ceramic capacitor is: a through-hole type for stereoscopic installation. '· Illustration diagram of the structure of the pinch pin in the substrate. Layer Symbol description: 20 ~ capacitor body; 30 ~ Xishan 7 2 ~ ceramic layer; Xi terminal multilayer ceramic capacitor; L ~ first internal electrode;

2030-3679-P.ptd 第13頁 498373 五、發明說明(ίο) 1 a〜第一主要部; 12〜第二内部電極; la’〜第二主要部; lb、lc、ld、le〜第一導引部; lb’ 、lc’ 、Id.,、le> 〜第二導引部 3b、3d、4a、4c〜第一夕卜部電極; 4d〜第二外部電極 6a 20V 201b 204 208 3 2 0〜電容本 3 0 2〜陶瓷層 209a、209b〜電路圖樣 3a 、 3c 、 4b 5〜電路基板; 1 2 0〜電容本體; 1 02〜陶瓷層; i 02b〜陶瓷層第二長邊; 101〜第一内部電極; 101b〜第一(上)長邊; 1 0 3〜第一外部電極; 105、106〜電路基板; 1 0 9〜焊料; 230〜積層陶瓷電容; 202a〜陶瓷層第二長邊; 2 02c、202d〜陶竟層短邊; 第二内部電極; 、201c〜導弓!部; 2 0 5〜第二外部電極; 6b〜電路圖樣; i30〜積層陶瓷電容; 102a〜陶瓷層第一長邊; 102c、102d〜陶竟層短邊 1 0 Γ〜第二内部電極; 101a〜第二(下)長邊; 104〜第二外部電極; 1 0 7、1 0 8〜電路圖樣; 2 2 0〜電容本體; 2 0 2〜陶瓷層; 202b〜陶瓷層第一長邊; 2 0 1 i〜第一内部電極; 2 0 i a〜第二主要部; 2 0 3〜第一外部電極; 2 0 6、2 0 7〜電路基板; 30〜通孔型積層陶瓷電容 02a、302b〜陶瓷層短邊;2030-3679-P.ptd Page 13 498373 V. Description of the invention (1) 1 a ~ first main part; 12 ~ second internal electrode; la '~ second main part; lb, lc, ld, le ~ first A guide portion; lb ', lc', Id., Le > ~ second guide portion 3b, 3d, 4a, 4c ~ first night electrode; 4d ~ second external electrode 6a 20V 201b 204 208 3 2 0 ~ Capacitor 3 0 2 ~ Ceramic layers 209a, 209b ~ Circuit patterns 3a, 3c, 4b 5 ~ Circuit substrate; 1 2 0 ~ Capacitor body; 102 ~ Ceramic layer; i 02b ~ Second long side of ceramic layer; 101 ~ First internal electrode; 101b ~ First (upper) long side; 103 ~ First external electrode; 105, 106 ~ Circuit board; 10 ~ Solder; 230 ~ Multilayer ceramic capacitor; 202a ~ Second ceramic layer Long side; 2 02c, 202d ~ short edge of Tao Jing layer; second internal electrode; 201c ~ guide bow! 2 05 ~ 2nd external electrode; 6b ~ circuit pattern; i30 ~ multilayer ceramic capacitor; 102a ~ first long side of ceramic layer; 102c, 102d ~ short edge of ceramic layer 10 0 Γ ~ second internal electrode; 101a ~ Second (lower) long side; 104 ~ Second external electrode; 107, 108 ~ Circuit pattern; 220 ~ Capacitor body; 202 ~ Ceramic layer; 202b ~ Ceramic layer first long side; 2 0 1 i ~ first internal electrode; 2 0 ia ~ second main part; 2 3 3 ~ first external electrode; 2 06, 2 7 7 ~ circuit board; 30 ~ through-hole multilayer ceramic capacitors 02a, 302b ~ Short side of ceramic layer;

2030-3679-P.ptd 第14頁 4983732030-3679-P.ptd p. 14 498373

3 01,〜第一内部電極; 301a〜第二主要部; I五'發明說明(li) | 302c、302d〜陶瓷層長邊 * | 30 12〜第二内部電極; I 301b、301c〜導引部; 3 0 4〜第二外部電極; 303、3 03’〜第一外部電極; 305、306〜電路基板; 07a 、 307b 、 308a 、 308b〜電路圖樣 較佳實施例的詳細說明: 第一實施例 之夕:第3圖所$ ’根據本實施例的两以立體安賠 ;層陶究電容30具有-電容本體2〇,4長方;: 容本體2°,如第2圖所示,係包括交替地:由、 ;崎層2積層於圖中水平方向之既定圖ΐ —巧電極11與第二内部電極12。也就是說ΐ 部電極12係經由㈣層2積層與第二内 短邊與電容本體20的高度方陶竟層的 構成的至少一陶瓷声可被積;致。庄思非由内部電極 面。 1尤層了被積層於本體2〇在積層方向的兩端 央’且具有複 ,從第一王要部la的長邊延 如第2圖所示,各第一内部命 主要部la,位於陶瓷層2的第^長方形的第一 數第一導引部1 b、1 c、1 d與1 e 、衣 伸至陶瓷層2的長邊。 邱1 /外S’/Λ二内部電極12具有相同形狀的-宾-主爱3 01, ~ first internal electrode; 301a ~ second main part; I5 'invention description (li) | 302c, 302d ~ long side of ceramic layer * | 30 12 ~ second internal electrode; I 301b, 301c ~ guide 3 0 4 ~ 2nd external electrode; 303, 3 03 '~ 1st external electrode; 305, 306 ~ circuit board; 07a, 307b, 308a, 308b ~ detailed description of the preferred embodiment of the circuit pattern: First implementation The evening of the example: Figure 3 shows the two-dimensional stereo compensation according to this embodiment; the layered ceramic capacitor 30 has-the capacitor body 20,4 rectangular;: the capacity body 2 °, as shown in Figure 2, The system consists of a predetermined pattern alternately formed by: 崎, 2; and 崎 layer 2 in the horizontal direction in the figure—the smart electrode 11 and the second internal electrode 12. That is to say, at least one ceramic sound composed of the sacral electrode 12 is laminated by the sacral layer 2 and the second inner short side and the high-level ceramic layer of the capacitor body 20, which can be integrated. Zhuang Sifei consists of internal electrode faces. 1 is layered on the main body 20 at both ends of the layering direction and has a complex, extending from the long side of the first king main part la as shown in FIG. 2, each first inner main part la is located at The first rectangular first guide portions 1 b, 1 c, 1 d and 1 e of the ceramic layer 2 extend to the long side of the ceramic layer 2. Qiu 1 / outer S ’/ Λ two internal electrodes 12 having the same shape

2030-3679-P.ptd " 面對於苐一内部電極%锋 .^ s 一主要 冲一主要部la經甴一陶瓷 4983732030-3679-P.ptd " Facing to the internal electrode% ^ s a main punch a main part la warp a ceramic 498373

層2在相對於陶瓷層2的表面之後面(第二面), 二主要部la,的長邊在與第一導引部^、lc、u盘有二= 位置延伸至陶瓷層2的長邊之複數第二導引。e,:、同 如第1圖與第4圖所示,電容本體20的上 |成有電性連接於沿陶瓷層2之積層方向位於同二列 二冓 I導引都lb、1c、id與le之第一外鄯電極3b、3 、 奏二 ° ^ 4 3 4 C ° 電容本體2 0的上面與下面係構成有電性連接於沿陶瓷 層2之積層方向位於同一列的第二導引部丨b, v 2 1 , 》 c H IQ 興Layer 2 is on the rear surface (second side) of the surface opposite to ceramic layer 2. The long sides of the two main portions la are at two positions from the first guide ^, lc, and u disk, and extend to the length of ceramic layer 2. The Plural Second Guide. e,:, as shown in Fig. 1 and Fig. 4, the upper part of the capacitor body 20 is electrically connected to the two layers in the same direction along the direction of the lamination of the ceramic layer 2. I guides lb, 1c, id ^ 4 3 4 C ° with the first external electrodes 3b, 3, and 2 of the le. The upper and lower sides of the capacitor body 2 are electrically connected to a second conductor located in the same row along the ceramic layer 2 stacking direction. Lead 丨 b, v 2 1,》 c H IQ Xing

ie 〜第二外部電極3a、3c、4b與4d。 也就是說,如第1圖與第4圖所示,第一外部電極3b、 3d、4a與4c以及第二外部電極3a、3c、4b與4d係配置於電 )容本體20的夕卜周彼此不同之位置。另外,第一外部電極 I 3b、3d、4a與4c係經由第一導引部lb〜le連接於層的第一 |内部電極,旦第二外部電極3a、3c、4b舆4d係經由第二 I導引部lb,〜le,連接於層的第二内部電極丨2。 I 這些内部電極1!與12係由塗佈或燒烤一鎳或其他導電 i性塗層於一陶瓷綠薄片之表面而構成,且包括鎳或鎳合金 |層等。注意内部電極也可包括基底金屬銅、貴金屬把或把 |銀合金層等等。 、 | 陶兗層2係包括一鋇鈦酸·鹽基、欽基、結酸鹽基、或 j其他陶瓷組成物。陶瓷層2與内部電極的積層係由塗佈一 陶土於一基底薄膜或其他薄膜表面構成,而成為一綠薄 片,印製一.電性塗層於其上,然後積層,切割5且燒成ie ~ the second external electrodes 3a, 3c, 4b and 4d. That is, as shown in FIGS. 1 and 4, the first external electrodes 3 b, 3 d, 4 a, and 4 c and the second external electrodes 3 a, 3 c, 4 b, and 4 d are disposed in the capacitor). Positions different from each other. In addition, the first external electrodes I 3b, 3d, 4a, and 4c are connected to the first internal electrode of the layer via the first guides lb ~ le, and the second external electrodes 3a, 3c, and 4b are connected through the second The I guides lb, ~ le are connected to the second internal electrodes 2 of the layer. I These internal electrodes 1 and 12 are formed by coating or grilling a nickel or other conductive i coating on the surface of a ceramic green sheet, and include nickel or nickel alloy layers. Note that the internal electrodes may also include base metal copper, precious metal handles, or silver alloy layers, and so on. The ceramic layer 2 includes a barium titanate · salt-based, chin-based, sulphate-based, or other ceramic composition. The laminated layer of the ceramic layer 2 and the internal electrode is formed by coating a ceramic clay on the surface of a base film or other films to form a green sheet and printing one. An electrical coating is applied thereon, and then laminated, cut 5 and fired

2030-3679-P.ptd 第16頁 498373 五、發明說明(13) 該綠薄片。在本體2 〇的產生後,構成且燒烤外部電極。具 韙而言,外部電極3a〜3d與4a〜4d可由塗佈' 乾燥與燒烤一 銅塗層於本體上以構成一下地層(underlayer),然後以一 鎳與錫的鍵層覆蓋下地層。 這樣生產的積層陶瓷電容30係由直接連接第一外部電 極3b、3d、4a與4c以及第二外部電極3a、:3c、4b與4d至電 路基板之不同的電路圖樣,且供應不同極的電壓至鄰接的 外部電極5而圬於多重端子的立體安裝。 本實施例之多端子積層陶瓷電容的單位尺寸並未特別 限制’但可為例如高〇 · 5 ± 0 · 1顏,寬(積層方向)1 · 6 土 j O.lfflffi,以及長3.2土 G.lmm。陶瓷層的厚度未特別限制, j但可為例如4 //m。陶瓷層的形狀係為短邊〇· 5 ± 0· 1mm與長 |邊3·2±0·1πΐ!η的一長方形。位於電容本體20之上面與下面 |且面對的外部電極之間的距離可設成大體相當於陶瓷層2 |的短邊長度。 這樣設置的多端子積層陶瓷電容3 0可安裝於如第4圖 所示的具有半導體裝置D之電源電路的電路基板5。此一立 體安裝可如下列方式進行。 也就是說,一組外部電極3a、3b、3c與3d係連接於半 等體裝置D的任一端子,且另一組外部電極、4b、4c與 4d係設置成直接面對電路基板5的不同電路圖樣6a與❿, ,電性連^以傲為正極/負極(GND)。在立體安裝中,甴保2030-3679-P.ptd Page 16 498373 V. Description of the invention (13) The green sheet. After the body 20 is produced, the external electrodes are constructed and grilled. Specifically, the external electrodes 3a ~ 3d and 4a ~ 4d can be coated with a copper coating on the body to form an underlayer, and then cover the lower layer with a nickel and tin bond layer. The multilayer ceramic capacitor 30 produced in this way consists of directly connecting the first external electrodes 3b, 3d, 4a, and 4c and the second external electrodes 3a ,: 3c, 4b, and 4d to different circuit patterns of the circuit board, and supplying voltages of different poles The three-dimensional mounting of the multiple external terminals to the adjacent external electrode 5. The unit size of the multi-terminal multilayer ceramic capacitor of the present embodiment is not particularly limited, but may be, for example, height 0.5 · 0.5 ± 1, width (layer direction) 1 · 6 soil j O.lfflffi, and length 3.2 soil G .lmm. The thickness of the ceramic layer is not particularly limited, but may be, for example, 4 // m. The shape of the ceramic layer is a rectangle with a short side of 0.5 ± 0 · 1 mm and a long side of 3 · 2 ± 0 · 1πΐ! Η. The distance between the upper and lower surfaces of the capacitor body 20 and the facing external electrodes may be set to be approximately the length of the short side of the ceramic layer 2 |. The multi-terminal multilayer ceramic capacitor 30 thus provided can be mounted on a circuit board 5 including a power supply circuit of a semiconductor device D as shown in FIG. This three-dimensional installation can be performed as follows. That is, one set of external electrodes 3a, 3b, 3c, and 3d are connected to any terminal of the hemibody device D, and the other set of external electrodes, 4b, 4c, and 4d are provided directly facing the circuit substrate 5. The different circuit patterns 6a and ❿ are electrically connected with AO as the positive / negative electrode (GND). In stereo installations,

2030-3679-P.ptd 第17頁 ΐ ΐ ΐ Ϊ ΐ ί尺寸Η整體看來低,焊墊的繞道變得較短, 且可使電路側之雷片-w 电感7C件的效應較小。 498373 五、發明說明(14) 為減少電路圖樣的電感’甴安裳具有值為 80〜ΙΟΟρΗ,旦ESR值為低至ΙΟιηΩ的積層陶究電容3〇,焊執 的電感元件可忽略。因此’若將習知技術的多端子積層^ 兗電容之ESL以及ESR與根據本發碉具有相同的靜電雷容的 多端子積層陶瓷電容相比,在使罔根據習知技:的多二二 積層陶究電容之狀況’該值變大8%’而在根據本實施例的 多端子積層陶瓷電容之狀況,保持在低2〜3%。 這是由於在本實施例的多端子積層陶曼電容中,由於 面對的外部電極之間的距離可設短’且電容裝置的高度整 體看來可減少’即使電容係安裝於一多層基板,由於焊墊 的繞道而造成的總電感可減少,且構成於多層基板上的焊 墊可簡化。 土 第二實施例 其次,如第5圖至第8圖所示,根據圖示實施例的用以 立體安裝之積層陶瓷電容130具有一電容本體12〇,為長方 形六面體狀。電容本體120,如第5圖與第6圖所示,係包 括交替地經由以長方形構成的陶瓷層i 〇2積層於圖中水$ 方向之既定圖樣的複數第一内部電極1(n輿^二内部電極 101,。也就是說,本實施例中,如第5圖與第6圖所示,複 數第一内部電極101與第二内部電極1〇Γ係經由陶瓷層i〇2 積層於水千方向,使得陶瓷層的短邊與電容本體12〇的高 度方问从主思非由内部電極構成的至少一陶免層1 Q 2 可被積層於尽體120在積層方向的兩端面。2030-3679-P.ptd Page 17 Η ΐ ΐ Ϊ Η ΗThe overall size is low, the routing of the solder pads becomes shorter, and the effect of the lightning-w inductor 7C on the circuit side is small. 498373 V. Description of the invention (14) In order to reduce the inductance of the circuit pattern, 甴 Anshang has a multilayer ceramic capacitor with a value of 80 ~ 100ρΗ and an ESR value as low as ΙΟιηΩ, and the inductance component of the welding can be ignored. Therefore, 'if the ESL and ESR of a multi-terminal multilayer of conventional technology ^ capacitors are compared with the multi-terminal multilayer ceramic capacitors having the same electrostatic lightning capacity according to the present invention, in accordance with the conventional technology: The condition of the multilayer ceramic capacitor 'the value becomes 8% larger' and the condition of the multi-terminal multilayer ceramic capacitor according to this embodiment is maintained at 2 to 3% lower. This is because in the multi-terminal multilayer Taurman capacitor of this embodiment, since the distance between the facing external electrodes can be set short, and the height of the capacitor device as a whole can be reduced, even if the capacitor is mounted on a multilayer substrate. The total inductance caused by the routing of the bonding pads can be reduced, and the bonding pads formed on the multilayer substrate can be simplified. Second Embodiment Secondly, as shown in FIGS. 5 to 8, the multilayer ceramic capacitor 130 for three-dimensional mounting according to the illustrated embodiment has a capacitor body 120, which is a rectangular hexahedron shape. The capacitor body 120, as shown in FIG. 5 and FIG. 6, includes a plurality of first internal electrodes 1 (n and ^) of a predetermined pattern alternately laminated in the direction of water $ in the figure through ceramic layers i 〇2 formed in a rectangular shape alternately. The two internal electrodes 101. In other words, in this embodiment, as shown in FIG. 5 and FIG. 6, the plurality of first internal electrodes 101 and the second internal electrode 101 are stacked in water via the ceramic layer i02. Thousands of directions, so that the short side of the ceramic layer and the height of the capacitor body 120 are at least one ceramic layer 1 Q 2 that is not composed of internal electrodes, and can be laminated on both ends of the body 120 in the laminated direction.

如第6圖所示,纟第—内部電極1〇1具有長方形的第一As shown in FIG. 6, the first-internal electrode 101 has a rectangular first

2030-3679-P.Ptd 第18頁 498373 五、發明說明(15) ?主要部,位於陶瓷層102的第一面(表面)。只有第一主要 j部的上(第一)長邊i〇lb沿陶瓷層1〇2的第一長邊i〇2a暴露 I於本體120的表面。第一電極iQi的縱向與橫向尺寸係設定 I成使得第一電極1〇1的另一長邊與兩短邊不到達陶瓷層1〇2 I的第二長邊102b與兩短邊102c與i02d。第一電極1〇1的横 |寬可為與陶瓷層1 〇2的橫寬具有相同寬度的尺寸。第一電 |極101的短邊之一可沿陶瓷層1〇2的短邊i〇2c與i〇2d暴露。 j 另外,各第二内部電極101,具有長方形的第二主要 !部,在相對於第一内部電極101的第一主要部之後面(第二 |面)沿縱方向經由一陶瓷層丨02。第二内部電極1〇1,之第二 I主要部的面積係與第一内部電極101之第一主要部的面積 |相同但,、有第一主要部的下(第二)長邊I 〇 1 a係沿陶瓷層 I 102的第二長邊102b暴露於本體120的下面。第二雷極 |的縱向與橫向尺寸係設定成使得第二電極·i01,的另一長邊 |與兩短邊不到達陶瓷層102的第一長邊i〇2a與兩短邊1〇以 丨:麵。f而’第二電極101,的橫寬可為與陶瓷;|^02的 杈見具有相同寬度的尺寸。第二電極丨0丨,的短邊之一可、、儿 |陶瓷層102的短邊l〇2c與l〇2d暴露。 一 ! 如第5圖舆第6圖所示,在本實施例中,在本體丨2〇 |内,具有相同長方形但面積較小於陶瓷層丨02的内 | 101與101’係經由陶瓷層102積層且交替地配置於垂直方 j的不同位置。從實行内鄯電極的圖樣結構於陶容層 |表面的觀點,内部電極101舆101’最好為彼此相同的長= |形狀’但本發明並非必須限定為相同形敗。 、 498373 五、發明說明(16) 電容本體120的上面接合有第一外部電極1〇3,以被電 性連接於具有沿陶瓷層102的第一長邊丨〇2a暴露之長邊 101b的第一内部電極1〇1。電容本體丨2〇的下面接合有第二 外部電極1 0 4,以被電性連接於具有沿陶瓷層丨〇 2的第二長 |邊102b暴露之長邊i〇ia的第二内部電極ι〇ι,。這些外部電 |極1 0 3與1 0 4係最好構成於電容本體丨2 〇的整個上面或下面 |之上5但並非必須限定覆蓋整韻表面。也可根據電容13〇 所欲安裝在的多層基板之焊墊形狀來決定覆蓋面積。相對 於内部電極101與101’的長邊暴露之本體上面或下面的面 積’外部電極103或104的面積最好為至少百分之50的面 積。2030-3679-P.Ptd Page 18 498373 V. Description of the invention (15) The main part is located on the first side (surface) of the ceramic layer 102. Only the upper (first) long side 101b of the first main part j is exposed on the surface of the body 120 along the first long side 102a of the ceramic layer 102. The longitudinal and lateral dimensions of the first electrode iQi are set to 1 such that the other long side and the two short sides of the first electrode 101 do not reach the second long side 102b and the two short sides 102c and i02d of the ceramic layer 102. . The lateral width of the first electrode 101 may be a size having the same width as the lateral width of the ceramic layer 102. One of the short sides of the first electrode 101 may be exposed along the short sides i02c and 102b of the ceramic layer 102. j In addition, each of the second internal electrodes 101 has a rectangular second main portion, and passes through a ceramic layer in a longitudinal direction with respect to the rear surface (second surface) of the first main portion of the first internal electrode 101. The area of the second main portion of the second internal electrode 101 is the same as the area of the first main portion of the first internal electrode 101. However, there is a lower (second) long side I of the first main portion. 1 a is exposed below the body 120 along the second long side 102 b of the ceramic layer I 102. The vertical and lateral dimensions of the second thunder pole | are set so that the other long side | of the second electrode i01, and the two short sides do not reach the first long side i02a of the ceramic layer 102丨: Face. f And the width of the second electrode 101 ′ may be a dimension having the same width as that of the ceramic; One of the short sides of the second electrode 丨 0 ″ may be exposed at the short sides 102c and 102d of the ceramic layer 102. First! As shown in FIG. 5 and FIG. 6, in this embodiment, in the body 丨 2 |, the same rectangular shape but smaller area than the ceramic layer 丨 02 | 101 and 101 'are passed through the ceramic layer 102 is laminated and arranged alternately at different positions on the vertical side j. From the viewpoint of implementing the pattern structure of the internal electrodes on the surface of the ceramic capacitor layer, the internal electrodes 101 ′ and 101 ′ are preferably the same length = shape, but the present invention is not necessarily limited to the same shape. 498373 V. Description of the invention (16) A first external electrode 103 is bonded to the capacitor body 120 to be electrically connected to the first electrode having the long side 101b exposed along the first long side of the ceramic layer 102. An internal electrode 101. A second external electrode 104 is bonded to the lower surface of the capacitor body 丨 2, so as to be electrically connected to a second internal electrode having a long side i〇ia exposed along the second long side 102b of the ceramic layer 丨 〇2 〇ι ,. These external electric poles 103 and 104 are preferably formed on the entire upper or lower surface of the capacitor body 5 above but not necessarily limited to cover the entire rhyme surface. The coverage area can also be determined according to the pad shape of the multilayer substrate on which the capacitor 13 is to be mounted. The area of the external electrode 103 or 104 above or below the body exposed with respect to the long sides of the internal electrodes 101 and 101 'is preferably at least 50% of the area.

I ! 這些内部電極101與101,係甴塗佈或燒烤一鎳或其他 I導冤性塗層於一陶瓷綠薄片之表面而構成,且包括鎳或鎳 合金層等。注意内部電極也可包括基底金屬銅、貴金屬鈀 或Ιε銀合金層等等。 陶瓷層1 0 2係包括一鋇鈦酸鹽基、鈦基、锆酸鹽基、 或其他陶免組成物。陶瓷層1 〇 2與内部電極的積層係由塗 佈一陶土於一基底薄膜或其他薄膜表面構成,而成為一綠 薄片,印製一導電性塗層於其上,然後積層,切割,且燒 成該綠薄片。在本體1 2 〇的產生後,構成且燒烤外部電 極。具體而言,外部電極1 〇 3與1 〇 4可由塗佈、乾燥與燒烤 一銅塗層於電容本體120上以構成一下地層,然後以一鎳 與錫的鍍層覆蓋下地層。 這樣生產的積層陶瓷電容1 3 〇係由直接連接第一外部I! These internal electrodes 101 and 101 are formed by coating or grilling a nickel or other coating on the surface of a ceramic green sheet, and include a nickel or nickel alloy layer. Note that the internal electrode may also include a base metal copper, a noble metal palladium or a 1ε silver alloy layer, and the like. The ceramic layer 102 includes a barium titanate-based, titanium-based, zirconate-based, or other ceramic-free composition. The laminated layer of the ceramic layer 102 and the internal electrode is formed by coating a clay on the surface of a base film or other films to form a green sheet, and a conductive coating is printed thereon, and then laminated, cut, and fired. Into the green flakes. After the body 1 2 0 is generated, the external electrodes are constructed and grilled. Specifically, the external electrodes 103 and 104 can be coated, dried, and grilled with a copper coating on the capacitor body 120 to form a lower ground layer, and then the lower ground layer is covered with a nickel and tin plating layer. The multilayer ceramic capacitor 130 produced in this way is directly connected to the first external

\ -\-

2030-3679-P.ptd 第20頁 货啊說明(17) 電極103以及第-从 樣,且供應不同:二電極^4至電路基板之不同的電路圖 螭子的立體安裝。〜、包堅至郇接的外部電極,而用於多重 本實施例之多娃 限制,但可為例如 ,+ sn,瓷電容的單位尺寸並未特別 〇」_。r自究=戸择土1職,寬0.8± ο.1·,以及長 出。陶兗層的形敗係5的=未特別限制,但可為例如4 " 的一旦方平 馮紐邊〇· 3工〇· imm與長邊3· 2 ± 〇· imm2030-3679-P.ptd Page 20 Description of the goods (17) Electrode 103 and the first-from the same, and the supply is different: the different circuit diagram of the two electrodes ^ 4 to the circuit board. ~, The external electrode is enclosed and connected, and it is used for multiple restrictions in this embodiment, but it can be, for example, + sn. The unit size of the ceramic capacitor is not special. r self-research = 戸 choose soil 1 position, width 0.8 ± ο.1 ·, and growth. The failure of the pottery layer 5 is not particularly limited, but may be, for example, 4 " once Fang Ping Feng Niuban 〇3 work 〇 · imm and long side 3.2 ± 〇 · imm

人 内部電極101與1〇!,可兩1 5M 構成。積層的屉數旦 j甶丨· b上·2· β //m的各度 且外部電極十門的里為静電電容係為例如0·22 : 亦即二離可設成相,於陶曼層的短邊寬度, 、'策3文農·的多端子積廣陶資雷它壯+、+ 士 第7圖所示具有主導成 =y奋130 5女裝或夾在如 邮與106之問'—/此_體立裝路中面對的電路基板 接+ ί ^疋规,電容130的外部電極U3與1(Μ係設詈成直 板m與106的不同電路圖樣m與⑽且\ 二為二極/負極Ο。在此-立體安裝中,電容 ⑽盘ηΓ6ΓΛ可保持低。另夕卜,由於面對的電路基板 倒々Hr距離保持窄’焊塾的繞道可縮短,且電路 A〜4感凡件的效應可減少。 美纟t,且另—外部電極104係電性連接於構成於電路 土反X 0 5的一開口中之電路圖樣丨〇 7。The human internal electrodes 101 and 10! Can be composed of two 15M. The number of layered drawers is j 甶 丨 · b on · 2 · β // m of each degree and the inside of the external electrode has a capacitance of, for example, 0 · 22: that is, two ions can be set into a phase, as in Tao The width of the short side of the man layer, 'Ce 3 Wennon's multi-terminal product wide pottery ceramics Lei Ta Zhuang +, + + 7 as shown in Figure 7 has a dominant component = y Fen 130 5 women's clothing or sandwiched as post and 106 Asking '— / this_ The circuit board facing in the body-mounting circuit is connected with the external electrode U3 and capacitor 1 of the capacitor 130 (M is a different circuit pattern m and 106 which are arranged in a straight plate m and 106 and \ Two is the bipolar / negative pole 0. In this three-dimensional installation, the capacitor plate ηΓ6ΓΛ can be kept low. In addition, because the Hr distance of the facing circuit substrate is kept narrow, the winding path of the solder can be shortened, and the circuit A ~ 4 can reduce the effect of ordinary parts. In addition, the external electrode 104 is electrically connected to a circuit pattern formed in an opening of the circuit soil X 0 5.

2030-3679-P.ptd 第21頁 中,圖所示二電容130可立體安裝。在太例 1〇9 ^ ^ 、缟子與電容1 3 0的一外部電極i 0 3係以焊料 498373 五、發明說明(18) 為減少電路圖樣的電感,由埋設具有ESL值為 10〜20pH,且ESR值為低至5〜7πιΩ的積層陶瓷電容13〇於電 路基板5·内,焊墊的電感元件可忽略。 右將習知技術具有0.22 aF靜電電容的積層陶曼電容 之ESL以及ESR與根據本貫施例的積層陶曼電容相比,若根 據習知技術的積層陶瓷電容之值為100% 5則根據本實施例 的積層陶瓷電容之值可降低2〜3 °/0。 這是由於在本實施例的積層陶瓷電容中,由於外部電 極103與104之間的距離可設短5且電容裝置的高度整體看 來可保持低,即使本實施例的電容係安裝於一多層基板, 由於焊墊的繞道而造成的總電感可減少,且構成於多層基 板上的焊墊可簡化。 苐二貫施例 以立如第9圖至第i2圖所示,根據圖示實施例的周 方形i ί ^責層陶变電容23G具有—電容本體22G,為長 包括;替:經由體220,如第9圖與第10圖所示,係 極2 0“。也:曰的禝數第一内部電極20 ^與第二内部電 示,複數第二二Ϊ,、本實施例中,如第9圖與第1〇圖所 瓷層202積層於水7卩電極2〇 11與第二内部電極2〇“係經由陶 體220的高度方向一方向,使得陶瓷層2〇2的短邊與電容本 陶瓷層2 0 2可被^展致’主思非由内部電極構成的至少一 如第1〇 _所八曰於本體2 20在積層方向的兩端面。 ^ 〃不,各第一内部電極2〇1具有長方形的第2030-3679-P.ptd Page 21, the two capacitors 130 shown in the figure can be installed in three dimensions. An external electrode i 0 3 of Taiji 1109, 缟 and capacitor 130 is solder 498373. V. Description of the invention (18) In order to reduce the inductance of the circuit pattern, the ESL value is 10 ~ 20pH. , And the multilayer ceramic capacitor 13 having an ESR value as low as 5 to 7 μmΩ is within the circuit substrate 5 ·, and the inductance component of the bonding pad can be ignored. The right side compares the ESL and ESR of a multilayer Taumman capacitor with a 0.22 aF electrostatic capacitance in the conventional technology to the multilayer Taurman capacitor according to the present embodiment. If the value of the multilayer ceramic capacitor according to the conventional technology is 100%, 5 The value of the multilayer ceramic capacitor in this embodiment can be reduced by 2 ~ 3 ° / 0. This is because in the multilayer ceramic capacitor of this embodiment, since the distance between the external electrodes 103 and 104 can be set to 5 and the height of the capacitor device as a whole can be kept low, even if the capacitor of this embodiment is installed in more than one In the multilayer substrate, the total inductance due to the routing of the bonding pads can be reduced, and the bonding pads formed on the multilayer substrate can be simplified. The second embodiment is as shown in FIG. 9 to FIG. 2. According to the illustrated embodiment, the square-shaped ceramic capacitor 23G has a capacitor body 22G, which is long; includes: Via body 220 As shown in FIG. 9 and FIG. 10, the system electrode 20 ". Also: the first internal electrode 20 ^ and the second internal electrical indication, the second plural two, in this embodiment, such as The ceramic layer 202 shown in FIGS. 9 and 10 is laminated on the water 7 卩 electrode 2011 and the second internal electrode 20 ″ through the height direction of the ceramic body 220, so that the short side of the ceramic layer 202 and the The capacitor ceramic layer 202 can be extended to at least two ends of the main body 2 20 in the lamination direction, as shown in FIG. ^ No, each first internal electrode 201 has a rectangular

2030-3679-?.ptd 第22頁 498373 五、發明說明(19) | 一主要部,位於陶瓷層202的第一面(表面)。只有第一主 | |要部的下(第一)長邊沿陶瓷層202的第一長邊202b暴露於 | I本體2 20的下面。第一電極2 01!的縱向與橫向尺寸係設定 | ΐ ^ ? |成使得第一電極20 I的另一長邊與兩短邊不到達陶瓷層 |2〇2的第二長邊2023與兩短邊202(:舆202(1。第一電極2011 | I的横寬可為與陶瓷層202的横寬具有相同寬度的尺寸。第 | I 一電極20 L的短邊之一可沿陶瓷層202的短邊202c與202d \ 暴露。 j 另外,各第二内部電極2012具有長方形的第二主要部 |2030-3679-?. ptd Page 22 498373 V. Description of the invention (19) | A main part is located on the first side (surface) of the ceramic layer 202. Only the first main side of || the main part of the lower (first) long edge ceramic layer 202 is exposed to the underside of the | I body 2 20. The longitudinal and transverse dimensions of the first electrode 2 01! Are set | ΐ ^? | So that the other long side and two short sides of the first electrode 20 I do not reach the ceramic layer | The second long side 2023 and two of the 02 Short side 202 (:: 202 (1. The first electrode 2011 | I may have a width that is the same as the width of the ceramic layer 202. One of the short sides of the | I-th electrode 20 L may be along the ceramic layer The short sides 202c and 202d of 202 are exposed. J In addition, each second internal electrode 2012 has a rectangular second main portion |

! 在相對於第一内部電極2〇 的第一主要部之後面: | (第二面)沿縱方向經由一陶瓷層202。第二主要部201a係 j由從上(第二)長邊延伸至陶瓷層202的第二長邊202a而暴 | 露的一對導引部201b與201c構成。這些導引部201b與201c \ !係構成以從長方形第二主要部201a之長邊的兩端向上凸 |The rear surface of the first main portion with respect to the first internal electrode 20: (the second surface) passes through a ceramic layer 202 in the longitudinal direction. The second main portion 201a is composed of a pair of guide portions 201b and 201c exposed from the upper (second) long side to the second long side 202a of the ceramic layer 202. These guide portions 201b and 201c are formed so as to project upward from both ends of the long side of the rectangular second main portion 201a |

I 出。/ II out. / I

i 第二電極20“的縱向與橫向尺寸係設定成使得第二電 Ii The vertical and horizontal dimensions of the second electrode 20 "are set such that the second electrode I

極2 0 12的第二主要部201a之另一長邊與兩短邊不到達陶瓷 I 層202的第一長邊2〇2b與兩短邊202c與202d。然而,第二 | 電極2 0 12的橫寬可為與陶瓷層202的橫寬具有相同寬度的 尺寸。第二電極2〇12的短邊之一可沿陶瓷層202的短邊 | j 202c與2〇2d暴露。 丨The other long side and two short sides of the second main portion 201a of the pole 2 0 12 do not reach the first long side 202b and the two short sides 202c and 202d of the ceramic I layer 202. However, the width of the second | electrode 2 0 12 may be a size having the same width as the width of the ceramic layer 202. One of the short sides of the second electrode 2012 may be exposed along the short sides of the ceramic layer 202 j 202c and 202d.丨

I 如第9圖與第10圖所示,在本實施例中,在本體220 I I内,内部電極201!與2012係經由陶瓷層202積層且交替地配; i 於全直乃向的不同位置。 !I As shown in FIG. 9 and FIG. 10, in the present embodiment, in the body 220 II, the internal electrodes 201! And 2012 are laminated and alternately arranged through the ceramic layer 202; i is at different positions in the omnidirectional direction . !

2030-3679-P.ptd 第23頁 η 刈 373 五、發明說明(20) 如第11圖所示,電容本體2 2 0的下面接合有一第一外 部電極203,以被電性連接於具有沿陶瓷層202的第一長邊 2〇2b暴露之長邊的第一内部電極201!。電容本體220的上 i面接合有一對第二外鄯電極204與2 05,以被電性連接於具 |有沿陶瓷層2〇2的第二長邊2 02a暴露之導引部20 lb與201c j的第二内部電極2〇 ι2。外部電極2 03係最好構成於電容本 j體2 2 G的整個下面之上,但並非必須限定覆蓋整個表面。 也可根據電容2 3 0所欲安裝在的多層基板之焊墊形狀來決 |定覆蓋面積。相對於第一内部電極20 的長邊暴露之本體 ! 2 2 〇卜面的面積,第一外部電極2 0 3的面積最好為至少百分 j之5 0的面積。 I 這些内鄯電極20 L與2012係由塗佈或燒烤一鎳或其他 j導電性塗層於一陶瓷綠薄片之表面而構成,且包括鎳或鎳 j合金層等。注意内部電極也可包括基底金屬銅、貴金屬鈀 I或鈀銀合金層等等。2030-3679-P.ptd Page 23 η 刈 373 5. Description of the invention (20) As shown in Fig. 11, a first external electrode 203 is bonded to the bottom of the capacitor body 2 2 0 to be electrically connected to The first inner electrode 201! Of the first long side 202b of the ceramic layer 202 is exposed. The upper body i of the capacitor body 220 is joined with a pair of second outer electrodes 204 and 205 to be electrically connected to a guide portion 20 lb with a second long side 202a exposed along the ceramic layer 202. The second internal electrode 201c j 201m. The external electrode 203 is preferably formed on the entire lower surface of the capacitor body 2 2 G, but it is not necessarily limited to cover the entire surface. The coverage area can also be determined according to the shape of the pads of the multilayer substrate on which the capacitor 230 is to be mounted. The area of the first external electrode 203 is preferably at least 50% of the area of the body exposed to the long side of the first internal electrode 20! These internal electrodes 20 L and 2012 are formed by coating or grilling a nickel or other j conductive coating on the surface of a ceramic green sheet, and include a nickel or nickel j alloy layer and the like. Note that the internal electrode may also include a base metal copper, a precious metal palladium I or a palladium-silver alloy layer, and the like.

I I 陶瓷層202係包括一鋇鈦酸鹽基 '鈦基、錘酸鹽基、 I或其他陶瓷組成物。陶瓷層202與内部電極的積層係由塗 布、陶土於一基底薄膜或其他薄膜表面構成,而成為/綠 薄片,印製一導電性塗層於其上,然後積層,切割,真燒 成該綠薄片。在本體22〇的產生後,構成且燒烤外部電 極。具體而言,外部電極203、2〇4舆2〇5可由塗佈、乾燐 j與燒烤一銅塗層於電容本體22〇上以構成一下地層,然後 i以一鎳與錫的鍍層覆蓋下地層。 1 這樣生產的積層陶瓷電容230係由直接連接第一外部The I I ceramic layer 202 is composed of a barium titanate-based, titanium-based, halide-based, I, or other ceramic composition. The laminated layer of the ceramic layer 202 and the internal electrode is formed by coating and pottery clay on the surface of a base film or other films to form a / green sheet. A conductive coating is printed thereon, and then laminated, cut, and fired into the green Flakes. After the body 22 is produced, the external electrodes are constructed and grilled. Specifically, the external electrodes 203, 204 and 205 can be coated, dried, and grilled with a copper coating on the capacitor body 22 to form a ground layer, and then i is covered with a nickel and tin plating layer. Strata. 1 The multilayer ceramic capacitor 230 produced in this way is directly connected to the first external

498373 五、發明說明(21) 電極203以及第二外部電極2〇4與2〇 電路圖樣,s也瘅兀门、从+ 一 一名基板之不同的 % 一 μ應不同極的電壓至鄰 於多重端子的立體安裝。 接的外#笔極’而用 本灵她例之多端子積層陶瓷電容的單也尺 限f,但可為例如高〇,5±〇.1顏,寬0.8±0.1m/,以= m m曼層的厚度未特別限制,但可為例如4 / ^ 文層的形坟係為短邊0 5±01龍與長邊16土 0 1咖 ^•^形^部電極叫與叫可甴丨^至以㈣的厚度 構珉。外部電極203與204之間的距離Η與第二電極之間的 距離G可設成相當於陶瓷層的短邊寬度,亦即〇. 5 土 0. 1 mm。 又呈的多端子積層陶瓷電容23(]可被夾擠安裝在 如第1 2圖所示具有半導體裝置D之電源電路中面對的電路 基板2 0 6與2 0 7之間。此一立體安裝可如下列方式進行。 也就是說’外部電極2〇3、204與205係設置成直接面 對電路基板205與206的不同電路圖樣208、209a與209b, 且%性連接以做為正極/負極(G N D)。在此一立體安裝中, 電容裝置的高度Η整體可保持低,且另外面對的電路基板 2 0 6與2 0 7之間的距離保持窄。因此,焊墊的繞道可縮短, 且電路側之電感元件的效應可減少。 為減少電路圖樣的電感,由埋設具有ESL值為 10〜20ρΗ,且ESR值為低至5〜7m Ω的積層陶瓷電容230,焊 墊的電感元件可忽略。因此,若將習知技術具有0. 2 2 # F 靜電電容的積層陶瓷電容之ESL,以及ESR與根據本實施例的498373 V. Description of the invention (21) Circuit pattern of the electrode 203 and the second external electrode 204 and 20, s is also rugged, and the difference from + one to the other substrate is different from% to μ. Multi-terminal stereo mounting. The connected outer # 笔 极 'and the multi-terminal multilayer ceramic capacitor used in this example are also limited in size f, but can be, for example, 0.5, 0.5 ± 0.1 color, 0.8 ± 0.1 m /, and = mm The thickness of the Man layer is not particularly limited, but it can be, for example, the 4 / ^ layer of the tomb is a short side 0 5 ± 01 dragon and a long side 16 soil 0 1 coffee ^ • ^ shaped electrode called and called can be 甴 丨^ To 珉 to the thickness of ㈣. The distance G between the external electrodes 203 and 204 and the distance G between the second electrodes may be set to correspond to the width of the short side of the ceramic layer, that is, 0.5 to 0.1 mm. The multi-terminal multilayer ceramic capacitor 23 () can be sandwiched and installed between the circuit substrates 2 06 and 2 7 facing in the power supply circuit with the semiconductor device D as shown in FIG. 12. This stereoscopic The installation can be performed in the following way. That is, the 'external electrodes 203, 204, and 205 are arranged to directly face the different circuit patterns 208, 209a, and 209b of the circuit substrate 205 and 206, and are connected as a positive / Negative electrode (GND). In this three-dimensional installation, the height of the capacitor device can be kept low as a whole, and the distance between the circuit substrates 2 06 and 2 7 facing each other is kept narrow. Therefore, the detour of the solder pads can be It is shortened, and the effect of the inductance element on the circuit side can be reduced. In order to reduce the inductance of the circuit pattern, the multilayer ceramic capacitor 230 with an ESL value of 10 to 20ρΗ and an ESR value as low as 5 to 7m Ω is embedded, and the inductance of the pad The component can be ignored. Therefore, if the conventional technology has an ESL of a multilayer ceramic capacitor with an electrostatic capacitance of 0.2 2 # F, and the ESR and

2030-3679-P.ptd 第25頁 498373 !五、發明說明(22) I ^ j積層陶瓷電容(與習知技術的靜電電容相同)相比,若根據 j習知技術的積層陶瓷電容之值為丨〇 〇%,則根據本實施例的 積層陶瓷電容之值可降低2〜3%。 這是由於在本實施例的積層陶瓷電容中,外部電極 I 203、204與205之間的距離可設短,電容裝置的高度整體 |看來可保持低,且外部電極2〇3寬,至焊墊的連接容易。 另外’即使本實施例的電容2 3 〇係安裝於一多層基板5由 於焊墊的繞道而造成的總電感可減少,旦構成於多居基板 上的焊墊可簡化。 β 一 '2030-3679-P.ptd Page 25, 498373! V. Description of the invention (22) I ^ j multilayer ceramic capacitor (same as the electrostatic capacitance of the conventional technology) If it is 100%, the value of the multilayer ceramic capacitor according to this embodiment can be reduced by 2 to 3%. This is because in the multilayer ceramic capacitor of this embodiment, the distance between the external electrodes I 203, 204, and 205 can be set short, the height of the capacitor device as a whole | it seems to be kept low, and the external electrode 203 is wide, to Easy connection of pads. In addition, even if the capacitor 230 of this embodiment is mounted on a multilayer substrate 5, the total inductance due to the routing of the bonding pad can be reduced, and the bonding pad formed on the multi-substrate substrate can be simplified. β a '

圖示 有一 第13 陶瓷 部電 中, 二内 陶瓷 由内 積層 方As shown in the figure, there is a 13th ceramic component, and the 2 inner ceramics are laminated by the inner side.

第四實施例 其次’請參見第1 3圖至第1 6圖以解釋本實施例,根教 貝加例的罔以立體安裝之通孔型積層陶瓷電容Μ 〇具 m容本體320,為長方形六面體狀。電容本體32〇,士 圖與第14圖所示,係包括交替地經由以長方形構成备 層3 02積層於圖中水平方向之既定圖樣的複數第一内 極311與第二内部電極30 12。也就是說,本實施例 如第13圖與第14圖所示,複數第一内部電極3〇込與第 部電極30 “係經由陶瓷層302積層於水平方向5使得 層=302短邊與電容本體32〇的高度方向一致。注意$ 部’电極構成的至少一陶瓷層302可被積層於太體3204 方向的兩端面。 + — 立U圖所示,各第一内部電極30 11具有長 :的第一 ^要冑,位於陶瓷層30 2的第一面(表面)。第 一要"卩的网長邊沿陶瓷層302的兩長邊302c與302d暴露Fourth Embodiment Secondly, please refer to FIG. 13 to FIG. 16 to explain this embodiment. According to the Bejia example, a three-dimensionally mounted through-hole multilayer ceramic capacitor M with a m-capacity body 320 is rectangular. Hexahedral. The capacitor body 32, as shown in FIG. 14 and FIG. 14, includes a plurality of first internal electrodes 311 and second internal electrodes 30 12 alternately formed in a horizontal pattern in the figure by alternately forming a backup layer 3 02 in a rectangular shape. That is, as shown in FIG. 13 and FIG. 14 of the present embodiment, the plurality of first internal electrodes 30 込 and the first electrode 30 are laminated in the horizontal direction 5 through the ceramic layer 302 so that the layer = 302 short side and the capacitor body The direction of the height of 32 ° is the same. Note that at least one ceramic layer 302 formed by the electrode of the part can be laminated on both end surfaces in the direction of the body 3204. + — As shown in the U figure, each of the first internal electrodes 30 11 has a length: The first main point is located on the first side (surface) of the ceramic layer 302. The first long side of the net is exposed along the two long sides 302c and 302d of the ceramic layer 302.

第26頁Page 26

498373 五、發明說明(23) |於尽體3 20的表面。第一電極⑽^的縱向與橫向尺寸係設 |定成使得第一電極301!的兩短邊不到達陶瓷層3〇2的兩短 !邊3 02& 與302b。 另外,各第二内部電極30 l2具有長方形的第二主要部 301a ’在相對於第一内部電極3〇 h的第一主要部之後面 (第一面)沿縱方向經由一陶瓷層。第二主要部3〇ia係498373 V. Description of the invention (23) | The longitudinal and transverse dimensions of the first electrode ⑽ are set so that the two short sides of the first electrode 301! Do not reach the two short sides of the ceramic layer 302 and the sides 302 and 302b. In addition, each of the second internal electrodes 30 l2 has a rectangular second main portion 301a 'after a rear surface (first surface) of the first main portion 30 h with respect to the first internal electrode via a ceramic layer in the longitudinal direction. Department of the Second Main Section 30a

i由從兩短邊延#至陶瓷層302的短邊3023與3021)而暴露的 一對導引部301b與301c構成。這些導引部3〇ib舆301c係構| 成以從長方形第二主要部3(Ha之短邊的大約中央朝向兩邊I | 302a與302b凸ώ。第二主要部301a的短邊尺寸係設定成使| |得長方形第二主要部3〇la的長邊不到達陶瓷層3〇2的長邊 i 30 2c與302d。注意導引部3〇ib與301c的垂直寬度(本體高 |度刀向的寬度)係小於圖例中之部3〇ia的垂直寬庶5但也 i j可為相同的寬度。 。八一 | | 本貝知例中,如第1 3圖與第1 4圖所示,在本體3 2 Q | j内,内部電極3011與3012係經由陶瓷層302積層且交替地配j |置於垂直方向的不同位置。 如第13圖與第16圖所示,電容本體32〇的上面盥下面 |接合有第一外部電極303與303,,以被電性連接於^有沿 丨陶瓷層30^的長邊3〇2(:與3〇2(1暴露之長邊的第一内部電^ 3 01!。電容本體3 2〇的倒面之周面接合有—帶狀第二外都 j電極304,以被電性連接於具有沿陶瓷層3〇2的短盥 | 302b暴露之導引部“卜與別^的第二内部電極3〇丨。 | j 第一外部電極3〇3與303,係最好構成於電容本2體32〇的i is composed of a pair of guide portions 301b and 301c that are extended from the two short sides to the short sides 3023 and 3021 of the ceramic layer 302). These guide portions 30b and 301c are structured so as to protrude from the approximate center of the short side of the rectangular second main portion 3 (Ha toward the two sides I | 302a and 302b. The short side dimensions of the second main portion 301a are set So that | | the long side of the rectangular second main portion 30a does not reach the long sides i 30 2c and 302d of the ceramic layer 30. Note the vertical width of the guide portions 30b and 301c (body height | degree knife The width in the vertical direction) is smaller than the vertical width of the part 30a in the illustration, but ij can be the same width. Bayi | | In this example, as shown in Figures 13 and 14 In the body 3 2 Q | j, the internal electrodes 3011 and 3012 are laminated through the ceramic layer 302 and are alternately arranged at different positions in the vertical direction. As shown in FIGS. 13 and 16, the capacitor body 32 〇 The upper surface and lower surface | The first external electrode 303 and 303 are joined to be electrically connected to the long side 302 (with the long side of the exposed side of the ceramic layer 30 ^) and the long side of the exposed side of 302 (1 An internal electric ^ 3 01 !. The peripheral surface of the inverted side of the capacitor body 3 2 0 is joined with a strip-shaped second outer electrode j 304 to be electrically connected to a short bathroom having a ceramic layer 3 0 2 | 302b Exposed The second internal electrode 3〇 丨 of the guide part "Bu and Be." | J The first external electrodes 3 03 and 303 are preferably formed in the capacitor body 2 32

2030-3679-P.ptd 第27頁 498373 五、發明說明(24) 也 整個上面或下面之上,但並非必須限定覆蓋整個 可根據電容3 3 0所欲安裝在的多層基板之焊墊形狀 、^ 覆蓋面積。相對於第一内部電極3 〇 h的長邊暴露決定 320上面或下面的面積,第一外邬電極3〇3或3〇3,=體 好為至少百分之50的面積。 、间積最 這些内部電極30 與3012係由塗佈或燒烤一錄 導電性塗層於一陶瓷綠薄片之表面而構成,且包/括^其他 合金層等。注意内部電極也可包括基底金屬銅匕主=或鎳 或鈀銀合金層等等。 。 貝&屬#5 陶瓷層302係包括一鋇鈦酸鹽基、鈦基、錘酸鹽 或其他陶瓷組成物。陶瓷層3 〇 2與内部電極的積;^ 、乾燥 然後 與燒烤一銅塗層於電容本體320上以構成—下地層, 以一鎳與錫的鍍層覆蓋下地層。 ^ 這樣生產的積層陶瓷電容330係由直接連接第—外立 電極30 3與30 3’以及第二外部電極3 04至電路基板之不同 電路圖樣’且供應不同極的電壓至鄰接的外部電極,而的 於多重端子的立體安裝。 ’用 本實施例之多端子積層陶瓷電容的單位尺寸蓮未特。 限制’但可為例如高0 · 5 ± 0 · 1 mm ;宽(K 8 ± 〇 1 mm,以及^ 1 · 6 ± 0 · 1 mm。陶瓷層的厚度未特別限制,但可為例如$ 乂 佈一陶土於一基底薄膜或其他薄膜表面構成,胃而4成^^由 薄片,印製一導電性塗層於其上,然後積層,切割:一綠 成該綠薄片。在本體320的產生後,構成且3燒烤外^部缔且燒 極。具體而言,外部電極30 3、30 3,與304可由塗部兒2030-3679-P.ptd Page 27, 498373 V. Description of the invention (24) It also covers the entire top or bottom, but it is not necessary to limit the shape of the pad that covers the entire multilayer substrate that can be installed according to the capacitor 3 3 0, ^ Covered area. Relative to the long side exposure of the first internal electrode for 30 hours determines the area above or below 320, the first external condyle electrode is 303 or 30, which is an area of at least 50 percent. The inner electrodes 30 and 3012 are formed by coating or grilling a conductive coating on the surface of a ceramic green sheet, and including / including other alloy layers. Note that the internal electrode may also include a base metal, copper, or nickel or palladium-silver alloy layer, and the like. . Shell & Gen # 5 ceramic layer 302 comprises a barium titanate-based, titanium-based, hammer salt or other ceramic composition. The product of the ceramic layer 300 and the internal electrode is dried and then baked with a copper coating on the capacitor body 320 to form a lower ground layer, which is covered with a nickel and tin plating layer. ^ The multilayer ceramic capacitor 330 produced in this way is formed by directly connecting the first external electrodes 30 3 and 30 3 ′ and the second external electrode 304 to different circuit patterns of the circuit substrate and supplying different voltages to adjacent external electrodes. And for the three-dimensional installation of multiple terminals. The unit size of the multi-terminal multi-layer ceramic capacitor of this embodiment is not limited. Restricted 'but may be, for example, height 0 · 5 ± 0 · 1 mm; width (K 8 ± 〇1 mm, and ^ 1 · 6 ± 0 · 1 mm. The thickness of the ceramic layer is not particularly limited, but may be, for example, $ 乂A piece of clay is formed on the surface of a base film or other film, and the stomach is formed into a thin sheet, and a conductive coating is printed on it, and then laminated and cut: a green sheet is formed. After that, it is constituted and grilled on the outer part of the grill and burned. Specifically, the external electrodes 30 3, 30 3, and 304 can be coated by the coating part.

第28頁Page 28

2030-3679-P.ptd 498373 五、發明說明(25) m。陶瓷層的形狀係為短邊0.5v 〇. imm與長邊l6± (Klmm 的一長方形。内部電極3011與3〇19可由} 5至2 () 的厚度 構成。外部電極303與303,之間的距離H可設成相當於陶瓷 層302的短邊寬度’亦即〇.5± 〇Um。 这樣設置的通孔型積層陶瓷電交3 3{)可被夾擠安裝在 如第16圖所示具有半導體裝置{)之雷源雪致中面對的電路 基板305與306之間。沌一立體安裝可如下列方式進行。 .也就是說,垂直面對的外部電極303與303,係設置成 ,接面對電路基板305與306的不同電路圖樣3〇7a與3〇7b, 伸經由整個側面之周面的外部電極3〇4係設置成直揍 ===離的電路圖樣308a與308b,且這些係電性連接以做 為:極/負極獅)。在此一立體安裝中電容裝置的高度 保持低,且另外,面對的電路基板305與306之間 持窄。因此,焊墊的繞道可縮短,且電感元件的 效應可減少。 為減少電路圖樣的電感,由垣設具有£乩值為 執ϋΗ、,且SSR值為低至5〜?ΏΩ的積層陶兗電容330,焊 ς二琢兀许可忽略。因此,若將習知技術具有〇22#F 二=容的積層肖:是電容之他以及ESR與根據本實施例的 ;層:竟電容(與習知技術的靜電電容相同)相比;若根據 二術的積層陶究電容之值為1〇〇%,則根據本實施例的 積層陶瓷電容之值可降低2〜3%。 、這是甴於在本實施例的積層陶瓷電容申,外部電極 ο。。、303’與304之間的距離可設短,電容裝置的高度整體2030-3679-P.ptd 498373 V. Description of the invention (25) m. The shape of the ceramic layer is a rectangle with a short side of 0.5v 〇. Imm and a long side of 16 ± (Klmm. The internal electrodes 3011 and 3〇19 can be composed of a thickness of 5 to 2 (). Between the external electrodes 303 and 303, The distance H can be set to correspond to the width of the short side of the ceramic layer 302 ', that is, 0.5 ± 〇Um. The through-hole laminated ceramic ceramic 3 3 () thus arranged can be sandwiched and installed as shown in FIG. 16 Between the circuit substrates 305 and 306 of the lightning source Xuezhi shown with the semiconductor device {) shown. The chaotic one-dimensional installation can be performed as follows. That is, the external electrodes 303 and 303 facing vertically are arranged so as to face different circuit patterns 3007a and 3007b facing the circuit substrates 305 and 306, and the external electrodes 3 extending through the entire peripheral surface of the side surface 〇4 series is set to be straight === away from the circuit patterns 308a and 308b, and these series are electrically connected as: pole / negative lion). In this three-dimensional installation, the height of the capacitor device is kept low, and in addition, the facing circuit substrates 305 and 306 are kept narrow. Therefore, the routing of the bonding pad can be shortened, and the effect of the inductive element can be reduced. In order to reduce the inductance of the circuit pattern, it is determined that the value of £ is fixed and the SSR value is as low as 5 ~? The ΏΩ multilayer ceramic capacitor 330 is neglected. Therefore, if the conventional technology has a built-in multilayer structure of 022 # F = capacitance: it is the other of the capacitor and the ESR is according to this embodiment; the layer: the actual capacitance (same as the electrostatic capacitance of the conventional technology); The value of the multilayer ceramic capacitor according to the second technique is 100%, and the value of the multilayer ceramic capacitor according to this embodiment can be reduced by 2 to 3%. This is the external electrode of the multilayer ceramic capacitor applied in this embodiment. . The distance between 303 ’and 304 can be set short, the height of the capacitor device as a whole

2030>3679-P.Ptd 第29頁 498373 五、發明說明(26) 看來可保持低。另外,外部電極2 0 3寬,旦至焊墊的連接 容易,因此即使電容係安裝於一多層基板,由於焊墊的繞 道而造成的總電感可減少,且構成於多層基板上的焊墊可 簡化。 雖然本發明已以數個較佳實施例揭露如上,然其並非 羯以?艮定本發明,任何熟習此項技藝者%在不脫離本發明 之精神和範圍内,仍可作些許的更動與潤飾,因此本發明 之保護範圍當視後附之申請專利範圍所界定者為準。2030 > 3679-P.Ptd Page 29 498373 V. Description of the invention (26) It seems to be kept low. In addition, the external electrode is wide, and the connection to the bonding pad is easy, so even if the capacitor is mounted on a multilayer substrate, the total inductance due to the routing of the bonding pad can be reduced, and the bonding pad formed on the multilayer substrate Can be simplified. Although the present invention has been disclosed as above with several preferred embodiments, it is not a lie? As for the present invention, any person skilled in the art can still make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application. .

2030-3679-P.ptd 第30頁2030-3679-P.ptd Page 30

Claims (1)

498373 、申請專利範圍 1 1 一種用於立體安裝之積層陶瓷電容,包括: | 一陶瓷層,以一長方形構成; | 一第一内部電極,具有沿前述陶莞層之第一面於縱方 !向延伸的長方形第一主要部,且具有從前述第一主要部之 丨長邊延侍至前述陶曼層之長邊的複數第一導引部; | 一第二内部電極,具有與前述第一内部電極之前述第 | 一主要部經由前述陶瓷層相對並位於與前述第一面相對的 j前述陶瓷層之第二面的長方形第二主要部,且具有從前述 \ 第二主要部之長邊在與設置於前述第一内部電極之前述第 1 一導引部不同位置延伸至前述陶瓷層之前述長邊的複數第 二導引部; 一長方形六面體狀電容本體,包括複數前述第一内部 電極以及前述第二内部電極藉由前述陶瓷層積層,使得前 j述陶瓷層的短邊與前述電容本體的高度方向一致; J; | 第一外部電極,構成於前述電容本體之上面與下面, 且分別電性連接於沿前述陶莞層之積層方向位於同一列的 i前述第一導引部;以及 I 第二外部電極,對應於前述第一外部電極而交替地構 |成於前述電容本體之前述上面與前述下面,且分別電性連 i接於沿前述陶曼層之前述積層方向位於同一列的前述第二 ί導引部。 | 2.如申請專利範圍第1項所述的羯於立體安裝之積層 |陶瓷電容,其中前述第一外部電極係連接於前述電容本體 j外側的第一電路圖樣,且前述第二外部電極係連接於與前498373 、 Application patent scope 1 1 A multilayer ceramic capacitor for three-dimensional installation, comprising: | a ceramic layer composed of a rectangle; | a first internal electrode having a first side along the first side of the aforementioned ceramic layer in the vertical direction! A rectangular first main portion extending in a direction, and having a plurality of first guide portions extending from a long side of the first main portion to a long side of the Taumman layer; a second internal electrode having the same shape as the first The aforementioned first | main portion of an internal electrode is a rectangular second major portion facing through the ceramic layer and located on the second surface of the aforementioned ceramic layer opposite to the first surface, and has a length from the aforementioned second major portion A plurality of second guide portions extending to the long side of the ceramic layer at different positions from the first guide portion provided on the first internal electrode; a rectangular hexahedral capacitor body including a plurality of the first An internal electrode and the second internal electrode are laminated by the ceramic, so that the short side of the foregoing ceramic layer is consistent with the height direction of the capacitor body; J; | Is formed above and below the capacitor body, and is electrically connected to the aforementioned first guide portions located in the same row along the laminated direction of the ceramic layer; and the second external electrode corresponds to the first external portion. The electrodes are alternately formed on the upper surface and the lower surface of the capacitor body, and are electrically connected to the second guide portions located in the same row along the stacking direction of the Taoman layer, respectively. 2. The multi-layer mounted multilayer ceramic ceramic capacitor according to item 1 of the scope of patent application, wherein the first external electrode system is connected to the first circuit pattern outside the capacitor body j, and the second external electrode system is Connected with before 11 II I __匪_ II 國醒_1圓圓 I! 11 ____ 2030-3679-P.ptd 第31頁 4 498373 i六、申請專利範圍 I 述第一電路圖樣不同的第二電路圖樣。 3 ·如申請專利範圍第1項所述的用於立體安裝之積層 !陶瓷電容,其中前述積層陶瓷電容係埋設於一立體電路基 I板中。 i i 4, 一種用於立體安裝之積層陶瓷電容,包括: ! I 一陶曼層,以一長方形構成; | | 一第一内部電極5具有沿前述陶莞層之第一面於縱方 I向延伸的長方形第一主要部,且具有沿前述陶瓷層之第一 !長邊而暴露的前述第一主要部之第一長邊; ί I I 一第二内部電極,具有沿與前述第一面相對的前述陶 I11 II I __Beg_ II Guo Xing_1 Yuanyuan I! 11 ____ 2030-3679-P.ptd Page 31 4 498373 i 6. Scope of Patent Application I The second circuit pattern of the first circuit pattern is different. 3 · Multilayer ceramic capacitors for three-dimensional installation as described in item 1 of the scope of patent application, wherein the aforementioned multilayer ceramic capacitors are buried in a three-dimensional circuit-based I-board. i i 4, a multilayer ceramic capacitor for stereo mounting, including:! I a Taurman layer composed of a rectangle; | | a first internal electrode 5 has a rectangular first main portion extending in the longitudinal direction I along the first surface of the aforementioned ceramic layer, and has a first A! A long side and a first long side of the aforementioned first main part exposed; II a second internal electrode having the aforementioned ceramic I opposite the first surface I 瓷層之第二面於縱方向延伸的長方形第二主要部5且具有 | 沿前述陶瓷層之第二長邊而暴露的前述第二主要部之第二 I !ί 曰 ^ 一長方形六面體狀電容本體,包括複數前述第一内部I I電極以及前述第二内部電極藉由前述陶瓷層積層,使得前 | |述陶瓷層的短邊與前述電容本體的高度方向一致; I 第一外部電極,構成於前述電容本體之上面或下面, j 且分別電性連接於沿前述陶瓷層之前述第一長邊暴露的前i 述第一内部電極;以及 jI The rectangular second main portion 5 of which the second surface of the porcelain layer extends in the longitudinal direction and has a second I of the aforementioned second main portion that is exposed along the second long side of the aforementioned ceramic layer! The bulk capacitor body includes a plurality of the aforementioned first internal II electrodes and the aforementioned second internal electrodes through the aforementioned ceramic lamination so that the short side of the aforementioned ceramic layer is consistent with the height direction of the aforementioned capacitor body; I a first external electrode Is formed above or below the capacitor body, and is respectively electrically connected to the first internal electrode described above that is exposed along the first long side of the ceramic layer; and j 第二外部電極,構成於前述電容本體之上面或下面, 且分別電性連接於沿前述陶瓷層之前述第二長邊暴露的前 \ _ ί !述第二内部電極。 5 5,如申請專利範圍第4項所述的羯於立體安裝之積層 | 陶瓷電容5其中前述第一外部電極係連接於前述電容本體 I fThe second external electrode is formed above or below the capacitor body, and is electrically connected to the second internal electrode respectively exposed along the second long side of the ceramic layer. 5 5, as described in item 4 of the scope of the patent application for the three-dimensional installation of the multilayer | ceramic capacitor 5 wherein the aforementioned first external electrode is connected to the aforementioned capacitor body I f 2030-3679-P.ptd 第32頁 498373 六、申請專利範圍 外侧的第一電路圖樣,且前述第二外部電極係連接於與前 述第一電路圖樣不同的第二電路圖樣。 I 6.如申請專利範圍第4項所述的用於立體安裝之積層 |陶瓷電容,其中前述積層陶瓷電容係埋設於一立體電路基 |板中。 | 7. —種罔於立體安裝之積層陶瓷電容,包括: I 一陶瓷層,以一長方形構成; 1 一第一内部電極,具有沿前述陶瓷層之第一面於縱方 向延伸的長方形第一主要部,且具有沿前述陶兗層之第一 長邊而暴露的前述第一主要部之第一長邊; | 一第二内部電極,具有沿與前述第一面相對的前述陶 |瓷層之第二面於縱方向延伸的長方形第二主要部,且具有 |從前述第二主要部之第二長邊廷伸至前述陶瓷層之第二長 |邊的複數導引部; ! 一長方形六面體狀電容本體,包括複數前述第一内部 I電極以及前述第二内部電極藉由前述陶瓷層積層,使得前 i述陶瓷層的短邊與前述電容本體的高度方向一致; I 一第一外部電極,構成於前述電容本體之上面或下 |面,且電牷連接於沿前述陶瓷層之前述第一長邊暴露的前 I述第一内部電極;以及 第二外部電極,構成於前述電容本體之上面或下面, 且分別電性連接於沿前述陶瓷層之前述第二長邊暴露的前 I述導引部。 \ 8.如申請專利範圍第7項所述的罔於立體安裝之積層2030-3679-P.ptd Page 32 498373 6. Scope of patent application The first circuit pattern on the outside, and the second external electrode is connected to a second circuit pattern different from the first circuit pattern. I 6. The multilayer ceramic capacitor for three-dimensional installation as described in item 4 of the scope of patent application, wherein the aforementioned multilayer ceramic capacitor is buried in a three-dimensional circuit substrate. 7. —A multilayer ceramic capacitor mounted in a three-dimensional installation, including: I a ceramic layer composed of a rectangle; 1 a first internal electrode having a rectangular first extending in a longitudinal direction along a first surface of the ceramic layer A main part having the first long side of the first main part exposed along the first long side of the pottery layer; a second internal electrode having the pottery | porcelain layer opposite the first surface The second side of the rectangular second main portion extending in the longitudinal direction has a plurality of guide portions extending from the second long side of the second main portion to the second long side of the ceramic layer;! A rectangle The hexahedron-shaped capacitor body includes a plurality of the aforementioned first internal I electrodes and the aforementioned second internal electrodes by the aforementioned ceramic lamination so that the short sides of the aforementioned ceramic layer are consistent with the height direction of the aforementioned capacitor body; I-first The external electrode is formed on the upper or lower surface of the capacitor body, and is electrically connected to the first internal electrode described above exposed along the first long side of the ceramic layer; and the second external electrode is formed on Said capacitance above or below the main body, and electrically connected to the ceramic layers along the second long side of said exposed front guide portion I. \ 8. As described in item 7 of the scope of the patent application, the layering of the three-dimensional installation 2030-3679-P.ptd 第33頁 498373 I六、申請專利範圍 | !陶瓷電容5其中前述複數第二外部電極係以一大體相當於 j前述陶瓷層的前述短邊之距離配置於前述電容本體的前述 ! i上面或前述下面。 I I 9·如申請專利範圍第7項所述的羯於立體安裝之積層 j 1陶瓷電容,其中前述第一外部電極係連接於前述電容本體I I外側的第一電路圖樣,且前述第二外部電極係連接於與前I !述弟一電路_松不同的第二電路圖樣。 | 1G·如申請專利範圍第?項所述的用於立體安裝之積層 I 陶瓷電容,其中前述積層陶瓷電容係埋設於一立體電路基I2030-3679-P.ptd Page 33, 498373 I Sixth, the scope of patent application |! Ceramic capacitor 5 wherein the aforementioned plurality of second external electrodes are arranged on the capacitor body with a distance substantially equivalent to the aforementioned short side of the aforementioned ceramic layer The aforementioned! I above or below mentioned. II 9 · The multilayer j 1 ceramic capacitor for stereoscopic installation as described in item 7 of the scope of patent application, wherein the first external electrode is a first circuit pattern connected to the outside of the capacitor body II, and the second external electrode is It is connected to the second circuit pattern which is different from the former circuit. | 1G · If the scope of patent application is the first? The multilayer ceramic capacitor for three-dimensional mounting according to the item above, wherein the multilayer ceramic capacitor is embedded in a three-dimensional circuit substrate I 板中。 I 11. 一種用於立體安裝之積層陶瓷電容,包括: I 一陶瓷層,以一長方形構成; I 1 一第一内部電極:具有沿前述陶曼層之第一靣於縱方 | j向延伸的長方形第一主要部,旦具有沿前述陶瓷層之長邊 1 而分別暴露的前述第一主要部之兩長邊; I 一第二内部電極,具有沿與前述第一靣相對的前述陶 j 瓷層之第二面於縱方向延伸的長方形第二主要部,且具有 i從前述第二主要部之短邊分別延伸至前述陶瓷層之短邊的 I —對導引鄯; !In the board. I 11. A multilayer ceramic capacitor for three-dimensional mounting, comprising: I a ceramic layer formed of a rectangle; I 1 a first internal electrode: having a first frame extending vertically along the aforementioned Taoman layer | j direction A rectangular first main part having two long sides of the first main part that are respectively exposed along the long side 1 of the ceramic layer; a second internal electrode having the pottery j facing the first part The rectangular second main portion of the second layer of the porcelain layer extending in the longitudinal direction, and I having i extending from the short side of the aforementioned second main portion to the short side of the aforementioned ceramic layer, respectively—the pair of guides;! 一長方形六面體狀電容本體,包括複數前述第一内部I 電極以及前述第二内部電極藉由前述陶瓷層積層,使得前i 述陶瓷層的短邊與前述電容本體的高度方向一致; j 一對第一外部電極,構成於前述電容本體之上面與下| 面,且電性連接於朝向前述陶瓷層之前述長邊暴露的前述IA rectangular hexahedron-shaped capacitor body includes a plurality of the aforementioned first internal I electrodes and the aforementioned second internal electrodes through the aforementioned ceramic lamination, so that the short sides of the aforementioned ceramic layer are consistent with the height direction of the aforementioned capacitor body; j a The first external electrode is formed on the upper and lower surfaces of the capacitor body, and is electrically connected to the I exposed to the long side of the ceramic layer. 2030-3679-P.ptd 第34頁 498373 六、申請專利範圍 第一内部電極;以及 | ! 第二外郁電極,構成於前述電容本體之側面,且分別 | i電性連接於朝向前述陶瓷層之前述短邊暴露的前述導引 !部。 ί ! 12.如申請專利範圍第Η項所述的羯於立體安裝之積 | 1 I 層陶瓷電容,其中前述第二外部電極以一帶狀沿前述電容 | 丨本體的前述四側面之全周面延伸。 i ! i 3.如申請專利範圍第Π項所述的鸬於立體安裝之積 1 j層陶瓷電容5其中前述第一外部電極係連接於前述電容本 | ί體外側的第一電路圖樣,且前述第二外部電極係連接於與| i前述第一電路圖樣不同的第二電路圖樣。 i 1 4.如申請專利範圍第ί 1項戶斤述的用於立體安裝之積 | |層陶瓷電容,其中前述積層陶瓷電容係埋設於一立體電路 I I基板中。 i X i I 15.如申請專利範圍第14項所述的闱於立體安裝之積 ί I層陶瓷電容,其中前述積層陶瓷電容之前述第一外部電極 ! 丨與前述第二外部電極係直接連接於構成於前述立體電路基 丨 板的電路圖樣中。2030-3679-P.ptd Page 34 498373 VI. Patent application scope First internal electrode; and |! The second outer electrode, which is formed on the side of the capacitor body, and is electrically connected to the ceramic layer respectively The aforementioned guide portion of the aforementioned short side is exposed. ί! 12. The product of three-dimensional installation as described in item 范围 of the patent application scope | 1 I-layer ceramic capacitor, wherein the second external electrode is in a strip shape along the entire periphery of the four sides of the capacitor | 丨 the body面 Extending. i! i 3. The three-dimensionally mounted product 1 j-layer ceramic capacitor as described in item Π of the application scope, wherein the first external electrode is connected to the first circuit pattern on the outside of the capacitor | The second external electrode is connected to a second circuit pattern different from the first circuit pattern. i 1 4. According to item 1 of the scope of the patent application, the product for three-dimensional installation | | layer ceramic capacitors, wherein the aforementioned multilayer ceramic capacitors are buried in a three-dimensional circuit I I substrate. i X i I 15. The three-dimensionally mounted I-layer ceramic capacitor as described in item 14 of the scope of the patent application, wherein the aforementioned first external electrode of the aforementioned laminated ceramic capacitor is directly connected to the aforementioned second external electrode system In the circuit pattern formed on the three-dimensional circuit substrate. 2030-3679-P.ptd 第35頁2030-3679-P.ptd Page 35
TW89128033A 2000-12-27 2000-12-27 Multilayer ceramic capacitor for three-dimensional mounting TW498373B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW89128033A TW498373B (en) 2000-12-27 2000-12-27 Multilayer ceramic capacitor for three-dimensional mounting

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW89128033A TW498373B (en) 2000-12-27 2000-12-27 Multilayer ceramic capacitor for three-dimensional mounting

Publications (1)

Publication Number Publication Date
TW498373B true TW498373B (en) 2002-08-11

Family

ID=21662516

Family Applications (1)

Application Number Title Priority Date Filing Date
TW89128033A TW498373B (en) 2000-12-27 2000-12-27 Multilayer ceramic capacitor for three-dimensional mounting

Country Status (1)

Country Link
TW (1) TW498373B (en)

Similar Documents

Publication Publication Date Title
TW530315B (en) Multiterminal multilayer ceramic capacitor
JP4953988B2 (en) Multilayer capacitor and capacitor mounting board
US6807047B2 (en) Electronic device and interposer board
JP2015216337A (en) Multilayer ceramic capacitor, array multilayer ceramic capacitor, manufacturing method therefor, and mounting board therefor
JP2008060342A5 (en)
US8917490B2 (en) Multilayered ceramic capacitor having dual layer-electrode structure
CN105895369B (en) Cascade capacitor
JP2014103327A (en) Multilayer capacitor
KR20160108905A (en) Multi-Layer Ceramic Electronic Component and Method of Fabricating the Same
JP5415827B2 (en) Surface mount devices
KR101514532B1 (en) Multi-layered ceramic capacitor
TW201101355A (en) Solid electrolytic capacitor
JP6136507B2 (en) Multilayer capacitor array
JP2001155953A (en) Multi-terminal laminated ceramic capacitor for three- dimensional mounting
JP2009054974A (en) Multilayer capacitor and capacitor mounting substrate
JP2008021771A (en) Chip-type solid electrolytic capacitor
TW498373B (en) Multilayer ceramic capacitor for three-dimensional mounting
JP4906990B2 (en) Through-type multilayer ceramic capacitors for three-dimensional mounting
EP1605477B1 (en) Multilayer ceramic capacitor for three-dimensional mounting
JP6115276B2 (en) Multilayer capacitor
JP3531861B2 (en) Three-dimensional mounting structure of three-terminal multilayer ceramic capacitors
KR101701056B1 (en) Capacitor component and board for mounting same
JP2009123938A5 (en)
JP3531860B2 (en) Three-dimensional mounting structure of multilayer ceramic capacitors
JP2008021773A (en) Chip-type solid electrolytic capacitor

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent