JPS63316950A - Data communication system - Google Patents

Abstract

PURPOSE:To accelerate the transfer speed of data, by providing a second storage circuit in a transmission side and a reception side, respectively, other than a first storage circuit, and writing the data on the storage circuit on the other side while the storage circuit on one side transfers the data, in a data communication system which takes synchronization by using the storage circuit. CONSTITUTION:First of all, in an initial cycle, the data is written on a MEM1 that is a first storage circuit at the transmission side. In the next cycle, the data in the MEM1 is read out, and is transferred to the reception side. At the reception side, transferred data is written on a MEM3 that is the first storage circuit at the reception side. During that time, at the transmission side, the next data is written on a MEM2 that is the second storage circuit at the transmission side. In the cycle after next, at the reception side, the data written on the MEM3 is read out, and simultaneously, the data written on the MEM2 at the transmission side, and is transferred to the reception side, and it is written on a MEM4 that is the second storage circuit at the reception side. During that time, the next data is written on the MEM1. Hereafter, such operation is repeated. The same operation is performed in a MEM circuit 2.

Description

[Detailed Description of the Invention] [Summary] In a data communication system that synchronizes using a memory circuit,
A second memory circuit is provided outside the first tα circuit on both the transmitting side and the receiving side, and while one memory circuit is transmitting and receiving data, data is written in the other memory circuit. Improve transfer speed.

[Industrial application field]

The present invention relates to a data communication system, and particularly to a data communication system with improved data transfer speed.

[Conventional technology]

In the field of data communication, asynchronous data communication is
Data communications are synchronized using memory circuits.

FIG. 4 is a diagram showing a conventional example, and FIG. 5 is a diagram showing a time chart of the conventional example.

In FIG. 4, MEM circuit 1 is a first transmission path, and MEM circuit 2 is a second transmission path.

The transmitting side is provided with memory circuits (MEM1, MEM3), and the receiving side is provided with memory circuits (MEM2, MEM4).
) is provided. P/S is a parallel/serial converter H, and S/P is a serial/parallel converter.

The operation of the conventional example will be explained using the MEM circuit 1 of FIG. 4 and the time chart of FIG. 5.

First, data is written into the memory circuit (MEMI) on the transmitting side. After that, the 1M data is stored in the memory circuit on the receiving side (M
Transfer to EM2).

The memory circuit (MEM2) on the receiver side is connected to the memory circuit (MEM2) on the transmitter side.
After all EMI> data has been transferred.

At the same time as reading the data in the memory circuit (MEM2) on the receiving side, the next data is written in the memory circuit (MEM1) on the transmitting side.

Data communication is performed by repeating the above operations.

During this time, in the MEM circuit 2 as well, the transmitting side memory circuit (
MEM3) and the receiving side storage circuit (MEM4)
Data communication similar to that of the EM circuit 1 is performed.

[Problem that the invention seeks to solve]

The conventional asynchronous data communication f3 uses a memory circuit (ME) on the sending side.
M1, MEM3), transfers the contents to the receiving side storage circuit (MEM2.MEM4), reads the data from the receiving side storage circuit (MEM2.MEM4), and at the same time stores the data in the sending side storage circuit (MEM2.MEM4). MEM1, MEM3)
Data communication was performed by repeating the operation of writing the next data into the memory circuit (ME) on the receiving side.
M2. There is a problem in that the data transfer efficiency is low because data is not transferred while data is being read from the MEM4) and data is being written to the transmitting side storage circuits (MEM1, MEM3) at the same time.

Means for Solving Problem c] The present invention provides a data ij1 communication system in which synchronization is achieved using a storage circuit, in which a second storage circuit is provided outside the first storage circuit on both the transmitting side and the receiving side, The data transfer speed is improved by writing data to one memory circuit while the other memory circuit is transmitting and receiving data.

FIG. 1 is a diagram showing the basic configuration of the present invention.

In FIG. 1, a MEM circuit 1 is a first transmission line.

MEM circuit 2 is the second transmission path, MEMI is the MEM circuit 1
MEM2 is the second memory circuit provided on the transmitting side of MEM circuit 1, MEM3 is ME
A first memory circuit provided on the receiving side of the M circuit 1, MEM4, is a second memory circuit provided on the receiving side of the MEM circuit 1, MEM4.
5 is a first memory circuit provided on the transmitting side of MP, M circuit 2;
MEM6 is a second memory circuit provided on the transmitting side of the MEM circuit 2.

MEM7 is a first memory circuit provided on the receiving side of the MEM circuit 2, MEM8 is a second memory circuit provided on the receiving side of the MEM circuit 2, P/S is a parallel/serial converter, and S/P is a serial/serial converter. It is a parallel converter.

[Effect]

The three inventions will be described in detail using the basic configuration diagram of the invention shown in FIG. 1 and the time chart of the invention shown in FIG.

First, the MEM circuit 1 will be explained.

In the first cycle, data is written to MEMI, which is the first storage circuit on the transmitting side.

In the next cycle, we will sell 8 MEMI data,
Transfer to the receiving side. On the receiving side, the transferred data is written into MEM3, which is the first storage circuit on the receiving side.

During this time, on the transmitting side, M
Write the following data to EM2.

In the next cycle, the receiving side reads out the data written in MEM3, and at the same time, the sending side reads out the data written in MEM2 and transfers it to the receiving side. write to. In the meantime, write the following data to MEMl.

Thereafter, repeat the above operation.

Next, the MEM circuit 2 will be explained.

In the first cycle, data is written into MEM5, which is the first storage circuit on the transmitting side.

In the next cycle, data from MEM5 is read and transferred to the receiving side. On the receiving side, the transferred data is written into MEM7, which is the first storage circuit on the receiving side. During this time, on the sending side, MEM7, which is the second storage circuit on the sending side, is written.
Write the following data to EM6.

In the next cycle, the receiving side reads the data written in MEM7, and at the same time, the transmitting side reads the data written in MEM6, transfers it to the receiving side, and receives it (the second write jfJ circuit on the δ side). MEM i
Write to ll. In the meantime, write the following data to MEM5.

Thereafter, repeat the above operation.

〔Example〕

FIG. 3 is a diagram showing the configuration of one embodiment of the present invention.

In FIG. 3, MEMI is the first storage circuit provided on the transmission side of the first transmission path, MEM2 is the second storage circuit provided on the transmission side of the first transmission path, and MEM3 is the first storage circuit provided on the transmission side of the first transmission path. MEM4 is a second memory circuit provided on the receiving side of the first transmission line, MEM5 is a first memory circuit provided on the transmitting side of the second transmission line, MEM6 is the second
The first memory circuit provided on the transmission side of the transmission line, 'MEM7
is a first storage circuit provided on the receiving side of the second transmission path.

MEM8 is a second memory circuit provided on the receiving side of the second transmission path, and P/S is a parallel/serial converter.

S/P is a serial/parallel converter.

First, the circuit consisting of MEMI to MEM4 will be explained.

In the first cycle, data is written to MEMl, which is the first storage circuit on the transmitting side.

In the next cycle, data from MEM1 is read and transferred to the receiving side. On the receiving side, the transferred data is written into MEM3, which is the first storage circuit on the receiving side. During this time, on the sending side, the MEM3, which is the second storage circuit on the sending side, is written.
Write the next data to M2.

In the next cycle, the data written in MEM3 is simultaneously read out on the receiving side.

On the transmitting side, the data written in MEM2 is read and transferred, and the data is transferred to MEM2, which is the second storage circuit on the receiving side.
4. Meanwhile, write the next data to MEMI.

Thereafter, repeat the above operation.

Next, a circuit consisting of MEM5 to MEMS will be explained.

In the first cycle, data is written into MEM5, which is the first storage circuit on the transmitting side.

In the next cycle, the data written in the MEM5 is read and transferred to the receiving side. On the receiving side, MEM7 is the first storage circuit on the receiving side.

During this writing of the transferred data, the sending side writes the next data into the MEM6, which is the second storage circuit on the sending side.

In the next cycle, the data written in MEM7 is simultaneously read out on the receiving side.

On the transmitting side, data written in MEM6 is read out, transferred to the receiving side, and written into MEM8, which is a second storage circuit on the receiving side. During this time, the next data is written into MEM5, which is the first storage circuit on the transmitting side.

Thereafter, repeat the above operation.

In the circuit of this embodiment, in order to organize the direction of data,
There are three gates in various places.

〔Effect of the invention〕

In the present invention, since two memory circuits are provided on both the transmitting side and the receiving side, there is no stop time for data transfer when reading data from the receiving side memory circuit and writing data to the transmitting side memory circuit. , allowing efficient data communication.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is a diagram showing a time chart of the present invention, FIG. 3 is a diagram showing the configuration of one embodiment of the present invention, and FIG. 4 is a diagram showing a conventional example. , FIG. 5 is a diagram showing a time chart of a conventional example. In FIG. MEM circuit 1: first transmission line MEM circuit 2; second transmission line MEMI: MEM@fi! The first memory circuit MEM2 on the transmitting side of MEM circuit 1: The second memory circuit MEM3 on the transmitting side of MEM circuit 1: The first memory circuit MEM4 on the receiving side of MEM circuit 1. Memory circuit MEM5: First memory circuit on the transmitting side of the MEM circuit 2 MEM6: Second memory circuit on the transmitting side of the MEM circuit 2 MEM7: First memory circuit on the receiving side of the MEM circuit 2 MEMB: First memory circuit on the receiving side of the MEM circuit 2 Second storage circuit on the receiving side

Claims (1)

[Claims] In a data communication system that synchronizes transferred data using a memory circuit, a second memory circuit (MEM2, MEM6) is provided in addition to the first memory circuit (MEM1, MEM5) on the transmitting side. At the same time, a second memory circuit (MEM4, MEM8) is provided on the receiving side in addition to the first memory circuit (MEM3, MEM7), and first, the first memory circuit (MEM1, MEM5) on the transmitting side is
), reads the transmitted data, transfers it to the receiving side, and stores it in the first memory circuit (MEM) on the receiving side.
3. While writing to MEM7), write the next transmission data to the second memory circuit (MEM2, MEM6) on the transmitting side, and then write the next transmission data to the first memory circuit (MEM3, MEM7) on the receiving side.
At the same time, read the received data from the second memory circuit (MEM2, MEM6) on the transmitting side and transfer it to the receiving side.
, MEM8), and during that time, the first memory circuit (MEM1, MEM5) on the transmitting side
), the next transmission data is further written, and the above operation is thereafter repeated.