JPS63315971A - Ic testing system - Google Patents

Abstract

PURPOSE:To quickly execute an information exchange between a processor and a storage device, and to improve a test speed by storing the information of each separate function in each separate storage device, and controlling independently each other each storage device thereof by each independent address information line. CONSTITUTION:In a storage device 28, a control program for decoding a program given from a host processor 21 and executing it is stored. Also, in a storage device 29, a sequence program for controlling actually a hardware module 25 is stored, and a storage device 30 stores a measured data. To these respective storage devices 28, 29 and 30, a common data input line 32 and a common data output line 33 are connected. Moreover, to phase respective storage devices 28, 29 and 30, each separate address line 34, 35 and 36 is connected from a processor 23, and independent address information can be placed on these address lines 34, 35 and 36 by the processor 23.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to an IC test system having a hierarchical distributed architecture.

"Prior Art" FIG. 4 is a diagram showing an example of the configuration of a conventional I'C test system. In the IC test system, a program in which a test sequence for testing a device under test is written is stored in a storage device 10, and a central processing unit 11 is stored in a storage device 1.
The test program is configured to be sequentially executed from 0, and the central processing unit 11 controls all test operations for testing, for example, a semiconductor memory device.

Hardware modules 13A, 13B, 13C to 13N are connected to the central processing unit 11 through a control line 12, and the control signals that the central processing unit 11 outputs as it decodes and executes the test program are connected to these hardware modules. Module 13A.

13B, 13cm13N.

The control signal is, for example, a predetermined input of the device under test ◇:
This is a control signal for supplying a 5.25V DC signal to the device under test. When this control signal is supplied, the hardware module 13A, for example, sends a 5.25V DC signal to the specified element of the device under test. Supplied to the input terminal.

The control signal output by the central processing unit 11 is, for example, a control Ta signal that instructs to measure the signal at the output terminal of the device under test. It is connected to the designated output terminal of the element and measures its signal voltage.

These hardware modules 13A, 13B.

The microprocessor 14 may be incorporated in 13C to 13N. Even if a huge number of logic elements are required if the test circuit is constructed using only general-purpose logic elements, by using the microprocessor 14 in most parts of the logic circuit, the circuit board can be made smaller. The microprocessor 14 in this case is merely a substitute for a logic element, and only performs simple predetermined sequence control, and is generally not used in a way that requires a special judgment function.

``Problem to be solved by the invention j The central processing unit decodes and executes the test program.In other words, it outputs control signals for testing the device under test to the hardware module, etc. Nobuo's measurements and judgment of the quality of the measurement results, etc.
It is necessary to carry out all kinds of arithmetic control necessary for the operation of the C test system, especially for the DC test, for example, the test of the DC characteristics seen from the terminals of the device under test. Therefore, the time required for arithmetic processing by the central processing unit increases,
The test speed of a test system cannot be easily increased.

In addition, the central processing unit controls the system.
A large amount of information is exchanged with the Q device, but the address information placed on the address line must be changed sequentially while accessing the storage device, making it difficult to test the device under test at high speed. If requested,
The delay time caused by reading and writing has become so large that it cannot be ignored.

"Means for Solving Problems" In this invention, a higher-level processing device controls the execution of a test program in which a test procedure is described line by line.
The actual interpretation and execution of the control contents described in the program line is entrusted to a lower-level processing device that is controlled by a higher-level processing device.

The lower processing device accesses the hardware module or updates the test status according to the description of the program line.

Furthermore, according to the present invention, the tα device is divided and configured according to function. That is, the storage device is composed of a storage device that stores a test program, a storage device that stores a control program for controlling the hardware module, and a storage device that stores measurement results by the hardware module. The device is configured to access each of these storage devices by a common data input line, a common data output line, and a separate address line.

"Operation of the Invention" According to the structure of the present invention, the upper processing device controls the execution of the test program line by line, and the actual decoding and execution of the program lines is carried out by a plurality of dedicated processes connected to the lower level. This is done in a distributed manner depending on the device.

Furthermore, according to the present invention, functionally classified information is stored in separate memory locations, and each of the memory devices is controlled independently of each other by independent address information lines. Therefore, proactive control of address information is possible, or the time required for saving and restoring address information can be significantly saved. Further, information can be quickly exchanged between the processing device and each storage device, and between each storage device.

Embodiment FIG. 1 is a block diagram showing a configuration example of an IC test system of the present invention. In this example, the IC test system employs a plurality of processing devices and is configured in a hierarchical architecture, particularly semiconductor DCC soot.

For example, input outflow current, leakage current, breakdown voltage, /l'i
Current consumption 1: Constructed to be suitable for performing output short-circuit current tests, etc. That is, there is a higher-level processing device 21 that controls the execution of a test program stored in a storage device 20, and a control hub 22 that is connected to this higher-level processing device 21, and under the control of which the actual program line is executed. A plurality of lower-level processing devices 23A, 23B, 23C~
23N and these lower processing devices 23A, 23B, 23
Hardware module 25A controlled by C to 23N
, 25B.

It is hierarchically composed of 25C to 25N.

That is, in the test program for testing the device under test, the test procedure is written sequentially line by line, and the host processing device 21 sequentially reads the test program line by line from the storage device 20 and executes the read program line. Control whether or not.

This upper processing device 21 has a plurality of lower processing devices 23.
A, 23B, 23C to 23N are connected, and the host processing unit 21 determines whether or not to execute the read program line while checking the test status of the device under test, and actually executes the program line that it has decided to execute. is a processing device 23A connected to a lower level.

23B, 23C to 23N.

The lower processing devices 23A, 23B, 23C to 23N are dedicated processing devices suitable for controlling test signals for the device under test, and are connected to hardware modules 25A, 25B, respectively.

The programming language is a language suitable for controlling 25C to 25N. The processing device 23 is the upper processing bag 'l121.
When it is entrusted with executing a program line, it decodes the program line and starts executing the program line. That is, the processing device 23 stores a control program in which a procedure for outputting a test signal to the device under test is described.
20, the control program is successively executed based on the result of decoding the given program line, and the procedure for controlling the input/output of the signals described in the program line is executed.

These lower processing devices 23A, 23B, 23C to 23N are each connected to a hardware module 25.
It has a convenient command system for accessing any of A, 25B, 25C to 25N, and changing test conditions (terminal connections and measuring instrument conditions), and is converted into macro commands.

It is configured so that a processing speed several tens of times faster than when the higher-level processing device 21 performs the same processing using its own instruction word system.

In addition, the processing device 23 not only executes the program line that it has been entrusted to execute from the higher-level processing device 21, but also decodes the program line and, based on the decoding result, provides information to the device under test in advance. given functional conditions,
For example, check the minimum clock width, human power conditions, timing relationships, prohibition conditions, etc. to avoid giving incorrect human power signals or even falling into a signal state that could lead to damage to the device under test. The program is programmed to output a test signal to the device under test or to perform control to measure the output signal while determining whether the test signal is present or not.

In addition, each processing device 23A, 23B, 23C to 23N is a hardware module 1-25A, 25B, 25C to 25N.
The measurement signal is taken in through the d (d), if necessary, for example, linear correction or logarithmic curve correction of the determined signal can be performed, and the obtained measurement data can be used as a reference value or dark value. Compare and judge whether it is good or bad, and log the data.

Hardware modules 25A, 25B, 25C-25
N has lower processing devices 23A and 23B.

A control signal is supplied as the control program lines 23C to 23N are executed, and a test signal is supplied to a designated input terminal of the device under test, or an output signal of a designated output terminal of the device under test is supplied. 4111 can be set.

These hardware modules 25A, 25B.

25C-25N may include a microprocessor 26. This microprocessor 26 replaces a large number of logic elements and performs predetermined sequence processing at high speed. This microprocessor 26 is a general-purpose processor whose operation is programmed in advance, and controls input/output of signals to and from the device under test Iu based on instructions from the processing unit 23.

Further, according to the present invention, each lower processing device 23A.

A storage device 27A connected to 23B, 23C to 23N.

27B, 27C to 27N each represent a plurality of storage devices 2
8A, 28B, 28C to 28N, and 29A.

2'lB, 2'lC~29N and...30A, 3
0B.

30C to 3ON, and each of these storage devices has separate address spaces. That is, each storage device 28A
, 28B, 28C-28N, and 29A.

29B, 29C to 29N and...30A, 30B
.

Separate address lines 31A and 31B to 31C correspond to the respective processing devices 23A for 30C to 3ON.

Connected from 23B, 23C to 23N.

FIG. 2 is a diagram showing an example of the configuration of the main part of the present invention. In this example, storage 27 includes three storage devices 28.29.3
0, and these storage devices 28, 29, and 30 are connected to address control circuits AI and A in one processing device 23, respectively.
2, connected via A3.

In this example, the storage device 28 stores a control program that decodes program lines given from the higher-level processing device 21 and assembles the actual execution order for executing the interpreted contents. There is.

The two storage devices include a hardware module 25A.

A sequence program for actually controlling 25B, 25C to 25N is stored. For example, the program controls the hardware module 25A to
c This is an instruction block consisting of a group of instructions that describes the sequence up to the output of the test signal, for example, the steps from controlling the measuring instrument of the hardware module 25B to measuring the output signal of the device under test to importing the measurement data. This is an instruction block that describes a sequence. That is, a minimum unit of instructions sequentially describing a sequence for operating the hardware modules 25A, 25B, 25C to 25N is stored as a block.

The control program in the storage device 28 selects a plurality of instruction block groups necessary by interpreting the program line from among these instruction block groups, determines the order of execution of the block instruction groups, and proceeds to execution. .

Storage device 30 is hardware module 25 in this example.
This is a storage device that stores data measured by A, 25B, 25C to 25N.

A common data input line 32 is connected to each of these storage devices 2B, 29.30, and data is supplied from the processing device 23 to each storage device 2B, 29.30 through this data input line 32. In addition, each of these storage devices 28, 29
．． Common data output for 30 &? t33 is connected, and each storage device 28, 29 is connected through this data output line 33.
．． 30 outputs data to the processing device 23.

In this invention, separate address lines 34, 35, 36 are connected from the processing device 23 to each of these storage devices 28, 29, 30, and these address lines 34, 35, 36 are connected to each of these storage devices 28, 29, 30, and each address line 34, 35, 36 is provided with independent address information by the processing device 23. It is possible to carry

With this configuration, for example, the processing device 23
is written using the address line 34 and control signal line 37.
When executing the control program in the 9-position 28, when the execution moves to an instruction block in two selected storage devices, the address line 35 is controlled independently of the address line 34 to store the data. Instruction blocks of the device 29 can be sequentially read and executed. Further, with the configuration of the present invention, it is possible to read the information of the next control program from the storage device 28 before the reading of the information for the execution of the instruction block is completed. The read 71 response information can be placed on the address line 34 in advance by, for example, stepping the 'JnP circuit A1.

In other words, 1η
Even in this case, the time for saving, restoring, or resetting the address information on the address line 34 does not increase.

Further, the storage device 30 includes a hardware module 25A,
This is a device for sequentially storing, for example, data measured using 25B, 25C to 25N.

When executing a control program or instruction block while changing the address information on the address lines 34 and 35, when storing measurement data one after another in the storage device 30, the address 1 for a130 on the address line 3G f
H can be stepped independently of the other address lines 34 and 35, thus greatly saving the time required for controlling address information when storing many measured data in sequence. Can be done.

Furthermore, for example, the measurement data taken into the tα4A station 30 by an instruction block in the storage device 29,
There are cases where it is desired to transfer to a predetermined data area belonging to that instruction block. In such a case, the storage device 30 simultaneously puts the transfer source address on the address line 36 and the transfer destination address on the address line 35, and executes a direct transfer command, so that the measured data in the storage device 30 is transferred to the data output line. 3
3 to the processing device 23 and then immediately transferred to the storage device 29 via the data input line 32.

In this way, information is organized by function and stored in separate storage devices 28.
．． 29. 30 and each separate recording tg device 2B,
29, 30 can be independently controlled 1111, so that the address lines 34, 35, .
36 advanced control is now possible, and prompt access to each storage device is now possible. In particular, it is possible to eliminate wasted time in address control when switching between functional sections required for processing by the processing device 23.

FIG. 3A is a diagram showing an example of the timing when one 4111 constant data is moved within the storage device 27 constructed according to the present invention. For example, the processing device 23 executes a command block stored in the storage device 27 and stores a large amount of sequentially measured measurement data in the storage device 30. At some point after the end of the measurement, all or part of the measurement data may be transferred to the data area following the instruction block in the storage device 29. Alternatively, there may be cases where it is desired to transfer those data to the processing data area of another instruction block for processing.

When performing such data transfer, address information (A) is placed on the address line 36 (waveform A), and the control signal line 37 is
Outputs an address setting signal to the storage device 3o via (
Waveform B). Address information (B) is placed on the address line 35 (waveform C), and an address setting signal is output to the storage device 29 (waveform D). Access time t specific to the storage device 30
When a read signal is output to the storage device 30 after (waveform E
), the data at the desired address (Δ) from the storage device 30 is placed on the data output yA33 (waveform F), and the data is placed on the data power line 32 via the processing device 23 (
Waveform G>.

Furthermore, when a write signal is applied to the storage device 29 after the access time t specific to the storage device 29 (waveform H), the data on the data force line 32 is transferred to a predetermined position (B
). In this way, one piece of measurement data is transferred from the storage device 30 to the storage device 29 via the processing device 23.

On the other hand, FIG. 3B is a diagram showing a timing example in the conventional case where the memory device 27 is not separated by function and is connected to only one address line.

Put the address information (A) on the address line (to the waveform - ○) and write it through the control signal line! Setting the address on the device (3)
(waveform B-■). A read signal is output after an access time t specific to the storage device (waveform C). Data is placed on the data output cotton 33 from the desired address (A) of the storage device (waveform D), and the processing device 23 transfers this data to
Load into temporary storage register. Next, address information IH (, B''I) is placed on the address line (waveform A-■), and an address setting signal is output (waveform B-■).
Load data on lA32 (waveform E), and output a write signal after the access time t specific to the iQ device (waveform F).
, writes data to a predetermined address (B) of the storage device.

Taking the example of transferring one data, these two timing diagrams show that configuring the storage device by function and using separate address lines as shown in this invention has a great effect. be revealed. The effect of this invention becomes even greater when a large amount of data is transferred.

Also, in this waveform diagram, addresses ↑1'' I signals A and B are supplied to the storage devices 30 and 29 at different timings, but since different address lines are connected, they are supplied at the same timing. Address information can also be output.

In addition, in the explanation so far, there are multiple processes that have a hierarchical structure.
I! Although the case of a distributed processing system using devices has been described, the present invention is also effective between the first processing 'A' If and a storage device.

"Effects of the Invention" As explained above, according to the present invention, a higher-level processing device exclusively controls the execution of a program line, and the actual execution of the program line is distributed to multiple lower-level processing devices. Since we have constructed a hierarchical structure in which the test is carried out in a hierarchical manner, and we have used the optimum command system for each layer, the processing up to the output of control '+1 It can be carried out.

Further, according to the present invention, since an address line is provided for each storage device classified by function, when the processing device accesses each storage device, it is possible to output an address faster than before, or Different addresses can be output at the same time. Therefore, information can be exchanged quickly between the processing device and the storage device, which is extremely effective in increasing testing speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing the main parts of the present invention, and FIG. 3A is a timing example when accessing the stored value Q in the structure according to the present invention. FIG. 3B is a diagram showing an example of timing when accessing a 4Q device having a conventional configuration, and FIG. 4 is a diagram showing an example of the configuration of a conventional IC test system. 10: Storage device, 11: Central processing unit, 12: Control port line, 13: Hardware module, 14: Micro processor sensor, 20; Storage device, 21/Upper processing device, 22
; System? ] 11 bus, 23: lower processing unit, 24: control f
ff11 line, 25; hardware module, 26: microprocessor, 27.28.29.30: storage device, 31; address line, 32. Data input line, 33: Data output line, 34° 35.36: Address line, 37; Control signal line, Δ1°Δ2. A3 near address system? ] Mouth circuit. Patent applicant: Advantes Co., Ltd.
Professor Kusano
Takuo 2 Figure μ h Ren (・Snoring device fang 311] A Figure 3 B F!, -t

Claims (1)

[Claims] (1) A storage device that stores programs, a storage device that stores data for controlling hardware modules, a storage device that stores measurement results, and data that is commonly provided to these multiple storage devices. An input line, a data output line provided in common to these multiple storage devices, one processing device that accesses these storage devices, and an address line provided for each storage device from the processing device. Equipped with an IC test system.