JPS63310161A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize a desired characteristic by the use of a small area so as to suppress an increase in a chip size, by forming a buried layer and a third layer, which penetrates through a base region of a transistor and reaches the buried layer, so as to compose a capacity (large capacity). CONSTITUTION:A P<+> layer (large in its concentration) 21 is first formed by diffusion in a region 15, where a base P<+> (small in its concentration) of an NPN transistor Q0 is originally formed by diffusion, as shown in hatching, until it reaches a buried layer 14. This P<+> layer 21 is formed together with an element isolation P<+> layer 13, and so consequently a capacitance (junction capacitance can be formed of the P<+> layer 21 and the N<+> buried layer 14. Afterwards a base layer P<+> layer 15 and the like are formed. Accordingly a desired characteristic can be realized by the use of a small area, and also an increase in a chip size can be suppressed.

Description

[Detailed description of the invention] [Aim of invention, target (Industrial application field) The present invention relates to a semiconductor device comprising a composite element.

(Prior Art) An example of an applied circuit using this type of composite element is shown in FIG. This circuit consists of a constant current source I, a transistor QCs
...Q8. ..., but in this case, the base current "1211113t..." makes the collector current ICQ1 of the transistor Q small, and the output current "l*xss..." also becomes small ( mirror characteristics)
Since errors occur, a transistor Q0 is provided to prevent this, and a capacitor C and a resistor R0 are provided to prevent Qo from oscillating. In the example of FIG. 2, the composite element is the dotted line portion 1, that is, the transistor Q0 and the capacitor C.

FIG. 3(a) is a pattern plan view of the above-mentioned composite element part;
1 is a P-type substrate, 12 is an N-type epitaxial layer, and 13 is a P-type substrate.
14 is an N type buried layer, 15 is a P type element isolation diffusion layer.
16 is an N-type diffusion layer, and 17 is an electrode extraction portion. Here, the capacity is "c=c, 1+CCB".

(Problems to be Solved by the Invention) The disadvantages of the above-mentioned conventional composite elements are: (a) Since the two elements (QO and C) are configured separately,
This increases the area occupied by the device and increases the chip size, leading to an increase in cost.

(b) When obtaining C from the collector-pace parasitic capacitance of the transistor Qo, the capacitance per unit area is relatively small, so if you want to increase the capacitance, use a single element configuration instead of using a separate configuration for C. , it is necessary to make the base P+ region 15 wide, and the area of the element becomes large.

Therefore, it is an object of the present invention to realize desired characteristics in a small area in a monolithic integrated circuit, thereby increasing the chip size. Our objective is to provide a semiconductor device (composite element) that can reduce

[Structure of the invention] (Means and effects for solving the problems) The present invention has the following features:
a conductivity type base, a second conductivity type first layer formed on the base, a second conductivity type buried layer formed between the base and the first layer; The first formed in the layer
a second layer of conductivity type, a third layer of first conductivity type with a high α degree that penetrates this layer and reaches the buried layer, and a layer other than the third layer within the second layer. The second part formed in
a fourth layer of conductivity type;
and a fifth layer of second conductive plastic formed on a portion other than the layer, and a capacitor is formed between the buried layer and the third layer. That is, the present invention has an advantage in that the capacity (large capacity) is formed by the 8g3 layer that penetrates the entire base region of the transistor and reaches the buried layer, and the buried layer.
This does not require the parasitic capacitance t (small capacitance) of the prior art, and there is no need to configure two separate elements, making it possible to achieve desired characteristics in a small area.

(Example) An example of the present invention will be described below with reference to the drawings. 1st
The figure (- indicates the same embodiment) is a turn plan view, the figure (b) is the same sectional view, and the figure (d is the equivalent circuit diagram), but these correspond to those in Figure 3, so there is no correspondence between them. The same reference numerals are used to omit the explanation, and the characteristic points will be explained.The characteristic of this embodiment is that the base P'' (low concentration) of the conventional (FIG. 3(b)) For example, ρ8 Ko20
In the region 15 where a P+ layer (with a high concentration, e.g. 1 in ρ8) was formed by diffusion, as shown by
0Ω/portion) 2z1ks before reaching the buried layer 14. This P+ layer 21 is the P+ layer 13 for element isolation.
It can be formed together with Now P+ layer 21 and N+
A capacitance f (junction capacitance f) C=Ccll was formed by the buried layer 14. After that, the base P+ layer 15 and the like may be formed.

Also, in the area surrounded by the dotted line in Fig. 1(b),
eep) By implanting N+, the resistance r between the N+ layer for extracting the collector pole and the buried layer 14 is increased. can be made smaller. Although this DigiN layer 22 is unnecessary depending on the purpose of use, the resistor r (gives a negative impact on the high frequency characteristics).

As shown in FIG. 1, the P+ layer 21 is diffused into the base region 15 of the NPN (NPN) Lanzoster Q0 until it reaches the buried layer 14, and the parasitic capacitance between the base and collector of the transistor Q0 of the prior art (FIG. 3) is formed. (small capacitance) becomes C==C,'c (large capacitance) in Fig. 1, eliminating the need for a two-regulator configuration as shown in Fig. 3, and achieving the desired characteristics in a small area. .

[Effects of the Invention] As explained above, the present invention provides a semiconductor device that achieves desired characteristics in a small area in a monolithic integrated circuit and suppresses increase in chip size! (composite element).

[Brief explanation of drawings]

FIG. 1 (a), (b), (each cl is an embodiment of the present invention) J? Turn plan view, cross-sectional view, and equivalent circuit diagram; Figure 2 is an application circuit diagram using a composite element; Figure 3 (ml.) (b) and (c) are the mother turn plan view and cross-section of a conventional device, respectively. 1 is an equivalent circuit diagram. 1... Composite element, 11... P-type substrate, 12... N
Mold work e taxial layer, 13... P-type element isolation expansion layer, 14... N-type buried layer, 15... P-type diffusion layer,
16... N type expansion layer (emitter), 17... Electrode extraction part, 21... P weir high concentration diffusion layer, 22... Deag N type layer, Qo... NPN transistor, C.
...capacitance, rc...parasitic resistance. Applicant's agent Takehiko Suzue (a) (b) Figure 1 Figure 2 (a) (b) Figure 3

Claims (3)

[Claims] (1) a first conductivity type base, a second conductivity type first layer formed on the base, and a second conductivity type buried layer formed between the base and the first layer; , a second layer of the first conductivity type formed on the first layer, and a third layer of the first conductivity type with a high concentration penetrating this layer and reaching the buried layer;
a fourth layer of a second conductivity type formed in a portion of the second layer other than the third layer; and a fourth layer of a second conductivity type formed in a portion of the first layer other than the second layer. a fifth layer of a second conductivity type, and a capacitor is formed between the buried layer and the third layer. (2) The semiconductor device according to claim 1, further comprising a deep layer of a second conductivity type that connects the fifth layer and the buried layer. (3) The semiconductor device according to claim 1, wherein the third layer is formed together with a first conductivity type high concentration layer for element isolation.