JPS6330921A - Timer circuit - Google Patents

Abstract

PURPOSE:To make it unnecessary to correct a time data by forming a counter and a port as one body, and giving the same address. CONSTITUTION:A port 3 and a counter 4 are formed as one body and has one address as a timer circuit 2, and by one instruction from a CPU 1, a level data of a serial signal and a time data are written, respectively. These data are updated from the CPU 1, and the port 3 outputs the serial signal. In this way, it becomes unnecessary to correct the time data, and also, a program size becomes small, and if necessary, other instruction can be executed, and a microprocessor can be operated at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a timer circuit that is controlled by a CPU and sends out time-managed serial signals.

[Conventional technology]

FIG. 3 is a block diagram of a microcomputer showing a conventional example of this type of timer circuit, FIG. 4 is a sequence diagram of CPUI commands, and FIG. 5 is a serial signal format diagram.

This timer circuit is composed of a counter 4 and a port 3, in which the time and level of pulses constituting the serial signal are set by the CPU 1 via a data bus 5, respectively. In this case, as shown in Fig. 5, the value of the serial signal “
0'' is represented by a high level at time T followed by a low level, and a value "1" is represented by a high level at time T and a subsequent low level at time 2T. To set this serial signal in the timer circuit, as shown in Figure 4,
In the first instruction cycle, address bus 8. Select port 3 via address decoder 7 and select “1” or “
0", and in the next instruction cycle select counter 4 and set the value corresponding to T or 2T.

When the counter 4 completes counting the time data by π1, it sends an interrupt signal to the CPU 1 from the control signal bus 6.

As a result, CP(J1) executes the above-mentioned instruction again and updates the data of port 3.counter 4.

Thereafter, this operation is repeated and a serial signal is sent out.

[Problem that the invention seeks to solve]

The conventional timer circuit described above has the following drawbacks because the counter and the port are provided separately and have different addresses, and two instructions are required to set one piece of serial data.

■ The time when data is set to the port and the time when data is set to the counter are different by one instruction.
Corrections must be made to the values set in the counters.

■ Also, since data must be set to ports and counters many times, it is fine if the program capacity is large, but if it is small, it will inevitably become a problem. Since it is required, it does not take much time to output the serial signal.

■ Ports and counters each have different addresses, so the address recorder becomes larger, and if you need to store data sent to the port and data sent to the counter, separate registers are required, and the number of registers increases. Put it away.

[Means for solving problems]

The timer circuit of the present invention is characterized in that a counter and a port are integrated and assigned the same address.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a microcomputer including an embodiment of the timer circuit of the present invention, and FIG. 2 is a sequence diagram of CPU instructions. The same numbers as in FIG. 3 indicate the same items.

The port 3 and the counter 4 are integrated and have one address as the timer circuit 2, and the level data and time data of the serial signal are respectively written by one command from CPIJ1. Similar to the conventional example, these data are stored in CPU 1
Port 3 outputs a serial signal.

〔Effect of the invention〕

As explained above, the present invention has the following effects by integrating a counter and a port and giving them the same address.

■ Since the time data of the serial signal and the output data are set at the same time with one command, there is no need to correct the time data as in the past.

(2) Since setting data requires only one instruction, which is one less than the conventional method, the program size is reduced, and as a result, other instructions can be executed if necessary, allowing the microprocessor to operate at high speed.

■ By making the port and counter addresses the same, the circuit scale of the address decoder can be reduced.

■ It is no longer necessary to separately store the data sent to the port and the data sent to the counter as in the past; they can be stored in one register, and the number of registers can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a microcombinator including an embodiment of the timer circuit of the present invention, and FIG.
3 is a block diagram of a conventional example, FIG. 4 is an instruction sequence diagram of the CPU 1, and FIG. 5 is a serial signal format diagram. 1...CPU, 2...Timer circuit, 3...Port, 4...Counter, 5...Data bus, 6...
IIIt[I signal bus, 7...address decoder, 8
...address bus. Patent applicant: NEC Corporation Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] Consisting of a counter and a port to which the time and level data of the pulses constituting the serial signal are respectively set by the CPU, and when the counter finishes counting the set data, the serial signal is sequentially output from the port. 1. A program-controlled timer circuit in which the counter and timer data are respectively updated from a CPU at the same time as the counter and timer data are updated by a CPU, characterized in that the counter and the port are integrated and assigned the same address.