JPH0228834A - Register writing circuit - Google Patents

Abstract

PURPOSE:To shorten a time necessary for I/O write by executing the operation of 2 bus cycles, which is needed for parameter set to a register, with 1 bus cycle. CONSTITUTION:An index on a data bus 10 is held to one of index registers 1 and supplied to a selector 4. In such a case, when writing to a register 6 is a word write mode, the index on the data bus 10 is selected by the selector 4 and one of the registers 6 is selected according to the said index. Data on the data bus 10 are written to the selected register 6 and the I/O write is finished in one bus cycle. In the case of byte write, the index on the data bus is once held to the register 1 in the first bus cycle and the data are written in the next bus cycle. Then, the I/O write is finished in the 2 bus cycles.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) The present invention has an index port and a data port on an I/O space, and selects any register from a plurality of registers based on an index value. The present invention relates to a register write circuit having a function of writing data to the register, and particularly relates to a register write circuit which aims to shorten the time required for Ilo to the register.

(Prior Art) Conventionally, in LSIs such as microcomputer components that have multiple registers inside, index numbers are attached to each of the registers, and multiple registers exist in one I/O space. I'm letting you do it.

To write data to this register, first write an index to the index register, set the index, and then write data to the register indicated by the index.

(Problem to be solved by the invention) Therefore, in the past, a bus cycle was required for each of index write, index write, and data write, and I/O write was performed over two bus cycles. .

Therefore, each time one parameter is set in a register, it takes two bus cycles for two I/O writes.

The present invention has been made in view of the above circumstances, and allows the operation of two bus cycles, which was required for setting parameters to registers, to be performed in one bus cycle.
It is an object of the present invention to provide a register write circuit that reduces the time required for O write.

Structure of the Invention (Means and Effects for Solving the Problems) The present invention is an I/
In order to perform the O write within one bus cycle, a circuit is provided that concurrently executes the writing of an index to the index register and the operation of giving the index to a selection circuit that selects a register into which data is to be written.

In other words, in a register write circuit that has the function of selecting any register from a plurality of registers based on an index value and writing data to the same register, the index value and data are transferred simultaneously as shown in Figure 1. a register selection circuit 5 that selects one register from a plurality of registers 6 based on the index value on the bus /O; The device is equipped with a circuit 7 for writing data, so that register designation according to an index value and data writing to the designated register can be executed in one bus cycle.

In addition, in order to enable I/'O writes in two bus cycles as before, there are two types: byte writes, which perform I/O writes in two bus cycles, and word writes, which complete I/O writes in one bus cycle. Provide a circuit for switching.

That is, in a register write circuit that has the function of selecting an arbitrary register from a plurality of registers based on an index value and writing data to the same register, the index value and data are transferred simultaneously as shown in FIG. a data bus IO, a plurality of index registers that store index values on the same bus/O, a first index selector 3 that selects one of the index registers, and an index of the index register selected by the selector 3. a second index selector 4 that selects a value or an index value on the bus /O; and a register selection circuit 5 that selects one register from the plurality of registers 6 based on the index value selected by the selector 4. and the register selected by the same circuit 5 is connected to the bus/
A circuit 7 for writing data on O is provided, so that register designation according to an index value and data writing to the designated register can be selectively executed in one pass cycle or two bus cycles.

Thereby, the I/O write can be completed in one bus cycle, and the I/O write time can be significantly shortened and the processing speed can be improved. Furthermore, since I/O writing can be performed in two bus cycles as in the past, compatibility with existing systems can be maintained.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, 1 indicates a plurality of (n) index registers (IRI to I
Rn). 2 is an address decoder that decodes the address value on the address node 20. Reference numeral 3 denotes a selector (first inte/sock selection circuit) which selects one of the index registers (IR1 to IRn) according to the decoded output of the address decoder 2. A selector 4 (second index selection circuit) selects either the index on the data bus /O or the integer selected by the selector 3. 5 is address decoder 2
This is a register selection circuit that selects one of the registers 6 in response to the decoded output of the register 6 and the index selected by the selector 4. Reference numeral 6 denotes a plurality of (n) registers for storing data on the data bus/O. 7 is a register selection circuit 5
This is a write control gate that performs write control of the register 6 selected by .

The operation of one embodiment of the present invention will now be described with reference to FIG.

The index on the data bus /O is held in the index registers (IR1-IRn) 1 - (lRi) and is supplied to the selector 4.

At this time, when writing to register 6 is in word write mode, the index on data bus /O is selected by selector 4, one of registers 6 (register i) is selected according to the index, and the selected The data on the data bus/O is written to the registered register (i) 6, and the I/O write is completed within one bus cycle.

That is, at this time, the selector 4 selects an index on the data bus /O according to the decoded output of the address decoder 2, and the register selection circuit 5 selects one of the registers 6 (register i) according to the index. This results in
Data on the data bus /O is written into the selected register (i) 6 in synchronization with the write strobe signal.

In this way, in the case of a word write, the I/O write is completed within one bus cycle.

Also, when writing a byte, the index on the data bus is first held in one of the index registers (IR1 to IRn) (lRi) in the first bus cycle, and then stored on the data bus /O in the next bus cycle. data is written and the I/O write is completed within two bus cycles.

That is, in this case, first, the index selected by selector 4 or selector 3 is selected according to the decoded output of address decoder 2, and therefore the index on data bus /O is not supplied to register selection circuit 5. The index register (IRD 1) selected by the selector 3 is selected by the register selection circuit 5. In the next bus cycle, write data is sent onto the data bus /O, and the same data is sent to the register selected by the register selector 5. circuit 5
is written to register (i) 6 selected by .

In this way, I/O in two bus cycles as in the past
O-write can be performed.

[Effects of the Invention] As described in detail above, according to the present invention, an index port and a data port are provided on the I/O/O, and an arbitrary register can be selected from a plurality of registers according to the index value, and the same register can be selected. In a register write circuit with a function to write data, there is a data bus in which index values and data are transferred simultaneously, and a selection in which one register is selected from the above multiple registers based on the index value on the same bus. The circuit has a circuit and a circuit that writes data on the bus to a register selected by the circuit, and is configured to execute register specification according to an index value and data write to the same specified register in one bus cycle. As a result, the operation that required two bus cycles to set parameters to the register can be performed in one bus cycle, and ■
/O The time required for writing can be shortened.

Further, according to the present invention, the register write function has an index port and a data port on the I/O space, and has the function of selecting any register from a plurality of registers based on the index value and writing data to the same register. The circuit includes a data bus on which index values and data are transferred simultaneously, a plurality of index registers on the same bus that store index values, and a first index selection circuit that selects one of the index registers. a second index selection circuit that selects the index value of the index register selected by the circuit or the index value on the bus; and a second index selection circuit that selects one register from the plurality of registers based on the index value selected by the circuit. It has a register selection circuit to select a register, and a circuit to write data on the bus to a register selected by the same circuit, and designates a register according to an index value and writes data to the same designated register in one bus cycle or two bus cycles. By having a configuration that allows selective execution of I/
O write can be completed in one bus cycle, greatly reducing I/O write time, and I/O write can be completed in two bus cycles as before, maintaining compatibility with existing systems. be able to.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Index register (IRI to IRn), 2
... address decoder, 3... selector (first index selection circuit), 4... selector (second index selection circuit), 5... register selection circuit, 6.
. . . Register (register 1 to register n) 7 . . . Write control gate, /O . . . Data bus, 20 . . . Address bus. Applicant's agent Patent attorney Takehiko Suzue

Claims (2)

[Claims] (1) In a register write circuit that has an index port and a data port on the I/O space, and has the function of selecting any register from multiple registers based on the index value and writing data to the same register. , a data bus on which index values and data are transferred simultaneously;
The circuit includes a selection circuit that selects one register from the plurality of registers based on the index value on the same bus, and a circuit that writes data on the bus to the register selected by the circuit, and according to the index value. A register write circuit characterized by specifying a register and writing data to the same specified register in one bus cycle. (2) In a register write circuit that has an index port and a data port on the I/O space, and has the function of selecting any register from multiple registers based on the index value and writing data to the same register. , a data bus on which index values and data are transferred simultaneously;
a plurality of index registers that store index values on the same bus; a first index selection circuit that selects one of the index registers; and a first index selection circuit that selects one of the index registers; A second index selection circuit selects one register from the plurality of registers based on the index value selected by the second index selection circuit, and a register selection circuit selects one register from the plurality of registers based on the index value selected by the second index selection circuit. 1. A register write circuit, comprising a circuit for writing data, and selectively executing register designation according to an index value and writing data to the designated register in one bus cycle or two bus cycles.