JPS63308934A - Manufacture of compound semiconductor device - Google Patents
Manufacture of compound semiconductor deviceInfo
- Publication number
- JPS63308934A JPS63308934A JP14658187A JP14658187A JPS63308934A JP S63308934 A JPS63308934 A JP S63308934A JP 14658187 A JP14658187 A JP 14658187A JP 14658187 A JP14658187 A JP 14658187A JP S63308934 A JPS63308934 A JP S63308934A
- Authority
- JP
- Japan
- Prior art keywords
- region
- ion
- semiconductor device
- boron
- high resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 150000001875 compounds Chemical class 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 11
- 229910052796 boron Inorganic materials 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 9
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 9
- 229910052751 metal Inorganic materials 0.000 abstract description 6
- 239000002184 metal Substances 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 abstract description 2
- 150000002739 metals Chemical class 0.000 abstract description 2
- 238000002955 isolation Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 235000009508 confectionery Nutrition 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
Landscapes
- Element Separation (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は化合物半導体装置に係り、特にＧ ａ Ａ ｓ
（ガリウム砒素）のＭＥＳ （Ｍｅｔａｌ Ｓｅｍ１ｃ
ｏｎｄｕｃｔｅｒ ）ＦＥＴを基本素子として集積化し
たアイリレーション構造に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a compound semiconductor device, and in particular to a GaAs
(Gallium arsenide) MES (Metal Sem1c)
The present invention relates to an eye relation structure in which FET (onductor) is integrated as a basic element.
従来のＭＥＳ−ＦＥＴ （Ｍｅｔａｌ Ｓｅｍ１ｃｏｎ
ｄｕｃｔｅｒ ＦＥＴ）は、第３図に示すように、半絶
縁性Ｇ ａ Ａ ｓ基板１にシリコンのイオン注入を用
いてｎ型活性層６゜７を形成し、この活性層６，７を積
うようにゲート金属８，９を形成して、ショットキー接
合とし、この活性層６，７両端部に高濃度ｎ＋領領域形
成して、ソース領域２，４、及びドレイン領域３゜５と
したいわば半絶縁性ＧａＡｓ基板１の海の中に、ＭＥＳ
−ＦＥＴＯ島を形成して成り、更にＧａＡｓ１Ｃはこれ
らＦＥＴの集合より成る。Conventional MES-FET (Metal Sem1con
ducter FET), as shown in FIG. 3, an n-type active layer 6.7 is formed in a semi-insulating GaAs substrate 1 by silicon ion implantation, and these active layers 6 and 7 are stacked. Gate metals 8 and 9 are formed to form a Schottky junction as shown in FIG. In the sea of semi-insulating GaAs substrate 1, MES
-FETO islands are formed, and GaAs1C is further composed of a collection of these FETs.
従って、素子間のアイソレーションは、 ＧａＡｓ基板
１の半絶縁性に依する。しかしながら、現状の技術で達
成し得る絶縁性は高々１０Ω・α程度であり、しかもＧ
ａ Ａ ｓ基板１の抵抗値は炭素のシャロー・アクセ
プターと、ＥＬ２（深い準位に与えられた呼称；コンタ
クジョン・バンドエツジヨリ、約０．８ｅＶ程深いとこ
ろの禁１ｕ１］帯中に準位を形成する）のディープ・ド
ナーとの補償作用（Ｃｏｍｐｅｎ−ｓａｔｉｏｎ Ｅｆ
ｆｅｃｔ）により維持されている。しかもこれら両準位
とも現状技術では制御性を欠くので、実際に育成される
結晶のもつ抵抗値は、約１０’乃至１０Ω・口と広範囲
にわたる。Therefore, isolation between elements depends on the semi-insulating property of the GaAs substrate 1. However, the insulation that can be achieved with current technology is at most about 10Ω・α, and
The resistance value of the A s substrate 1 is due to the shallow acceptor of carbon and the level in the EL2 (name given to deep level; contact band edge, about 0.8 eV deep level) band. Compensation effect with deep donor (forming Ef)
fect). Moreover, since the current state of the art lacks controllability in both of these levels, the resistance values of the actually grown crystals range over a wide range from about 10' to 10 Ω.
一方、ＭＥＳ−ＦＥｉ−’ ｉ基本素子とせしく）ａＡ
ｓＩＣでは、集積度が向上するにつれ、高い素子間アイ
ソレーションが要求され、しかも、適用回路によっては
高密度集積によシ接近したＦＥＴ間に電源電圧、もしく
はこれに近い電位が印加されることになり１．素子間分
離の重要性が増す。On the other hand, MES-FEi-' i basic element) aA
In sIC, as the degree of integration increases, high isolation between elements is required, and depending on the applied circuit, the power supply voltage or a potential close to this may be applied between FETs in close proximity to each other due to high density integration. Nari 1. The importance of isolation between elements increases.
実際問題としである閾値電圧以上の電圧が印加されると
、それまでオーム性を示していた基板性の電流−電圧特
性が急激に過大電流が流れ始めるため、素子間アイソレ
ーションは破綻する。この問題を解決する一つの手段と
しては、素子間にプロトン（Ｈ）をイオン注入して、高
抵抗領域を形成する方法がある。しかしながら、この方
法では、４００”Ｃ近傍の低温熱処理により、高抵抗領
域が焼鈍化され、高抵抗領域が完全に保持できないとい
う難点があった。本発明の目的は、前記問題点が解決さ
れ、高抵抗領域が充分に保持できるようにする化合物半
導体装置の製造を提供することにある。In practice, when a voltage equal to or higher than a certain threshold voltage is applied, the current-voltage characteristics of the substrate, which had previously exhibited ohmic properties, suddenly begin to allow an excessive current to flow, causing isolation between elements to fail. One way to solve this problem is to form a high resistance region by implanting protons (H) between elements. However, this method has the disadvantage that the high-resistance region is annealed due to the low-temperature heat treatment at around 400"C, and the high-resistance region cannot be maintained completely.The object of the present invention is to solve the above-mentioned problems, An object of the present invention is to provide manufacturing of a compound semiconductor device in which a high resistance region can be sufficiently maintained.
本発明の構成は、ガリウム砒素のＭＥＳ−ＦＥＴを基本
素子とした化合物半導体装置の製法において、各素子間
を隔てるように、プロトン及びボロンを同一領域にイオ
ン注入する工程を有することを特徴とする。The structure of the present invention is characterized in that a method for manufacturing a compound semiconductor device using a gallium arsenide MES-FET as a basic element includes a step of ion-implanting protons and boron into the same region so as to separate each element. .
次に図面を参照しながら本発明の詳細な説明する。第１
図は本発明の第１の実施例の化合物半導体装置の製法を
示す断面図である。同図において、半絶縁性の（３ａＡ
ｓ基板１に、シリコン（Ｓｉ）のイオン注入により、活
性層領域６．７全形成し、しかるのちに、ソース領域２
，４及びドレイン領域３．５が形成され、更にゲート金
属８．９を形成して、ＭＥ Ｓ −Ｆ ＥＴは完成する
。このとき、活性領域６，７と、ンース飴域２，４、及
びドレイン領域３，５の形成順序が逆転してもよい。プ
ロトン、及びボロンをイオン注入法により、領域１０に
ドンブして、高抵抗領域は完成する。第２図は本発明の
第２の実施例の化合物半導体装置の製法を示す断面図で
ある。同図において、ＧａＡｓ基板上１に、プロトン及
びボロンを領域１１にイオン注入し、しかるのち低抵抗
値をもつエピタキシャル層１３を形成し、以後前記第１
の実施例と同様にして、ＭＥＮ−ＦＥＴを形成し、しか
るのち同様に領域１２にプロトン及びボロンをイオン注
入して高抵抗領域を形成し、第２の実施例は完成する。Next, the present invention will be described in detail with reference to the drawings. 1st
The figure is a sectional view showing a method for manufacturing a compound semiconductor device according to a first embodiment of the present invention. In the same figure, semi-insulating (3aA
The entire active layer region 6.7 is formed on the s-substrate 1 by ion implantation of silicon (Si), and then the source region 2 is formed.
, 4 and a drain region 3.5 are formed, and a gate metal 8.9 is formed to complete the ME S-FET. At this time, the order of formation of the active regions 6, 7, the loose candy regions 2, 4, and the drain regions 3, 5 may be reversed. The high resistance region is completed by implanting protons and boron into the region 10 by ion implantation. FIG. 2 is a sectional view showing a method for manufacturing a compound semiconductor device according to a second embodiment of the present invention. In the figure, protons and boron are ion-implanted into a region 11 on a GaAs substrate 1, and then an epitaxial layer 13 having a low resistance value is formed.
A MEN-FET is formed in the same manner as in the second embodiment, and then proton and boron ions are similarly implanted into the region 12 to form a high resistance region, thereby completing the second embodiment.
以上箱１．第２の実施例から明白なように、まずプロト
ンイオン注入により形成し、更に同一領域にボロンを注
入するいわゆるダブルイオン注入方式を採用する。また
、プロトンとボロンとの順序は逆となってもよい。Above box 1. As is clear from the second embodiment, a so-called double ion implantation method is adopted in which the proton ion implantation is performed first, and then boron is implanted into the same region. Furthermore, the order of protons and boron may be reversed.
以上説明したように、本発明は、プロトンとボロンとの
ダブルイオン注入により、プロトンのみの場合に比較し
て、イオン注入領域ははソ完全に非晶質化され、低温で
の焼鈍化はほとんど進行せず、イオン注入領域は、はソ
高抵抗のま＼保持され、従って、ＩＣ製造の後工程での
熱効果、例えはアロイ工程もしくは組立工程での４００
″Ｃ前後の熱処理によっても高抵抗層は保持され、高密
度・高集積ＧａＡ ｓ Ｉ Ｃのアイソレーション化は
はゾ完全に達成されるという効果がある。As explained above, in the present invention, by double ion implantation of protons and boron, the ion implanted region becomes completely amorphous compared to the case of only protons, and annealing at low temperature is almost impossible. The ion implantation region remains highly resistive and therefore suffers from thermal effects during later stages of IC manufacturing, such as during alloying or assembly processes.
The high-resistance layer is maintained even by heat treatment before and after "C", and the effect is that isolation of the high-density, highly integrated GaAs IC is completely achieved.
第１図は本発明の第１の実施例の化合物半導体装置の製
法を示す断面図、第２図は本発明の第２の実施例の化合
物半導体装置の製法を示す断面図、第３図は従来の半導
体装置を示す断面図である。
１−ＧａＡｓ基板、２ 、４−・・ソース領域、３，５
・・・ドレイン領域、６．７・・・活性層領域、８，９
・・・ゲート金属、１０，１１．１２・・・高抵抗イオ
ン注入領域、１３・・・エピタキシャル層。FIG. 1 is a cross-sectional view showing a method for manufacturing a compound semiconductor device according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view showing a method for manufacturing a compound semiconductor device according to a second example of the present invention, and FIG. FIG. 2 is a cross-sectional view showing a conventional semiconductor device. 1-GaAs substrate, 2, 4--source region, 3, 5
...Drain region, 6.7...Active layer region, 8,9
. . . Gate metal, 10, 11. 12 . . . High resistance ion implantation region, 13 . . Epitaxial layer.
Claims (1)
半導体装置の製法において、各素子間を隔てるように、
プロトン及びボロンを同一領域にイオン注入する工程を
有することを特徴とする化合物半導体装置の製法。In the manufacturing method of a compound semiconductor device using gallium arsenide MES/FET as the basic element, in order to separate each element,
1. A method for manufacturing a compound semiconductor device, comprising a step of ion-implanting protons and boron into the same region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14658187A JPS63308934A (en) | 1987-06-11 | 1987-06-11 | Manufacture of compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14658187A JPS63308934A (en) | 1987-06-11 | 1987-06-11 | Manufacture of compound semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63308934A true JPS63308934A (en) | 1988-12-16 |
Family
ID=15410936
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14658187A Pending JPS63308934A (en) | 1987-06-11 | 1987-06-11 | Manufacture of compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63308934A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5166768A (en) * | 1989-12-25 | 1992-11-24 | Mitsubishi Denki Kabushiki Kaisha | Compound semiconductor integrated circuit device with an element isolating region |
| KR100338936B1 (en) * | 1999-11-09 | 2002-05-31 | 박종섭 | Method for forming isolation region of semiconductor device |
-
1987
- 1987-06-11 JP JP14658187A patent/JPS63308934A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5166768A (en) * | 1989-12-25 | 1992-11-24 | Mitsubishi Denki Kabushiki Kaisha | Compound semiconductor integrated circuit device with an element isolating region |
| KR100338936B1 (en) * | 1999-11-09 | 2002-05-31 | 박종섭 | Method for forming isolation region of semiconductor device |
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