KR100338936B1 - Method for forming isolation region of semiconductor device - Google Patents
Method for forming isolation region of semiconductor device Download PDFInfo
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- KR100338936B1 KR100338936B1 KR1019990049439A KR19990049439A KR100338936B1 KR 100338936 B1 KR100338936 B1 KR 100338936B1 KR 1019990049439 A KR1019990049439 A KR 1019990049439A KR 19990049439 A KR19990049439 A KR 19990049439A KR 100338936 B1 KR100338936 B1 KR 100338936B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000002955 isolation Methods 0.000 title abstract description 22
- 150000004767 nitrides Chemical class 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 230000003647 oxidation Effects 0.000 claims abstract description 4
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 230000010354 integration Effects 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 238000006731 degradation reaction Methods 0.000 abstract description 2
- 230000000694 effects Effects 0.000 abstract description 2
- 238000005498 polishing Methods 0.000 abstract description 2
- 210000004185 liver Anatomy 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
본 발명은 반도체소자의 격리영역 형성방법에 관한 것으로, 종래에는 반도체소자의 고집적화가 진행됨에 따라 STI의 폭을 줄여야 하고, 폭이 줄어든 STI를 채우기 위해서는 깊이도 줄여야 하는데, STI의 깊이를 줄일경우 소자간의 격리특성이 저하되는 문제점이 있었다. 따라서, 본 발명은 반도체기판 상에 제1산화막과 질화막을 순차적으로 형성한 다음 STI 패터닝을 실시하여 트렌치를 형성하는 공정과; 상기 트렌치가 형성된 결과물 상에 양자(proton)를 주입하는 공정과; 상기 양자가 주입된 결과물 상에 산화공정을 통해 제2산화막을 형성한 다음 고밀도 플라즈마 산화막을 증착하여 트렌치를 채우는 공정과; 상기 질화막이 노출될때까지 고밀도 플라즈마 산화막을 연마하여 평탄화한 다음 노출된 질화막 및 제1산화막을 제거하는 공정으로 이루어지는 반도체소자의 격리영역 형성방법을 통해 트렌치 영역 하부 반도체기판 내에 양자를 주입함으로써, 양자가 주입된 영역의 저항값을 증가시켜 소자의 고집적화로 인해 트렌치의 깊이가 얇아짐에 따른 소자간의 격리특성 저하를 억제할 수 있는 효과가 있다.The present invention relates to a method for forming an isolation region of a semiconductor device, and in the related art, as the integration of semiconductor devices increases, the width of the STI needs to be reduced, and the depth of the STI must be reduced to fill the reduced STI. There was a problem that the isolation properties of the liver are lowered. Accordingly, the present invention includes forming a trench by sequentially forming a first oxide film and a nitride film on a semiconductor substrate and then performing STI patterning; Injecting protons into the trenched product; Forming a second oxide film on the resultant implanted product through an oxidation process and then depositing a high density plasma oxide film to fill a trench; By injecting protons into the semiconductor substrate under the trench region through a method of forming an isolation region of a semiconductor device, the process includes: polishing and planarizing a high density plasma oxide film until the nitride film is exposed, and then removing the exposed nitride film and the first oxide film. Increasing the resistance value of the implanted region has the effect of suppressing the degradation of isolation characteristics between devices due to the thinning of the trench due to the high integration of the device.
Description
본 발명은 반도체소자의 격리영역 형성방법에 관한 것으로, 특히 얕은 트렌치 격리(shallow trench isolation : 이하, STI) 구조로 형성되는 고집적 디램(DRAM) 격리영역의 격리특성을 향상시키기에 적당하도록 한 반도체소자의 격리영역 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an isolation region of a semiconductor device, and more particularly, to a semiconductor device suitable for improving isolation characteristics of a highly integrated DRAM isolation region formed of a shallow trench isolation (STI) structure. It relates to a method for forming an isolation region of the.
종래 반도체소자의 격리영역 형성방법을 첨부한 도1a 내지 도1d의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A detailed cross-sectional view of FIGS. 1A to 1D attached to a method of forming an isolation region of a conventional semiconductor device will be described in detail as follows.
먼저, 도1a에 도시한 바와같이 반도체기판(1) 상부에 산화막(2)과 질화막(3)을 순차적으로 형성한다.First, as shown in FIG. 1A, an oxide film 2 and a nitride film 3 are sequentially formed on the semiconductor substrate 1.
그리고, 도1b에 도시한 바와같이 상기 질화막(3) 상에 STI를 위한 마스크(미도시)를 형성하고, 이를 적용하여 질화막(3)과 산화막(2)을 식각한 다음 마스크를 제거하고, 잔류하는 질화막(3) 및 산화막(2)을 마스크로 적용하여 반도체기판(1)을 소정의 깊이로 식각함으로써, 트렌치(4)를 형성한다. 이때, 트렌치(4)의 벽면은 일정한 기울기를 갖도록 하여 후속 고밀도 플라즈마 산화막(high density plasma : HDP, 6)을 채우기 용이하도록 한다.As shown in FIG. 1B, a mask (not shown) for STI is formed on the nitride film 3, the nitride film 3 and the oxide film 2 are etched by applying the mask, and then the mask is removed, and the remaining mask is removed. The trench 4 is formed by etching the semiconductor substrate 1 to a predetermined depth by applying the nitride film 3 and the oxide film 2 as a mask. At this time, the wall surface of the trench 4 has a constant slope so as to easily fill the subsequent high density plasma (HDP) 6.
그리고, 도1c에 도시한 바와같이 상기 트렌치(4)가 형성된 구조물 상에 산화공정을 실시하여 반도체기판(1) 표면상에 산화막(5)을 형성한 다음 상부전면에 고밀도 플라즈마 산화막(6)을 증착하여 트렌치(4)를 채운다.As shown in FIG. 1C, an oxidation process is performed on the structure on which the trench 4 is formed to form an oxide film 5 on the surface of the semiconductor substrate 1, and then a high density plasma oxide film 6 is formed on the upper surface of the semiconductor substrate 1. Deposition fills the trench 4.
그리고, 도1d에 도시한 바와같이 상기 질화막(3)이 노출될때까지 고밀도 플라즈마 산화막(6)을 화학기계적 연마(chemical mechanical polishing : CMP)하여 평탄화한 다음 노출된 질화막(3)을 제거하고, 계속해서 산화막(2)을 제거한다.Then, as shown in FIG. 1D, the high density plasma oxide film 6 is planarized by chemical mechanical polishing (CMP) until the nitride film 3 is exposed, and then the exposed nitride film 3 is removed, and then continued. The oxide film 2 is removed.
그러나, 상기한 바와같은 종래 반도체소자의 격리영역 형성방법은 반도체소자의 고집적화가 진행됨에 따라 STI의 폭을 줄여야 하고, 폭이 줄어든 STI를 채우기 위해서는 깊이도 줄여야 하는데, STI의 깊이를 줄일경우 소자간의 격리특성이 저하되는 문제점이 있었다.However, in the method of forming the isolation region of the conventional semiconductor device as described above, the width of the STI needs to be reduced as the integration of the semiconductor device increases, and the depth of the STI must be reduced to fill the reduced STI. There was a problem that the isolation characteristics are degraded.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 STI 구조로 형성되는 고집적 디램 격리영역의 격리특성을 향상시킬 수 있는 반도체소자의 격리영역 형성방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method for forming an isolation region of a semiconductor device capable of improving the isolation characteristic of a highly integrated DRAM isolation region formed of an STI structure. have.
도1a 내지 도1d는 종래 반도체소자의 격리영역 형성방법을 보인 수순단면도.1A to 1D are cross-sectional views showing a method of forming an isolation region of a conventional semiconductor device.
도2a 내지 도2d는 본 발명의 일 실시예를 보인 수순단면도.2A to 2D are cross-sectional views showing an embodiment of the present invention.
도3은 반도체기판의 도핑농도 및 양자의 농도에 따른 저항값의 증가를 보인 그래프도.3 is a graph showing an increase in the resistance value according to the doping concentration and the concentration of both of the semiconductor substrate.
***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***
11:반도체기판 12,15:산화막11: Semiconductor substrate 12, 15: oxide film
13:질화막 14:트렌치13: Nitride 14: trench
16:고밀도 플라즈마 산화막16: high density plasma oxide film
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자의 격리영역 형성방법은 반도체기판 상에 제1산화막과 질화막을 순차적으로 형성한 다음 STI 패터닝을 실시하여 트렌치를 형성하는 공정과; 상기 트렌치가 형성된 결과물 상에 양자(proton)를 주입하는 공정과; 상기 양자가 주입된 결과물 상에 산화공정을 통해 제2산화막을 형성한 다음 고밀도 플라즈마 산화막을 증착하여 상기 트렌치를 채우는 공정과; 상기 질화막이 노출될때까지 상기 고밀도 플라즈마 산화막을 연마하여 평탄화한 다음 노출된 질화막 및 제1산화막을 제거하는 공정을 포함하여 이루어진다.The method for forming an isolation region of a semiconductor device as described above includes forming a trench by sequentially forming a first oxide film and a nitride film on a semiconductor substrate and then performing STI patterning; Injecting protons into the trenched product; Forming a second oxide film through an oxidation process on the resultant implanted product and then depositing a high density plasma oxide film to fill the trenches; And grinding the planarized high density plasma oxide film until the nitride film is exposed, and then removing the exposed nitride film and the first oxide film.
상기한 바와같은 본 발명에 의한 반도체소자의 격리영역 형성방법을 첨부한도2a 내지 도2d의 수순단면도를 일 실시예로 하여 상세히 설명하면 다음과 같다.The procedure of cross-sectional view of FIGS. 2A to 2D with the method of forming the isolation region of the semiconductor device according to the present invention as described above will be described in detail as follows.
먼저, 도2a에 도시한 바와같이 반도체기판(11)의 상부에 산화막(12)과 질화막(13)을 순차적으로 형성한다.First, as shown in FIG. 2A, an oxide film 12 and a nitride film 13 are sequentially formed on the semiconductor substrate 11.
그리고, 도2b에 도시한 바와같이 상기 질화막(13) 상에 STI를 위한 마스크(미도시)를 형성하고, 이를 적용하여 질화막(13)과 산화막(12)을 식각한 다음 마스크를 제거하고, 잔류하는 질화막(13) 및 산화막(12)을 마스크로 적용하여 반도체기판(11)을 소정의 깊이로 식각함으로써, 트렌치(14)를 형성한 다음 그 결과물 상에 양자(proton)를 주입한다. 이때, 소자의 고집적화에 따라 트렌치(14)의 폭이 0.1㎛까지 줄어들 경우에 깊이는 2500Å 이하로 제한되고, 이 경우에 양자를 5∼30KeV의 에너지 및 10×1014∼10×1016proton/㎤의 도핑농도로 주입하여 상기 반도체기판(11) 내에서 산란층(scattering layer)으로 작용하도록 함으로써, 반도체기판(11) 내에 양자가 주입된 영역의 저항값을 증가시켜 트렌치(14)의 깊이가 얇아짐에 따른 소자간의 격리특성 저하를 억제할 수 있게 된다.As shown in FIG. 2B, a mask (not shown) for STI is formed on the nitride film 13, the nitride film 13 and the oxide film 12 are etched by applying the mask, and then the mask is removed and the remaining film is removed. By etching the semiconductor substrate 11 to a predetermined depth by applying the nitride film 13 and the oxide film 12 as a mask, a trench 14 is formed, and then protons are implanted on the resultant. At this time, when the width of the trench 14 is reduced to 0.1 μm according to the high integration of the device, the depth is limited to 2500 mW or less, and in this case, both the energy of 5 to 30 KeV and the 10 × 10 14 to 10 × 10 16 proton / By implanting at a doping concentration of cm 3 to act as a scattering layer in the semiconductor substrate 11, the depth of the trench 14 is increased by increasing the resistance value of the region in which both are implanted in the semiconductor substrate 11. It is possible to suppress the deterioration of the isolation characteristics between devices due to thinning.
그리고, 도2c에 도시한 바와같이 상기 양자가 주입된 결과물 상에 산화공정을 실시하여 반도체기판(11) 표면상에 산화막(15)을 형성한 다음 상부전면에 고밀도 플라즈마 산화막(16)을 증착하여 트렌치(14)를 채운다.As shown in FIG. 2C, an oxide process is performed on the resultant in which the protons are injected to form an oxide film 15 on the surface of the semiconductor substrate 11, and then a high density plasma oxide film 16 is deposited on the upper surface of the semiconductor substrate 11. Fill the trench 14.
그리고, 도2d에 도시한 바와같이 상기 질화막(13)이 노출될때까지 고밀도 플라즈마 산화막(16)을 화학기계적 연마하여 평탄화한 다음 노출된 질화막(13)을 제거하고, 계속해서 산화막(12)을 제거한다.2D, the high-density plasma oxide film 16 is chemically polished and planarized until the nitride film 13 is exposed, and then the exposed nitride film 13 is removed, and the oxide film 12 is subsequently removed. do.
한편, 도3은 상기 반도체기판(11)의 도핑농도 및 양자의 농도에 따른 저항값의 증가를 보인 그래프도로써, 양자의 농도가 1013proton/㎤ 이상이 될 경우에 반도체기판(11)의 저항값이 증가하는 것을 알 수 있다.3 is a graph showing an increase in resistance value according to the doping concentration and the concentration of both of the semiconductor substrates 11, and when the concentrations of the semiconductor substrates 11 are 10 13 proton / cm 3 or more, It can be seen that the resistance value increases.
상기한 바와같은 본 발명에 의한 반도체소자의 격리영역 형성방법은 트렌치 영역 하부 반도체기판 내에 양자를 주입함으로써, 양자가 주입된 영역의 저항값을 증가시켜 소자의 고집적화로 인해 트렌치의 깊이가 얇아짐에 따른 소자간의 격리특성 저하를 억제할 수 있는 효과가 있다.In the method of forming an isolation region of a semiconductor device according to the present invention as described above, by implanting quantum into the semiconductor substrate under the trench region, the depth of the trench is thinned due to the high integration of the device by increasing the resistance of the implanted region. There is an effect that can suppress the degradation of isolation characteristics between devices.
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| KR20010045919A KR20010045919A (en) | 2001-06-05 |
| KR100338936B1 true KR100338936B1 (en) | 2002-05-31 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990049439A KR100338936B1 (en) | 1999-11-09 | 1999-11-09 | Method for forming isolation region of semiconductor device |
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| Country | Link |
|---|---|
| KR (1) | KR100338936B1 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63308934A (en) * | 1987-06-11 | 1988-12-16 | Nec Corp | Manufacture of compound semiconductor device |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63308934A (en) * | 1987-06-11 | 1988-12-16 | Nec Corp | Manufacture of compound semiconductor device |
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| Publication number | Publication date |
|---|---|
| KR20010045919A (en) | 2001-06-05 |
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