KR20030050199A - Method of forming a isolation layer in a semiconductor device - Google Patents
Method of forming a isolation layer in a semiconductor device Download PDFInfo
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- KR20030050199A KR20030050199A KR1020010080599A KR20010080599A KR20030050199A KR 20030050199 A KR20030050199 A KR 20030050199A KR 1020010080599 A KR1020010080599 A KR 1020010080599A KR 20010080599 A KR20010080599 A KR 20010080599A KR 20030050199 A KR20030050199 A KR 20030050199A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 36
- 238000002955 isolation Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 150000004767 nitrides Chemical class 0.000 claims abstract description 27
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 18
- -1 nitrogen ions Chemical class 0.000 claims abstract description 16
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 239000011810 insulating material Substances 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 5
- 230000000903 blocking effect Effects 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 5
- 239000012774 insulation material Substances 0.000 abstract 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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Abstract
Description
본 발명은 반도체 소자의 소자 분리막 형성 방법에 관한 것으로, 특히 소자분리막의 상부 가장자리에서 게이트 산화막이 얇게 형성되는 것을 방지하여 험프 특성이 발생되는 것을 억제할 수 있는 반도체 소자의 소자 분리막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a device isolation film of a semiconductor device, and more particularly, to a method of forming a device isolation film for a semiconductor device capable of preventing formation of a hump characteristic by preventing a thin gate oxide film from being formed at the upper edge of the device isolation film. .
모든 반도체 소자에서는 각종 소자를 전기적으로 분리하기 위하여 소자 분리막을 형성한다. 종래에는 소자 분리막을 열산화 공정으로 형성하였으나, 이러한 경우 소자 분리막의 가장 자리에서 버즈 빅이 발생되어 소자의 전기적 특성 및 집적도를 저하시키는 문제점이 발생된다.In all semiconductor devices, device isolation layers are formed to electrically separate various devices. Conventionally, the device isolation layer is formed by a thermal oxidation process, but in this case, a buzz big is generated at the edge of the device isolation layer, thereby deteriorating the electrical characteristics and the integration degree of the device.
반도체 소자가 고집적화 되어감에 따라, 소자 분리막에 버즈 빅이 발생되는 것을 방지하면서 소자 분리막이 차지하는 면적을 최소화할 수 있도록 소자 분리막을 STI(Shallow Trench Isolation) 구조로 형성한다. 그러나, 소자 분리막을 STI 구조로 형성할 경우 소자 분리막의 상부 가장 자리가 식각되어 모우트가 발생된다. 또한, 트렌치의 상부 가장 자리가 각진 형태로 형성되므로, 이 부분에 게이트 산화막이 형성될 경우 각진 모서리 부분에서 게이트 산화막이 매우 얇게 형성되어 험프(Hump) 특성이 나타난다.As semiconductor devices become highly integrated, a device isolation layer is formed in a shallow trench isolation (STI) structure to minimize the area occupied by the device isolation layer while preventing buzz big from occurring in the device isolation layer. However, when the device isolation layer is formed in the STI structure, the upper edge of the device isolation layer is etched to generate a moat. In addition, since the upper edge of the trench is formed in an angular shape, when the gate oxide film is formed in this portion, the gate oxide film is formed very thin in the angular corner portion to exhibit the Hump characteristic.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 트렌치를 절연물질층으로 매립한 후 식각 공정을 통해 트렌치의 소정 깊이까지 절연물질층을 제거하면서 반도체 기판의 모서리를 둥근 형태로 만들어 전계가 집중되는 것을 방지하고, 노출된 반도체 기판의 모서리 부분에는 질소이온을 주입하여 모서리 부분에서 게이트 산화막이 얇게 형성되더라도 누설 전류가 발생되는 것을 방지함으로써, 소자의 전기적 특성을 향상시킬 수 있는 반도체 소자의 소자 분리막 형성 방법을 제공하는데 그 목적이 있다.Accordingly, in order to solve the above problem, the present invention concentrates an electric field by filling a corner of a semiconductor substrate with a round shape while removing the insulating material layer to a predetermined depth through an etching process after filling the trench with an insulating material layer. And implanting nitrogen ions into the exposed edges of the semiconductor substrate to prevent leakage current from being generated even when the gate oxide film is thinly formed at the edges, thereby improving the electrical characteristics of the device. The purpose is to provide.
도 1a 내지 도 1j는 본 발명에 따른 반도체 소자의 소자 분리막 형성 방법을 설명하기 위한 소자의 단면도.1A to 1J are cross-sectional views of a device for explaining a device isolation film forming method of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11 : 반도체 기판11a : 트렌치11 semiconductor substrate 11a trench
12 : 패드 산화막13 : 패드 질화막12 pad oxide film 13 pad nitride film
13a: 개구부14 : 열산화막13a: opening 14: thermal oxide film
15 : 제 1 절연물질층16 : 질소이온주입층15: first insulating material layer 16: nitrogen ion injection layer
17 : 제 2 절연물질층100 : 소자 분리막17: second insulating material layer 100: device isolation film
본 발명에 따른 반도체 소자의 소자 분리막 형성 방법은 패드 산화막 및 패드 질화막을 형성하고 패터닝 공정으로 트렌치 영역을 정의한 후 트렌치 영역 가장 자리의 패드 질화막을 식각하여 트렌치 영역보다 큰 개구부를 형성하는 단계와, 반도체 기판에 트렌치를 형성하는 단계와, 트렌치를 제 1 절연물질층으로 매립하는 단계와, 개구부를 통해 노출된 패드 산화막 및 제 1 절연물질층을 습식 식각 공정으로 트렌치의 소정 깊이까지 제거하면서 반도체 기판의 상부 모서리 부분을 둥글게 만드는 단계와, 트렌치 상부에 제 2 절연물질층을 형성하는 단계와, 패드 질화막 및 패드 산화막을 제거하는 단계로 이루어지는 것을 특징으로 한다.A method of forming a device isolation layer of a semiconductor device according to the present invention includes forming a pad oxide layer and a pad nitride layer, defining a trench region by a patterning process, and etching the pad nitride layer at the edge of the trench region to form an opening larger than the trench region, and Forming a trench in the substrate, filling the trench with the first insulating material layer, and removing the pad oxide film and the first insulating material layer exposed through the opening to a predetermined depth of the trench by a wet etching process. Rounding the upper edge portion, forming a second insulating material layer on the trench, and removing the pad nitride film and the pad oxide film.
상기에서, 트렌치를 형성한 후에 트렌치의 측벽 및 저면에 열산화막을 형성하여 트렌치의 하부 모서리를 둥글게 형성할 수도 있다.In the above, after forming the trench, a thermal oxide film may be formed on the sidewalls and the bottom of the trench to round the bottom edge of the trench.
또한, 습식 식각 공정을 실시한 후에 노출된 반도체 기판의 상부 모서리에 질소이온을 주입하여 반도체 기판의 상부 모서리에서 누설 전류가 발생되는 것을 방지할 수도 있다. 이때, 이온 주입 공정은 패드 질화막의 두께에 따라 질소이온의 주입각을 조절하여 패드 질화막을 이온 주입 차단층으로 이용함으로써, 반도체 기판의 상부 모서리에만 질소이온이 주입되고 제 1 절연물질층에는 질소이온이 주입되지 않도록 한다.In addition, after performing the wet etching process, nitrogen ions may be injected into the exposed upper edges of the semiconductor substrate to prevent leakage current from occurring at the upper edges of the semiconductor substrates. In this case, the ion implantation process uses a pad nitride layer as an ion implantation blocking layer by adjusting the implantation angle of nitrogen ions according to the thickness of the pad nitride layer, whereby nitrogen ion is implanted only at the upper edge of the semiconductor substrate and nitrogen ion is injected into the first insulating material layer. Do not inject this.
이후의 제 2 절연물질층은 패드 산화막의 높이까지 형성되며, 제 1 및 제 2 절연물질층은 고밀도 플라즈마 산화막으로 형성된다.Subsequently, the second insulating material layer is formed to the height of the pad oxide film, and the first and second insulating material layers are formed of the high density plasma oxide film.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 보다 더 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.
도 1a 내지 도 1j는 본 발명에 따른 반도체 소자의 소자 분리막 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1J are cross-sectional views of devices for describing a method of forming a device isolation film of a semiconductor device according to the present invention.
도 1a를 참조하면, 반도체 기판(11) 상에 패드 산화막(12) 및 패드 질화막(13)을 순차적으로 형성한다. 패드 산화막(12) 및 패드 질화막(13)은 후속 공정에서 반도체 기판(11)에 트렌치를 형성하기 위한 식각 공정 시 STI 하드 마스크 역할을 한다.Referring to FIG. 1A, a pad oxide film 12 and a pad nitride film 13 are sequentially formed on a semiconductor substrate 11. The pad oxide layer 12 and the pad nitride layer 13 serve as an STI hard mask during an etching process for forming a trench in the semiconductor substrate 11 in a subsequent process.
도 1b를 참조하면, 트렌치 마스크를 이용한 식각 공정으로 패드 질화막(13) 및 패드 산화막(12)을 제거하여 트렌치가 형성될 영역의 반도체 기판(11)을 노출시킨다.Referring to FIG. 1B, the pad nitride layer 13 and the pad oxide layer 12 are removed by an etching process using a trench mask to expose the semiconductor substrate 11 in the region where the trench is to be formed.
도 1c를 참조하면, 트렌치가 형성될 영역의 주변에 형성된 패드 질화막(13)을 제거한다. 이때, 패드 산화막(12)은 패드 질화막(13)과의 식각 선택비에 의하여 식각되지 않고 그대로 잔류된다. 이로써, 패드 질화막(13)에 형성된 개구부(13a)는 트렌치가 형성될 영역보다 넓게 형성된다.Referring to FIG. 1C, the pad nitride film 13 formed around the region where the trench is to be formed is removed. At this time, the pad oxide film 12 is not etched by the etching selectivity with the pad nitride film 13 and remains as it is. As a result, the opening 13a formed in the pad nitride film 13 is formed wider than the region where the trench is to be formed.
도 1d를 참조하면, 식각 공정을 통해 반도체 기판(11)의 노출된 영역을 소정 깊이까지 식각하여 트렌치(11a)를 형성한다.Referring to FIG. 1D, the trench 11a is formed by etching the exposed region of the semiconductor substrate 11 to a predetermined depth through an etching process.
도 1e를 참조하면, 트렌치(11a)의 각진 하부 모서리를 둥근 형태로 만들기 위한 라운딩 공정으로, 트렌치(11a)의 측벽 및 저면에 노출된 반도체 기판(11)의 표면에 열산화막(14)을 형성한다. 열산화막(14)은 반도체 기판(11)의 표면을 산화시키면서 형성되기 때문에, 트렌치(11a)의 각진 하부 모서리가 둥근 형태로 변한다. 이로써, 트렌치(11a)의 하부 모서리에 전계가 집중되는 것을 방지하여 소자의 전기적 특성을 향상시킬 수 있다.Referring to FIG. 1E, a thermal oxide film 14 is formed on the surface of the semiconductor substrate 11 exposed to the sidewalls and the bottom of the trench 11a in a rounding process for rounding the lower angled corners of the trench 11a. do. Since the thermal oxide film 14 is formed while oxidizing the surface of the semiconductor substrate 11, the angular lower edge of the trench 11a changes to a round shape. As a result, the electric field of the device may be prevented from being concentrated at the lower edge of the trench 11a.
도 1f를 참조하면, 전체 상부에 제 1 절연물질층을 형성한 후 화학적 기계적 연마 공정으로 패드 질화막(13) 상부의 제 1 절연물질층을 제거하여 트렌치(11a)에만 제 1 절연물질층(15)을 잔류시킨다. 이때, 패드 질화막(13) 상부의 제 1 절연물질층을 완전히 제거하기 위하여 화학적 기계적 연마를 과도하게 실시한다. 이로 인하여, 패드 질화막(13)의 상부도 일부 연마되어 두께가 얇아진다.Referring to FIG. 1F, after forming the first insulating material layer over the entire surface, the first insulating material layer 15 is removed from the trench 11a only by removing the first insulating material layer on the pad nitride layer 13 by a chemical mechanical polishing process. ) Is left. At this time, in order to completely remove the first insulating material layer on the pad nitride film 13, chemical mechanical polishing is excessively performed. For this reason, the upper part of the pad nitride film 13 is also partially polished, and the thickness becomes thin.
상기에서 제 1 절연물질층(15)은 고밀도 플라즈마(High Density Plasma; HDP) 산화막으로 형성한다.The first insulating material layer 15 is formed of a high density plasma (HDP) oxide film.
도 1g를 참조하면, HF 용액을 이용한 습식 식각 공정을 실시하여 반도체 기판(11)의 소정 깊이까지 제 1 절연물질층(15)을 제거한다.Referring to FIG. 1G, a wet etching process using an HF solution is performed to remove the first insulating material layer 15 to a predetermined depth of the semiconductor substrate 11.
HF 용액은 반도체 기판(11)에 비하여 산화막을 더 많이 식각하므로, 습식 식각 시 HF 용액을 이용할 경우, 질화막(13)의 개구부(13a)를 통해 노출된 패드 산화막(12) 및 제 1 절연물질층(15)이 식각되면서 노출되는 반도체 기판(11)은 산화막에 비하여 조금만 식각된다. 이로 인하여, 트렌치(11a)의 상부 모서리에서 반도체 기판(11)이 둥근 형태로 형성된다. 이로써, 트렌치(11a) 상부 모서리의 반도체 기판(11)에 전계가 집중되는 것을 방지하여 소자의 전기적 특성을 향상시킬 수 있다.Since the HF solution etches the oxide film more than the semiconductor substrate 11, when the HF solution is used during wet etching, the pad oxide film 12 and the first insulating material layer exposed through the opening 13a of the nitride film 13 are exposed. The semiconductor substrate 11 exposed by etching 15 is slightly etched compared to the oxide film. For this reason, the semiconductor substrate 11 is formed in a round shape at the upper edge of the trench 11a. As a result, an electric field may be prevented from being concentrated on the semiconductor substrate 11 at the upper edge of the trench 11a, thereby improving electrical characteristics of the device.
도 1h를 참조하면, 트렌치(11a)의 상부 모서리에 노출된 반도체 기판(11)에 소정의 주입각으로 질소 이온을 주입하여 질소이온 주입층(16)을 형성한다.Referring to FIG. 1H, a nitrogen ion implantation layer 16 is formed by implanting nitrogen ions at a predetermined implantation angle into the semiconductor substrate 11 exposed at the upper edge of the trench 11a.
이때, 주입각은 잔류하는 패드 질화막(13)의 두께에 따라 조절하여 패드 질화막(13)을 이온 주입 차단층으로 이용함으로써, 열산화막(14)이나 제 1 절연물질층(15)에는 질소이온이 주입되지 않도록 한다.At this time, the implantation angle is adjusted according to the thickness of the remaining pad nitride film 13 to use the pad nitride film 13 as an ion implantation blocking layer, whereby nitrogen oxide is added to the thermal oxide film 14 or the first insulating material layer 15. Do not inject.
또한, 노출된 반도체 기판(11)에 질소이온을 골고루 주입하기 위하여, 질소 이온의 주입각을 유지한 상태에서 360°회전하면서 질소이온 주입 공정을 실시한다.In addition, in order to uniformly inject nitrogen ions into the exposed semiconductor substrate 11, a nitrogen ion implantation process is performed while rotating 360 ° while maintaining an implantation angle of nitrogen ions.
상기의 공정을 통해 형성된 질소이온 주입층(16)은 게이트 산화막이 반도체 기판(11)의 상부 모서리에서 얇게 형성될 경우 누설 전류가 발생되는 것을 방지하여 소자의 전기적 특성이 저하되는 것을 방지한다.The nitrogen ion implanted layer 16 formed through the above process prevents leakage current from occurring when the gate oxide film is thinly formed at the upper edge of the semiconductor substrate 11 to prevent deterioration of electrical characteristics of the device.
도 1i를 참조하면, 습식 식각 공정에 의해 제거된 제 1 절연물질층의 두께를 보상하기 위하여 트렌치(11a) 상부에 패드 산화막(12)의 높이까지 제 2 절연물질층(17)을 형성한다.Referring to FIG. 1I, in order to compensate for the thickness of the first insulating material layer removed by the wet etching process, the second insulating material layer 17 is formed on the trench 11a to the height of the pad oxide layer 12.
도 1j를 참조하면, 반도체 기판(11) 상부의 패드 산화막(12) 및 패드 질화막(13)을 제거한다. 이로써, 열산화막(14), 제 1 절연물질층(15) 및 제 2 절연물질층(17)으로 이루어진 소자 분리막(100)이 형성된다.Referring to FIG. 1J, the pad oxide film 12 and the pad nitride film 13 on the semiconductor substrate 11 are removed. As a result, the device isolation layer 100 including the thermal oxide film 14, the first insulating material layer 15, and the second insulating material layer 17 is formed.
상술한 바와 같이, 본 발명은 라운딩 공정을 통해 트렌치의 각진 모서리 부분을 둥근 형태로 만들어 전계가 집중되는 것을 방지하고, 소자 분리막과 접하는 반도체 기판의 상부 모서리 부분에는 질소이온을 주입하여 모서리 부분에서 누설 전류가 발생되는 것을 방지함으로써, 소자의 전기적 특성을 향상시킨다.As described above, the present invention prevents the electric field from being concentrated by rounding the angular corner portions of the trench through the rounding process, and injecting nitrogen ions into the upper corner portions of the semiconductor substrate in contact with the device isolation layer to leak from the corner portions. By preventing current from being generated, the electrical characteristics of the device are improved.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100567877B1 (en) * | 2003-12-31 | 2006-04-04 | 동부아남반도체 주식회사 | Method for forming the shallow trench isolation of the semiconductor device |
| CN104425345A (en) * | 2013-09-09 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Formation method for shallow trench isolation structure |
| WO2019007347A1 (en) * | 2017-07-03 | 2019-01-10 | 无锡华润上华科技有限公司 | Trench isolation structure and manufacturing method therefor |
| CN117747535A (en) * | 2024-02-21 | 2024-03-22 | 合肥晶合集成电路股份有限公司 | Shallow trench isolation structure, semiconductor structure and preparation method |
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2001
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100567877B1 (en) * | 2003-12-31 | 2006-04-04 | 동부아남반도체 주식회사 | Method for forming the shallow trench isolation of the semiconductor device |
| CN104425345A (en) * | 2013-09-09 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Formation method for shallow trench isolation structure |
| WO2019007347A1 (en) * | 2017-07-03 | 2019-01-10 | 无锡华润上华科技有限公司 | Trench isolation structure and manufacturing method therefor |
| US11315824B2 (en) | 2017-07-03 | 2022-04-26 | Csmc Technologies Fab2 Co., Ltd. | Trench isolation structure and manufacturing method therefor |
| CN117747535A (en) * | 2024-02-21 | 2024-03-22 | 合肥晶合集成电路股份有限公司 | Shallow trench isolation structure, semiconductor structure and preparation method |
| CN117747535B (en) * | 2024-02-21 | 2024-05-28 | 合肥晶合集成电路股份有限公司 | Shallow trench isolation structure, semiconductor structure and preparation method |
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