KR20060075363A - Method of forming a gate electrode pattern in flash memory device - Google Patents
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- KR20060075363A KR20060075363A KR1020040114140A KR20040114140A KR20060075363A KR 20060075363 A KR20060075363 A KR 20060075363A KR 1020040114140 A KR1020040114140 A KR 1020040114140A KR 20040114140 A KR20040114140 A KR 20040114140A KR 20060075363 A KR20060075363 A KR 20060075363A
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000005468 ion implantation Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 230000003647 oxidation Effects 0.000 claims abstract description 7
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 230000007261 regionalization Effects 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 22
- 229920005591 polysilicon Polymers 0.000 abstract description 22
- 150000002500 ions Chemical class 0.000 abstract description 8
- 239000012528 membrane Substances 0.000 abstract 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 8
- 230000005684 electric field Effects 0.000 description 4
- -1 oxygen ions Chemical class 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
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Abstract
본 발명은 플래쉬 메모리소자의 게이트 전극 패턴 형성방법에 관한 것으로, 본 발명의 사상은 패터닝된 플로팅 게이트 전극용 실리콘막이 형성된 반도체 기판 상에 이온주입공정을 수행하여, 패터닝된 플로팅 게이트 전극 측벽에 이온주입영역을 형성하는 단계, 상기 결과물 전면에 산화공정을 수행하여, 상기 플로팅 게이트 전극용 폴리실리콘막의 경계를 따라 형성되되, 모서리 부분이 두껍게 라운딩된 산화막을 형성하는 단계 및 상기 결과물 상에 유전막을 형성하는 단계를 포함한다.
The present invention relates to a method of forming a gate electrode pattern of a flash memory device, and the idea of the present invention is to perform ion implantation on a semiconductor substrate on which a silicon film for a patterned floating gate electrode is formed, thereby implanting ions into the sidewall of the patterned floating gate electrode. Forming a region, and performing an oxidation process on the entire surface of the resultant to form an oxide film formed along a boundary of the polysilicon layer for the floating gate electrode and having a thick rounded corner; and forming a dielectric layer on the resultant. Steps.
ONO막ONO membrane
Description
도 1 내지 도 4는 본 발명에 따른 플래쉬 메모리소자의 게이트 전극 패턴 형성방법을 설명하기 위한 단면도들이다.
1 to 4 are cross-sectional views illustrating a method of forming a gate electrode pattern of a flash memory device according to the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10: 반도체 기판 12: 터널 산화막10
14: 제1 폴리 실리콘막 16: 제2 폴리 실리콘막14: first polysilicon film 16: second polysilicon film
18: 소자 분리막 20: SiO2가 이온주입된 영역18: device isolation layer 20: a region implanted with SiO 2
22: 산화막 24: ONO막
22: oxide film 24: ONO film
본 발명은 반도체 소자의 제조방법에 관한 것으로, 더욱 상세하게는 플래쉬 메모리소자의 게이트 전극 패턴 형성방법에 관한 것이다. The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a gate electrode pattern of a flash memory device.
최근 반도체 소자의 고집적화 고밀도화됨에 따라 플로팅 게이트 전극 패턴과 콘트롤 게이트 전극 패턴 사이에 형성되는 ONO막질의 두께또한 감소하게 된다. In recent years, as the integration density of semiconductor devices increases, the thickness of the ONO film formed between the floating gate electrode pattern and the control gate electrode pattern is also reduced.
상기 ONO막의 두께가 얇아지게 됨으로써 게이트 전극 패턴들간의 간섭효과가 증가되어 소자의 디스터브(disturb)를 증가시키게 되는 문제점이 있다. As the thickness of the ONO film becomes thinner, there is a problem in that interference effects between gate electrode patterns are increased to increase the disturbance of the device.
또한, 얇아진 ONO막으로 인해, 이후 형성될 콘트롤 게이트전극의 에지부분에서 강한 전계에 의해 발생되어 ONO막 측벽의 누설전류를 증가시키게 되는 문제점이 있다.
Further, due to the thinned ONO film, there is a problem in that it is generated by a strong electric field at the edge portion of the control gate electrode to be formed later, thereby increasing the leakage current of the sidewall of the ONO film.
상술한 문제점을 해결하기 위한 본 발명의 목적은 게이트 전극 패턴 간의 간섭효과를 감소시켜 소자의 디스터브를 감소시키고, ONO막 측벽의 누설전류를 감소시키게 하는 플래쉬 메모리소자의 게이트 전극 패턴 형성방법을 제공함에 있다.
SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming a gate electrode pattern of a flash memory device which reduces interference of the device by reducing interference between gate electrode patterns and reduces leakage current of the sidewall of the ONO film. have.
상술한 목적을 달성하기 위한 본 발명의 사상은 패터닝된 플로팅 게이트 전극용 실리콘막이 형성된 반도체 기판 상에 이온주입공정을 수행하여, 패터닝된 플로팅 게이트 전극 측벽에 이온주입영역을 형성하는 단계, 상기 결과물 전면에 산화공정을 수행하여, 상기 플로팅 게이트 전극용 폴리실리콘막의 경계를 따라 형성되되, 모서리 부분이 두껍게 라운딩된 산화막을 형성하는 단계 및 상기 결과물 상에 유전막을 형성하는 단계를 포함한다. The idea of the present invention for achieving the above object is to form an ion implantation region on the sidewall of the patterned floating gate electrode by performing an ion implantation process on the semiconductor substrate on which the silicon film for the patterned floating gate electrode is formed, the entire surface of the resultant And forming an oxide film formed along a boundary of the polysilicon film for the floating gate electrode and having a thick rounded corner, and forming a dielectric film on the resultant.
상기 이온주입영역은 산소이온이 주입된 상기 반도체 기판을 800℃의 온도인 챔버 내부로 주입한 후 챔버 내부를 900~ 1300℃의 온도로 유지하면서 산소 분위기하에 기판을 산화시킴으로써 형성하는 것이 바람직하다. The ion implantation region is preferably formed by injecting the semiconductor substrate into which oxygen ions are implanted into a chamber at a temperature of 800 ° C., and then oxidizing the substrate under an oxygen atmosphere while maintaining the chamber at a temperature of 900 to 1300 ° C.
상기 반도체 기판에 주입된 산소이온은 상기 플로팅 게이트 전극용 실리콘막 측벽 내부에 10~ 20Å 되도록 하기 위해, 10~ 50 KeV의 이온주입 에너지, 1.0~ 5.0E17의 도즈량을 갖는 공정조건에서 수행하는 이온주입공정을 통해 주입되는 것이 바람직하다. Oxygen ions implanted into the semiconductor substrate are ionized at a process condition having an ion implantation energy of 10 to 50 KeV and a dose amount of 1.0 to 5.0E17 so as to allow 10 to 20 kW inside the silicon film sidewall of the floating gate electrode. It is preferable to inject through the injection process.
상기 플로팅 게이트 전극용 실리콘막의 경계를 따라 형성되면서 동시에 모서리 부분이 두껍게 라운딩된 산화막은 20Å 정도의 두께를 가지도록 하는 것이 바람직하다.
It is preferable that the oxide film formed along the boundary of the floating gate electrode silicon film and at the same time the corner portion is thickly rounded has a thickness of about 20 GPa.
이하, 첨부 도면을 참조하여 본 발명의 실시 예를 상세히 설명한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있지만 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안 된다. 본 발명의 실시예들은 당업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해 제공되어지는 것이다. 또한 어떤 막이 다른 막 또는 반도체 기판의 '상'에 있다 또는 접촉하고 있다 라고 기재되는 경우에, 상기 어떤 막은 상기 다른 막 또는 반도체 기판에 직접 접촉하여 존재할 수 있고, 또는 그 사이에 제 3의 막이 개재되어질 수도 있다.
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, but the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. In addition, when a film is described as being on or in contact with another film or semiconductor substrate, the film may be in direct contact with the other film or semiconductor substrate, or a third film is interposed therebetween. It may be done.
도 1 내지 도 4는 본 발명에 따른 플래쉬 메모리소자의 게이트 전극 패턴 형성방법을 설명하기 위한 단면도들이다. 1 to 4 are cross-sectional views illustrating a method of forming a gate electrode pattern of a flash memory device according to the present invention.
도 1을 참조하면, 반도체 기판(10)상에 터널산화막(12), 플로팅 게이트전극용 제1 폴리실리콘막(14) 및 패드 질화막(미도시)을 순차적으로 형성한다.Referring to FIG. 1, a
상기 결과물의 소정영역에 트렌치 형성용 포토레지스트 패턴(미도시)을 형성한 후 이를 식각마스크로 식각공정을 수행하여 트렌치(미도시)를 형성한다. 이 트렌치(미도시) 내부에 갭필(gap fill)특성이 우수한 HDP(HighDensity plasma)산화막과 같은 산화막이 채워지도록 증착한 후 화학적 기계적 연마(chemical mechanical polishing: CMP)공정 등의 평탄화 공정을 수행하여 소자 분리막(18)의 형성을 완료한다. 이어서, 상기 제1 폴리 실리콘막(14) 상에 형성된 패드 질화막(미도시)을 제거한다. After forming a photoresist pattern (not shown) for forming a trench in a predetermined region of the resultant, a trench (not shown) is formed by performing an etching process with an etching mask. The trench (not shown) is deposited to fill an oxide film such as a high density plasma (HDP) oxide film having excellent gap fill characteristics, and then a planarization process such as chemical mechanical polishing (CMP) process is performed. The formation of the
상기 소자 분리막(18)이 형성된 결과물 전면에 플로팅 게이트전극용 제2 폴리 실리콘막을 형성하고, 상기 제2 폴리 실리콘막의 소정영역을 식각하여 패터닝된 제2 폴리 실리콘막(16)을 형성한다. A second polysilicon film for floating gate electrodes is formed on the entire surface of the resultant device on which the
도 2를 참조하면, 상기 패터닝된 플로팅 게이트전극용 제2 폴리 실리콘막(16) 상부에 이온주입공정을 수행하여, SiO2이온이 주입된 영역(20)을 형성한다. Referring to FIG. 2, an ion implantation process is performed on the patterned
상기 이온주입공정은 SiO2 이온을 상기 제2 폴리 실리콘막의 측벽영역에 틸트되도록 주입함으로써 수행되는 데, 이로 인해 상기 제2 폴리 실리콘막의 측벽에 SiO2이온이 주입된 영역(20)이 형성된다. The ion implantation process is performed by implanting SiO 2 ions into the sidewall region of the second polysilicon film, thereby forming a
상기 SiO2이온이 주입된 영역(20)은 산소이온이 주입된 실리콘 기판을 800 ℃ 정도의 온도인 챔버 내부로 주입한 후 챔버 내부의 온도를 900~ 1300℃ 정도의 유지하면서 산소 분위기하에 기판을 산화시킴으로써 형성한다.The
상기 산소이온이 주입되는 이온주입공정은 상기 제2 폴리 실리콘막 측벽 내부에 10~ 20Å정도 되도록 하기 위해, 10~50 KeV 정도의 이온주입 에너지, 1.0~ 5.0E17 정도의 도즈량을 갖는 공정조건에서 수행한다. The ion implantation process in which the oxygen ions are implanted is performed under process conditions having an ion implantation energy of about 10 to 50 KeV and a dose amount of about 1.0 to 5.0E17 so as to be about 10 to about 20 kW into the sidewall of the second polysilicon film. Perform.
도 3을 참조하면, 상기 SiO2이온이 주입된 영역(20)이 구비된 결과물 전면에 산화공정을 수행하여 상기 플로팅 게이트 전극용 제2 폴리실리콘막(16)의 경계를 따라 형성되되, 모서리 부분이 두껍게 라운딩된 산화막(22)을 형성한다. Referring to FIG. 3, an oxidation process is performed on the entire surface of the resultant having the
상기 제2 폴리 실리콘막 및 모서리부분에 라운딩된 산화막의 두께는 20Å 정도이다. The thickness of the oxide film rounded to the second polysilicon film and the corner portion is about 20Å.
상기 제2 폴리 실리콘막에 형성된 산화막은 상기 제1 폴리 실리콘막의 내부에 형성된 SiO2이온이 주입된 영역과 결합되어야 한다. The oxide film formed on the second polysilicon film should be combined with a region implanted with SiO 2 ions formed in the first polysilicon film.
즉, 상기 모서리 부분이 두껍게 라운딩된 산화막(22)은, 상기 제2 폴리 실리콘막의 측벽에 형성된 상기 SiO2이온이 주입된 영역(20)에 산화공정이 수행됨으로써 형성되는 데, 이때, 상기 이온이 주입된 영역(20)과 인접하지 않은 영역에 산화공정이 수행되어 형성된 산화막보다 상기 이온이 주입된 영역(20)에 산화공정이 수행 되어 형성된 산화막이 더 두껍게 형성되도록 한다. That is, the
상기 모서리 부분이 두껍게 라운딩된 산화막을 형성함으로써, 게이트 전극들간의 간섭효과를 줄여 소자의 디스터브(disturb)를 감소시키게 된다. By forming an oxide film having a thick rounded corner, the interference between the gate electrodes is reduced to reduce the disturbance of the device.
또한, 상기 모서리 부분이 두껍게 라운딩된 산화막이 플로팅 게이트 전극용 제2 폴리 실리콘막 상에 형성됨으로써, 이후 형성될 콘트롤 게이트전극의 에지부분에서 강한 전계에 의해 발생되는 누설전류를 감소시키게 된다. In addition, an oxide film having a thick rounded corner portion is formed on the second polysilicon film for the floating gate electrode, thereby reducing leakage current generated by a strong electric field at the edge portion of the control gate electrode to be formed later.
도 4를 참조하면, 상기 결과물인 모서리 부분이 두껍게 라운딩된 산화막(22) 상부에 유전막인 ONO막(24)을 형성함으로써, 본 공정을 완료한다. Referring to FIG. 4, the process is completed by forming an
도면에는 도시되지 않았지만, 상기 결과물 상부에 콘트롤 게이트 전극용 제3 폴리실리콘막을 형성한 후 상기 막질들을 패터닝하여 플래쉬 메모리소자의 게이트 전극 패턴을 형성하게 된다. Although not shown in the drawing, a third polysilicon film for the control gate electrode is formed on the resultant, and then the films are patterned to form a gate electrode pattern of the flash memory device.
본 발명에 의하면, 상기 모서리 부분이 두껍게 라운딩된 산화막을 형성함으로써, 게이트 전극들간의 간섭효과를 줄여 소자의 디스터브(disturb)를 감소시키게 된다. According to the present invention, by forming an oxide film having a thick rounded corner, the interference between gate electrodes is reduced to reduce the disturbance of the device.
또한, 본 발명에 의하면, 상기 모서리 부분이 두껍게 라운딩된 산화막이 플로팅 게이트 전극용 제2 폴리 실리콘막 상에 형성됨으로써, 이후 형성될 콘트롤 게이트전극의 에지부분에서 강한 전계에 의해 발생되는 누설전류를 감소시키게 된다.
Further, according to the present invention, an oxide film having a thick rounded corner portion is formed on the second polysilicon film for the floating gate electrode, thereby reducing leakage current generated by a strong electric field at the edge portion of the control gate electrode to be formed later. Let's go.
이상에서 살펴본 바와 같이 본 발명에 의하면, 상기 모서리 부분이 두껍게 라운딩된 산화막을 형성함으로써, 게이트 전극들간의 간섭효과를 줄여 소자의 디스터브(disturb)를 감소시키게 되는 효과가 있다. As described above, according to the present invention, an oxide film having a thick rounded corner portion is formed, thereby reducing interference between gate electrodes and reducing disturbance of the device.
또한, 본 발명에 의하면, 상기 모서리 부분이 두껍게 라운딩된 산화막이 플로팅 게이트 전극용 제2 폴리 실리콘막 상에 형성됨으로써, 이후 형성될 콘트롤 게이트전극의 에지부분에서 강한 전계에 의해 발생되는 누설전류를 감소시키게 되는 효과가 있다. Further, according to the present invention, an oxide film having a thick rounded corner portion is formed on the second polysilicon film for the floating gate electrode, thereby reducing leakage current generated by a strong electric field at the edge portion of the control gate electrode to be formed later. There is an effect made.
본 발명은 구체적인 실시 예에 대해서만 상세히 설명하였지만 본 발명의 기술적 사상의 범위 내에서 변형이나 변경할 수 있음은 본 발명이 속하는 분야의 당업자에게는 명백한 것이며, 그러한 변형이나 변경은 본 발명의 특허청구범위에 속한다 할 것이다.Although the present invention has been described in detail only with respect to specific embodiments, it is apparent to those skilled in the art that modifications or changes can be made within the scope of the technical idea of the present invention, and such modifications or changes belong to the claims of the present invention. something to do.
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| KR1020040114140A KR20060075363A (en) | 2004-12-28 | 2004-12-28 | Method of forming a gate electrode pattern in flash memory device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100739988B1 (en) * | 2006-06-28 | 2007-07-16 | 주식회사 하이닉스반도체 | Method for fabricating flash memory device |
| US20110079839A1 (en) * | 2009-09-30 | 2011-04-07 | Fayrushin Albert | Non-Volatile Memory Devices Having Reduced Susceptibility to Leakage of Stored Charges and Methods of Forming Same |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100739988B1 (en) * | 2006-06-28 | 2007-07-16 | 주식회사 하이닉스반도체 | Method for fabricating flash memory device |
| US20110079839A1 (en) * | 2009-09-30 | 2011-04-07 | Fayrushin Albert | Non-Volatile Memory Devices Having Reduced Susceptibility to Leakage of Stored Charges and Methods of Forming Same |
| KR101533447B1 (en) * | 2009-09-30 | 2015-07-02 | 삼성전자주식회사 | Semiconductor Device |
| US9082750B2 (en) | 2009-09-30 | 2015-07-14 | Samsung Electronics Co, Ltd. | Non-volatile memory devices having reduced susceptibility to leakage of stored charges |
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