KR101145802B1 - Memory cell of nand type flash memory device and method for manufacturing the same - Google Patents

Abstract

The present invention is to provide a memory cell of the NAND flash memory device and a method of manufacturing the same that can minimize the interference effect between the memory cells, the present invention is formed on the tunnel oxide film and the tunnel oxide film formed on the substrate A floating gate having a depletion region formed by doping first conductive impurity ions in a central portion and doping second conductive impurity ions in a central portion thereof, a dielectric film formed on the floating gate, and a control formed on the dielectric film A memory cell of a NAND flash memory device including a gate is provided.

Nand Flash Memory Devices, Interference Effects, Depletion Zones

Description

MEMORY CELL OF NAND TYPE FLASH MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

1 to 6 are cross-sectional views illustrating a method of manufacturing a memory cell of a NAND flash memory device according to an exemplary embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a depletion layer formed on sidewalls of a polysilicon film through the process of FIG. 6.

8 is a cross-sectional view for explaining the working principle according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10: substrate 11: triple N well

12 P well 13 tunnel oxide film

14 polysilicon film 15 buffer oxide film

16: pad nitride film 17: hard mask

18 trench 19 side wall oxide film

20 device isolation layer 22 depletion layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a memory cell manufacturing method of a nonvolatile memory device, and more particularly, to a memory cell manufacturing method of a NAND flash memory device.

In NAND flash memory devices, a plurality of cells (16 or 32) for storing data are connected in series to form a string, and a cell string and a drain and a cell string and a source ( A drain select transistor and a source select transistor are connected between the sources, respectively.

The unit memory cell of the NAND flash memory device forms a device isolation film by a shallow trench isolation (STI) process, and then a tunnel oxide, a floating gate, a dielectric film, and a control gate are formed on the semiconductor substrate. gate) is formed by sequentially forming stacked gates and then forming source and drain regions in the substrate exposed to both sides of the stack gate structure.

In such a NAND flash memory device, it is very important to keep the cell state constant because the state of the cell is affected by the operation of adjacent neighboring cells. The change of the state of a cell due to the operation of adjacent neighboring cells, in particular a program operation, is called an interference effect. That is, the interference effect means that when a program operation is performed on a second cell adjacent to a first cell to be read, the first effect is due to a capacitance action caused by a charge change of the floating gate of the second cell. When the cell is read, a threshold voltage higher than the threshold voltage of the first cell is read. This phenomenon is referred to as a phenomenon in which the floating gate charge of the read cell does not change, but the state of the actual cell is changed by changing the state of the adjacent cell. Refers to a phenomenon that appears to be distorted.

As described above, the change of state of the memory cell due to the interference effect results in an increase in the defective rate of the device, which in turn lowers the yield of the device. Therefore, minimizing the interference effect may be effective to keep the state of the cell constant.

Accordingly, the present invention has been proposed to solve the above problems of the prior art, and has the following objects.

First, an object of the present invention is to provide a memory cell of a NAND flash memory device capable of minimizing interference effects between memory cells.

Second, another object of the present invention is to provide a method of manufacturing the NAND flash memory device.

In the present invention according to one aspect to achieve the above object, a tunnel oxide film formed on a substrate, and formed in the tunnel oxide film, the first conductive type impurity ions are doped in the center portion, the second conductive type impurities on both side walls Provided is a memory cell of a NAND flash memory device including a floating gate having a depletion region doped with ions, a dielectric film formed on the floating gate, and a control gate formed on the dielectric film.

According to another aspect of the present invention, there is provided a substrate on which a tunnel oxide film and a polysilicon film doped with a first conductivity type impurity ion are provided, the polysilicon film, the tunnel oxide film, and the like. Etching the substrate to form a trench, forming a device isolation film in which the trench is embedded, etching the device isolation film to expose a portion of sidewalls of the polysilicon film, and etching the exposed polysilicon film. A method of manufacturing a memory cell of a NAND flash memory device includes forming a depletion region by implanting second conductivity type impurity ions into a sidewall.

In general, the amount of interference is determined by the gate-to-gate capacitance to reduce the inter-cell interference. That is, the capacitance is proportional to the area between the contact surface and the distance between the contact surfaces.

Therefore, in the present invention, a method of effectively reducing the distance of the contact surface—the distance between neighboring floating gates—in order to reduce the inter-cell interference effect is used. For example, p-type impurity ions of opposite conductivity are implanted into both sidewalls of the polysilicon film for floating gate doped with n-type impurities to form a depletion region. That is, p-type impurity ions implanted into both sidewalls of the polysilicon film are distributed on both sidewalls of the polysilicon film doped with relatively high concentration n-type impurities to form a depletion region. In the ion implantation process, since the depletion depth of the small doping concentration is increased, the depletion region inside the polysilicon film is increased, and the gap between the gates can be obtained.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

1 to 6 are cross-sectional views illustrating a memory cell and a method of manufacturing the NAND flash memory device according to an exemplary embodiment of the present invention. Here, only five memory cells are shown for convenience of description. It is carried out by applying the Advanced Self Aligned-Shallow Trench Isolation (ASA-STI) process.

First, as shown in FIG. 1, a semiconductor substrate 10 subjected to a pretreatment cleaning process is provided. Here, the pretreatment cleaning process is washed with DHF (Diluted HF; for example, HF solution diluted with H ₂ 0 at a ratio of 50: 1) and then SC-1 (NH ₄ OH / H ₂ O ₂ / H ₂ O). Or a mixture of HF and NH ₄ F diluted with H ₂ O at a ratio of 100: 1 or 300: 1 (BH). Ratio can be washed with SC-1.

Subsequently, a screen oxide film (not shown) is formed on the semiconductor substrate 10. Here, the screen oxide film is formed to prevent the interface of the semiconductor substrate 10 from being damaged by the well or threshold voltage forming ion implantation process performed in a subsequent process.

Subsequently, an ion implantation process is performed in the semiconductor substrate 10 to form triple N-wells (hereinafter, referred to as TN-wells) 11. In this case, when the semiconductor substrate 10 is a p-type substrate, the TN-well 11 is formed by performing an ion implantation process using phosphorus (P).

Subsequently, a P-well 12 is formed in the TN-well 11. At this time, the P-well 12 is formed by an ion implantation process using boron (B).

Subsequently, a threshold voltage ion implantation process is performed on the semiconductor substrate 10 to form a channel.

Subsequently, a tunnel oxide film 13 is formed on the semiconductor substrate 10. Here, the tunnel oxide film 13 is formed thicker in the high voltage region than in the cell region and the low voltage region not shown.

As an example, a method of forming the tunnel oxide film 13 will be briefly described as follows. First, a wet oxidation process is performed to form a thin oxide film on the entire structure including a cell region, a low voltage region, and a high voltage region, and then a wet oxidation process using a mask in which the high voltage region is opened is performed once again, thereby performing a high voltage region. To form a thick oxide film. The oxide film may be formed by performing a wet oxidation process within a temperature range of 750 ° C to 800 ° C and then performing an annealing process using N ₂ at a temperature range of 900 ° C to 910 ° C.

Subsequently, a floating silicon polysilicon film 14 is deposited on the tunnel oxide film 13. Here, the polysilicon film 14 is deposited at a low pressure of 0.1 to 3 torr in a temperature range of 530 to 680 ° C. to minimize the grain size to prevent electric field concentration. Meanwhile, the polysilicon film 14 may be deposited as an undoped silicon film having low oxidation resistance, or may be deposited as a low concentration doped silicon film having a low doping concentration, and preferably LPCVD (Low Pressure Chemical) Vapor Deposition) to form a doped silicon film using Si ₂ H ₆ and PH ₃ gas.

Next, a buffer oxide film 15 is formed on the polysilicon film 14. The reason why the buffer oxide film 15 is formed is that when the pad nitride film 16 is directly formed on the polysilicon film 14, the polysilicon film 14 is damaged by plasma during the nitride film deposition process.

Next, the pad nitride film 16 is formed on the buffer oxide film 15. At this time, the pad nitride film 16 is deposited to a thickness of 100 ~ 500Å by LPCVD method.

Subsequently, a hard mask 17 is deposited on the pad nitride film 16 to a thickness of 200 microseconds.

Subsequently, after the photoresist film is applied onto the hard mask 17, an exposure and development process using a photo mask is performed to form a photoresist pattern (not shown). Here, the photoresist pattern is used as an etching mask for forming trenches in the cell region.

Subsequently, an etching process using the photoresist pattern as an etch mask is performed to preferentially etch the hard mask 17 in the cell region, and then the pad nitride layer 16 is sequentially formed using the etched hard mask 17 as an etch barrier layer. A portion of the buffer oxide film 15, the polysilicon film 14, the tunnel oxide film 13, and the semiconductor substrate 10 is etched to form a trench 18.

Subsequently, a strip process is performed to remove the photoresist pattern.

On the other hand, as in the cell region, a trench (not shown) is formed in the peripheral circuit region by sequentially performing a photolithography process and an etching process.

Next, as shown in FIG. 2, a wall oxidation process is performed in the trenches formed in the cell region and the peripheral circuit region, respectively, to form the sidewall oxide layer 19. In this case, the monthly oxidation process may be performed by a radical oxidation process to compensate for the sidewalls of the damaged trench during the trench forming process, and may be formed to a thickness of about 27 to 33 Å.

Subsequently, a liner oxide (not shown) may be formed on the sidewall oxide film 19. Here, the liner oxide layer may be formed by depositing Dichlorosilane (SiH ₂ Cl ₂ ) High Temperature Oxide (DCSHTO) on the inner wall of the trench to a thickness of about 30 kV and then performing an annealing process at a temperature of 800 ° C. to 850 ° C. The liner oxide layer is intended to prevent the tunnel oxide layer 13 from being exposed to plasma during the subsequent high density plasma deposition (HDP) oxide deposition process at the edge of the active region.

Subsequently, as shown in FIG. 3, the isolation layer 20 is deposited to fill the trench 18 (see FIG. 1). In this case, the device isolation layer 20 is formed of a high density plasma (HDP) single layer or an HDP / Spin On Glass (HDP) / HDP stacked layer, and the deposition method is as follows.

For example, in the case of forming an HDP / SOG / HDP laminated film, an HDP oxide film having excellent embedding characteristics is deposited first so that a portion of the trench 18 is embedded, and then a PSZ (PoliSilaZane) film is applied to completely fill the trench 18. The PSZ film is then recessed to expose some of the inner walls of the trench 18. Then, the process proceeds again by depositing an HDP oxide film.

Meanwhile, after the device isolation layer 20 is formed, a densification process may be performed using a heat treatment process such as a curing process. The reason for this is to stably polish the device separator 20 in a subsequent chemical mechanical polishing (CMP) process.

Subsequently, as shown in FIG. 4, the device isolation film 20 is polished by performing a chemical mechanical polishing process. At this time, the chemical mechanical polishing process is performed so that the hard mask 17 (see FIG. 3) is removed by performing excessive polishing. As a result, the pad nitride film 16 is exposed after the polishing process, and the device isolation film 20 is separated from neighboring ones and is isolated inside the trench 18 (see FIG. 1).

Subsequently, as illustrated in FIG. 5, an etching process is performed to adjust the effective field oxide height (EFH) of the device isolation film 20 in the cell region, thereby uniformly forming the device isolation film 20 formed in the cell region. Recess to depth. In this case, the etching process may be performed by a dry etching or a wet etching process, preferably a wet etching process by using an etching mask in which the peripheral circuit region is closed and the cell region is open, thereby exposing a part of the sidewalls of the polysilicon layer 14. Let's do it. In this process, the pad nitride film 16 is etched to about 10 to 30 microseconds.

Next, as shown in FIG. 6, the polysilicon film 14 may be formed on both sidewalls of the polysilicon film 14 that is partially exposed by the recess of the device isolation film 20 by the etching process of FIG. 5. A p-type impurity ion implantation process 21 having opposite characteristics to the doped n-type impurity is performed to form a depletion region 22 (see FIG. 7) distributed on both sidewalls of the polysilicon film 14. At this time, the p-type impurity ion implantation step 21 is ion implantation energy of about 500eV ~ 20keV and 1.0E11 ~ 5.0E13Atoms / cm ² using boron or BF ₂ ions It is set as the dose of degree.

Subsequently, although not shown, an etching process using phosphoric acid (H ₃ PO ₄ ) is performed to remove the pad nitride layer 16.

Next, the buffer oxide film 15 is removed.

Subsequently, a dielectric film (not shown) is deposited along the entire top surface of the structure. In this case, the dielectric film may be formed of an oxide film, a nitride film, or an oxide film (Oxide / Nitride / Oxide, ONO). For example, the oxide film is formed of DCS-HTO with a thickness of 40 kPa to 60 kPa in the temperature range of 800 ° C to 850 ° C, and the nitride film is formed with a thickness of 40 kPa to 80 kPa in the temperature range of 600 ° C to 700 ° C.

Next, a polysilicon film for control gate is formed on the dielectric film. In this case, the polysilicon film for the control gate may be formed in the same manner as the polysilicon film 14 for the floating gate.

Hereinafter, the principle of preventing the inter-cell interference effect by referring to FIG. 8 will be described.

Referring to FIG. 8, p-type impurity ions of opposite conductivity are implanted into both sidewalls of the polysilicon film 14 for floating gate doped with n-type impurities to form a depletion region 22. That is, p-type impurity ions implanted into both sidewalls of the polysilicon film 14 are distributed on both sidewalls of the polysilicon film 14 doped with relatively high concentration n-type impurities to form the depletion region 22. The depletion region 22 has an increased degree of oxidation during an oxidation process for a subsequent floating gate, and eventually, more oxide films are deposited or grown on both sidewalls of the floating gate, thereby physically increasing the space S between the floating gates. Losing effect can be obtained.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In particular, instead of the ASA-STI process applied in the embodiment, it can be applied to a similar SA-STI process as it is. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, p-type impurity ions of opposite conductivity are implanted into both sidewalls of the polysilicon film for floating gate doped with n-type impurity to form a depletion region, thereby widening the gap between the floating gates substantially. Interference effects can be reduced.

Claims (12)

delete delete delete delete Sequentially forming a polysilicon film for a floating gate doped with a tunnel oxide film and a first conductivity type impurity ion on the substrate; Etching the polysilicon layer, the tunnel oxide layer, and the substrate to form a trench; Forming a device isolation layer buried in the trench; Etching the device isolation layer to expose a portion of the sidewalls of the polysilicon layer; Implanting second conductivity type impurity ions into the exposed sidewall of the polysilicon film to form a depletion region; And Sequentially forming a dielectric film and a control gate on the resultant Memory cell manufacturing method of the NAND flash memory device comprising a. Claim 6 was abandoned when the registration fee was paid. The method of claim 5, Claim 7 was abandoned upon payment of a set-up fee. The method of claim 6, And the second conductivity type impurity ions are p-type impurity ions. Claim 8 was abandoned when the registration fee was paid. The method of claim 7, wherein A method for manufacturing a memory cell of a NAND flash memory device using B or BF ₂ as the p-type impurity ions. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 5, The device isolation film is a memory cell manufacturing method of the NAND flash memory device to form a HDP / SOG / HDP laminated film. Claim 10 was abandoned upon payment of a setup registration fee. And forming a buffer oxide film and a pad nitride film on the polysilicon film before forming the trench. Claim 11 was abandoned upon payment of a setup registration fee. 11. The method of claim 10, And forming a hard mask on the pad nitride film after the forming of the pad nitride film. Claim 12 is abandoned in setting registration fee. The method of claim 5, And forming a depletion region on a sidewall of the polysilicon layer, and then oxidizing the depletion region.

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