KR20050002060A - Method for protecting moat in semiconductor device with selective silicon recess - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to improve trench top corner rounding effect and to prevent moat by selectively recessing a silicon substrate. CONSTITUTION: A trench structure including a sidewall oxide layer(25) and a liner nitride layer(26) is formed in a silicon substrate. A trench isolation layer(27) is formed by filling an insulating layer in the trench to define an active region and a field region. A pre-cleaning process is carried out. The silicon substrate of the active region is selectively recessed. Then, a gate polysilicon layer is deposited on the resultant structure.

Description

Selective Silicon Recess Method for Manufacturing Semiconductor Devices Preventing Mortity {METHOD FOR PROTECTING MOAT IN SEMICONDUCTOR DEVICE WITH SELECTIVE SILICON RECESS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a semiconductor device in which only a silicon substrate is selectively recessed to round a trench edge and prevent moat.

When fabricating a semiconductor device, an element isolation film is formed to electrically isolate the device. As a method of forming such a device isolation layer, a local trench method using a thermal oxide film (Local Oxidation of Silicon: LOCOS) and a shallow trench isolation method (STI) using a trench structure which is advantageous for integration are used. This is applied a lot.

Among them, the LOCOS technique using a thermal oxide film has a process instability such as deterioration of a field oxide film due to a decrease in design rules of a semiconductor device, and an active region according to a bird's beak. Because of the problems such as the reduction of the required device isolation technology that can solve this problem.

The emerging technology is the shallow trench isolation (STI). The STI technique is a device isolation technique that defines an active region and a field region by forming a trench in a semiconductor substrate and gap-filling the inside of the trench with an insulating film. The STI technique is not applicable to an ultra-high density semiconductor device manufacturing process. It is a promising technology.

Among the DRAM memory device manufacturing processes, the STI process is known to be one of the important factors that ultimately influence the performance of the DRAM device because the STI process has a great influence on the electrical characteristics of the transistor along with the gate electrode forming process.

Referring to FIGS. 1A to 1E, a conventional STI forming process is as follows. First, as shown in FIG. 1A, a pad oxide film 11, a pad nitride film 12, and a photoresist film 13 are sequentially formed on a semiconductor substrate 10, and then an exposure / development process is performed to form a device isolation film. The semiconductor substrate 10 is exposed by patterning to completely remove the pad oxide film 11 and the pad nitride film 12 in the region.

Next, the photoresist layer 13 is removed and the semiconductor layer 10 is etched by a predetermined thickness using the pad nitride layer 12 as an etching mask to form a trench structure in which the device isolation layer is embedded.

Subsequently, as shown in FIG. 1B, a silicon substrate having a predetermined thickness is oxidized by thermal oxidation for the purpose of protecting the silicon sidewalls of the trench sidewalls and the bottom to form a sidewall oxide film 15 along the surface of the trench. Subsequently, a thin liner nitride film 16 having a predetermined thickness is deposited on the sidewall oxide film 15 by chemical vapor deposition. Next, when a thin liner oxide film (not shown) is deposited on the liner nitride film 16 by CVD, a liner for trenches is formed.

The use of a liner in this way reduces the stress agglomerated on the silicon substrate and suppresses the diffusion of dopants from the device isolation film to the silicon substrate, thereby improving the refresh characteristics of the device. It is known to become.

Next, after the trench is filled with the insulating film 17 to be used as the device isolation film, chemical mechanical polishing for planarization is completed to complete the structure shown in FIG. 1B.

Next, as shown in FIG. 1C, when the cleaning process using the phosphoric acid solution (H ₃ PO ₄ ) is performed, the pad nitride film 12 is removed and only the pad oxide film 11 remains on the silicon substrate 10.

In the subsequent process, an ion implantation process for adjusting the threshold voltage of the gate is performed. In this ion implantation process, a screen oxide film is formed to protect the substrate. Before the screen oxide film is formed, a wet cleaning process using an HF or BOE solution is performed for the purpose of cleaning the silicon substrate. At this time, the remaining pad oxide film 11 is also removed.

During the wet cleaning process, the sidewall oxide layer 15 formed between the silicon substrate 10 and the liner nitride layer 16 is also wet-etched to generate a moat phenomenon in which the trench device isolation layer is lower than the silicon substrate. This is shown in Figure 1d.

Referring to FIG. 1D, the depth of the moat is deeply formed, and the moat becomes deeper in subsequent oxidation and cleaning processes existing up to the gate polysilicon 18 forming process.

Thus, looking at the device cross section after the gate polysilicon 18 is deposited, it develops into a very serious level of moat, as shown in FIG. 1D.

This deep moat results in angled active areas in contact with the trench, which in turn causes concentration of the electric field, leading to a decrease in threshold voltage (Vt).

In addition to the above-mentioned problems, it reduced the critical dimension (CD) of the active region, and formed a polysilicon residue (molecular silicon residue) in the mote region to act as a factor to reduce the yield and stability of the device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object thereof is to provide a method for forming a semiconductor device in which a silicon substrate is selectively recessed to suppress moats.

1A to 1E are cross-sectional views illustrating a process of forming a semiconductor device according to the prior art;

2A through 2F are cross-sectional views illustrating a process of forming a semiconductor device in accordance with an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

20: substrate

21: pad oxide film

22: pad nitride film

23: pad photosensitive film

24: trench

25: sidewall oxide film

26: liner nitride film

27: insulating film

28: gate oxide film

According to an aspect of the present invention, a trench structure including a sidewall oxide layer and a liner nitride layer is formed on a silicon substrate, and the trench structure is filled with an insulating layer to form a trench isolation layer defining an active region and a field region. step; Performing a pre-cleaning process before forming the screen oxide film; Selectively recessing only the silicon substrate among the sidewall oxide film, the liner nitride film, and the silicon substrate; And depositing gate polysilicon over the entire structure.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device. In particular, a method of forming a semiconductor device in which a rounding of an STI active region is formed by introducing a new concept of a process called a selective Si recess, and at the same time, suppresses a mot It is about.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

2A through 2F are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.

First, the process until the wet cleaning process using the HF or BOE solution for the purpose of cleaning the silicon substrate before forming the screen oxide film is the same as in the prior art.

That is, as shown in FIG. 2A, the pad oxide film 21, the pad nitride film 22, and the photoresist film 23 are sequentially formed on the semiconductor substrate 20, and then an exposure / development process is performed to form a device isolation film. The semiconductor substrate 20 is exposed by patterning to completely remove the pad oxide film 21 and the pad nitride film 22 in the region.

Next, the photoresist layer (not shown) is removed and the semiconductor substrate 20 is etched by a predetermined thickness using the pad nitride layer 22 as an etch mask to form a trench structure 24 in which the device isolation layer is to be embedded.

Next, as shown in FIG. 2B, the silicon substrate having a predetermined thickness is oxidized using a thermal oxidation method to form the sidewall oxide layer 25 to protect the silicon substrates on the trench sidewalls and the bottom.

Next, a thin liner nitride film 26 having a predetermined thickness is deposited on the sidewall oxide film 25 by chemical vapor deposition, and a thinner liner oxide film (not shown) is deposited on the liner nitride film 26 by CVD. A trench liner is formed.

Subsequently, the trench structure is filled with an insulating film 27 such as an HDP oxide film, followed by chemical mechanical polishing for planarization, thereby completing the structure shown in FIG. 2B.

Next, as shown in FIG. 2C, when the cleaning process using the phosphoric acid solution (H ₃ PO ₄ ) is performed, the pad nitride film 12 is removed and only the pad oxide film 21 remains on the silicon substrate 20.

In the subsequent process, an ion implantation process for adjusting the threshold voltage of the gate is performed. In this ion implantation process, a screen oxide film is formed to protect the substrate. Before the screen oxide film is formed, a wet cleaning process using HF or BOE solution is performed for the purpose of cleaning the silicon substrate, and the remaining pad oxide film 21 is also removed.

In this wet cleaning process, the sidewall oxide layer 15 formed between the silicon substrate 10 and the liner nitride layer 16 is also wet-etched to generate a moat phenomenon in which the trench device isolation layer is lower than the silicon substrate. This is shown in Figure 2d.

That is, the moat is generated by wet etching the sidewall oxide layer as in the prior art, but in one embodiment of the present invention, only the silicon substrate is selectively recessed in a subsequent process to reduce the depth of the moat.

After the pre-cleaning process before forming the screen oxide film as shown in FIG. 2D is performed, the selective silicon recess process shown in FIG. 2E is performed.

In the selective silicon recess process, since the sidewall oxide layer 25, the liner nitride layer 26, and the insulating layer 27 do not etch, only the silicon substrate 20 is selectively etched. It may be destroyed and eventually destroyed.

Comparing FIG. 2E according to an embodiment of the present invention with FIG. 1D according to the related art, it is understood that the depth of the moat is reduced, and as a result, the STI top corner rounding is naturally formed.

The process conditions of the selective silicon recess process according to the embodiment of the present invention are related to the loss of the sidewall oxide film and the nitride film of the liner which are lost in a subsequent process to be performed after this process.

For example, if the moiety caused by wet etching of the sidewall oxide film and the liner nitride film occurs in the process from the pre-cleaning process before the screen oxide film formation to the gate polysilicon deposition in the current STI process, the selective silicon recess process If the silicon substrate is recessed by about 150ms, theoretically 0m can be achieved.

The result of reducing the depth of the moat in accordance with one embodiment of the present invention is shown in Figure 2f. Referring to Figure 2f, it can be seen that since the silicon substrate is selectively recessed, the depth of the moat is greatly reduced, and the trench corner top rounding is also naturally formed.

In this selective silicon recess process, only silicon may be selectively etched to the oxide and nitride layers. For this etching solution, a mixed solution of HNO ₃ + HF may be used, or NH ₄ OH + H ₂ O ₂ + H _2. A mixed solution of O can also be used.

Alternatively, in addition, a solution such as KOH, NH ₄ OH, HF, HNO ₃ , H ₂ O ₂ , and H ₂ O may be mixed at a predetermined ratio and used as an etchant. desirable.

In an embodiment of the present invention, a wet etching method is applied for selective silicon recesses, but a dry etching method may also be applied. In this case, Cl ₂ gas may be used alone as an etching gas, or HBr gas may be used. Ar gas can also be mixed and used.

After reducing the moat depth through this selective silicon recess process, gate polysilicon 28 is deposited and a series of processes are performed as shown in FIG. 2F.

Application of the present invention to the manufacture of semiconductor devices has the advantage that the depth of the moat can be made shallow or the moat can be prevented from occurring. Therefore, as the occurrence of the moat is suppressed has the following advantages.

First, the reduction of the threshold voltage can be prevented, and second, the bridge due to the polysilicon residual film remaining in the moat can be prevented, and third, the active region loss associated with the moat formation can be prevented.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in the art.

Application of the present invention to the fabrication of semiconductor devices improves the rounding of the trench top corners, thereby making it possible to prevent the generation of gate residual films in subsequent gate patterning processes, thereby reducing the bridge phenomenon and the threshold voltage between the devices. Can be prevented.

Claims (5)

Forming a trench structure including a sidewall oxide layer and a liner nitride layer on a silicon substrate, and filling the trench structure with an insulating layer to form a trench isolation layer defining an active region and a field region; Performing a pre-cleaning process before forming the screen oxide film; Selectively recessing only the silicon substrate among the sidewall oxide film, the liner nitride film, and the silicon substrate; And Depositing gate polysilicon over the entire structure Method of manufacturing a semiconductor device comprising a. The method of claim 1, Selectively recessing only the silicon substrate, A method for manufacturing a semiconductor device, comprising using wet etching using a mixed solution of HNO ₃ + HF or a mixed solution of NH ₄ OH + H ₂ O ₂ + H ₂ O. The method of claim 2, The temperature of the mixed solution is a manufacturing method of a semiconductor device, characterized in that -10 ~ 150 ℃. The method of claim 1, Selectively recessing only the silicon substrate, A method of manufacturing a semiconductor device, characterized in that it is carried out by a dry etching method using an etching gas in which Cl ₂ gas or HBr gas and Ar gas are mixed. The method of claim 1, Selectively recessing only the silicon substrate, The amount of silicon substrate that is recessed And the depth of the moat caused by the loss of the sidewall oxide film and the liner nitride film between the precleaning process and the process of depositing the gate polysilicon.