CN104425345A - Formation method for shallow trench isolation structure - Google Patents
Formation method for shallow trench isolation structure Download PDFInfo
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- CN104425345A CN104425345A CN201310407724.3A CN201310407724A CN104425345A CN 104425345 A CN104425345 A CN 104425345A CN 201310407724 A CN201310407724 A CN 201310407724A CN 104425345 A CN104425345 A CN 104425345A
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- ion
- formation method
- isolation structure
- plough groove
- fleet plough
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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Abstract
The invention discloses a formation method for a shallow trench isolation structure. The formation method comprises the step of carrying out an ion implantation treatment on a semiconductor substrate at the corner of a shallow trench isolation area after forming the shallow trench isolation area, wherein stress at the corner can be reduced, thus a third dielectric layer is subsequently formed at the corner and not liable to break through, and then the performance of a device is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of formation method of fleet plough groove isolation structure.
Background technology
Fleet plough groove isolation structure is formed among Semiconductor substrate usually, and filled media layer is used for isolation of semiconductor devices.Fleet plough groove isolation structure forming step of the prior art comprises:
Semiconductor substrate 10 is provided, described Semiconductor substrate 10 forms oxide layer 20, hard mask layer 30 successively, as shown in Figure 1;
Etch described mask layer 30, oxide layer 20 and Semiconductor substrate 10 successively, form shallow channel isolation area 11 and expose Semiconductor substrate 10, as shown in Figure 2;
Semiconductor substrate 10 surface exposed in channel separating zone 11 forms lining oxide layer 40, as shown in Figure 3;
Form fleet plough groove isolation structure 50 on the surface of described lining oxide layer 40 and described hard mask layer 30, described fleet plough groove isolation structure 50 fills described shallow channel isolation area, and the material of wherein said fleet plough groove isolation structure 50 is silicon dioxide;
Use CMP process grinding to remove described hard mask layer 30 and part fleet plough groove isolation structure, expose oxide layer 20, as shown in Figure 5.
But when follow-up formation device, the grid in device is understood some and is ridden on described fleet plough groove isolation structure 50, and namely grid is formed on oxide layer 20 and fleet plough groove isolation structure 50.After device is formed, usually a series of test is carried out to device, whether meet standard with the performance of detection means.Wherein a detection is energized to device, the breakdown characteristics of test oxide layer 20.But the silicon dioxide formed due to fleet plough groove isolation structure 50 and corner's (as shown in Fig. 5 dotted line) of described Semiconductor substrate 10 is thinner, the stress that is subject to of corner is larger simultaneously; Therefore, when carrying out device being energized the breakdown characteristics testing oxide layer 20, the silicon dioxide of corner is normally the weakest, the most breakdown part, and this just causes the unstable properties of device, is unfavorable for the stability improving semiconductor device entirety.
So how to avoid the problems referred to above, the anti-breakdown performance improving corner's silicon dioxide just becomes the technical problem that those skilled in the art are badly in need of solution.
Summary of the invention
The object of the present invention is to provide a kind of formation method of fleet plough groove isolation structure, the anti-breakdown performance of corner's dielectric layer can be promoted.
To achieve these goals, the present invention proposes a kind of formation method of fleet plough groove isolation structure, comprises step:
Semiconductor substrate is provided, forms first medium layer and hard mask layer successively on the semiconductor substrate;
Etch described hard mask layer, first medium layer and Semiconductor substrate successively, forming shallow channel isolation area, there is turning at described shallow channel isolation area place in described Semiconductor substrate;
In described shallow channel isolation area, form second dielectric layer, described second dielectric layer exposes described turning;
Carry out ion implantation process to described turning, the ion beam that described ion implantation process uses and horizontal line are predetermined angle;
The 3rd dielectric layer is formed on described second dielectric layer surface.
Further, the ion beam that described ion implantation process uses comprises antimony ion, carbon ion and Nitrogen ion.
Further, the ion beam that described ion implantation process uses comprises C
2b
10h
12and oxonium ion.
Further, the ion beam that described ion implantation process uses comprises BF
2ion, carbon ion and Nitrogen ion.
Further, the ion energy range of described ion implantation process is 3KeV ~ 30KeV.
Further, the ion dose scope of described ion implantation process is 1e15/cm
2~ 1e16/cm
2.
Further, the ion beam of described ion implantation process and horizontal line are the scope of predetermined angle is 10 ° ~ 35 °.
Further, after etching described hard mask layer, first medium layer and Semiconductor substrate form shallow channel isolation area, at the turning at shallow channel isolation area place, etching is carried out back to described Semiconductor substrate.
Further, the material of described first medium layer is silicon dioxide, and thickness range is 100 dust ~ 400 dusts.
Further, the material of described hard mask layer is silicon nitride, and thickness range is 400 dust ~ 800 dusts.
Further, the material of described second dielectric layer and described 3rd dielectric layer is silicon dioxide.
Compared with prior art, beneficial effect of the present invention is mainly reflected in: after formation shallow channel isolation area, to described Semiconductor substrate, the corner in shallow channel isolation area carries out ion implantation process, the stress of corner can be reduced, make follow-up formation around the corner the 3rd dielectric layer not easily breakdown, and then improve the performance of device.
Accompanying drawing explanation
Fig. 1 to Fig. 4 is the generalized section that in prior art, fleet plough groove isolation structure is formed;
Fig. 5 is the flow chart of the formation method of fleet plough groove isolation structure in one embodiment of the invention;
Fig. 6 to Figure 11 is the generalized section of the formation method of fleet plough groove isolation structure in one embodiment of the invention.
Embodiment
Be described in further detail below in conjunction with the formation method of the drawings and specific embodiments to the fleet plough groove isolation structure that the present invention proposes.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 5, in the present embodiment, propose a kind of formation method of fleet plough groove isolation structure, comprise step:
S100: provide Semiconductor substrate 100, described Semiconductor substrate 100 forms first medium layer 200 and hard mask layer 300 successively, as shown in Figure 6;
Wherein, described Semiconductor substrate 100 can be silicon substrate, silicon-Germanium substrate or silicon-on-insulator substrate; Wherein, the material of described first medium layer 200 is silicon dioxide, and its thickness range is 100 dust ~ 400 dusts, such as, be 200 dusts; The material of described hard mask layer 300 is silicon nitride, and its thickness range is 400 dust ~ 800 dusts, such as, be 500 dusts, as the mask layer of etching.
S200: etch described hard mask layer 300, first medium layer 200 and Semiconductor substrate 100 successively, forming shallow channel isolation area 110, there is turning, as shown in Fig. 7 dotted line at described shallow channel isolation area 110 place in described Semiconductor substrate 100;
After formation shallow channel isolation area 110, use wet etching to carry out back etching (Pull-Back) to described Semiconductor substrate 100 and described hard mask layer 300 and first medium layer 200 to process, thus it is long-pending to make described Semiconductor substrate 100 expose more multiaspect at the turning at shallow channel isolation area 110 place, be convenient to the dielectric layer that follow-up formation is thicker, improve the breakdown characteristics of corner's dielectric layer.
S300: form second dielectric layer 400 in described shallow channel isolation area 110, described second dielectric layer 400 exposes described turning, as shown in Figure 8;
In this step; the second dielectric layer 400 formed is in order to protect other regions of described Semiconductor substrate 100; avoid follow-uply damaging other regions of described Semiconductor substrate 100 when carrying out ion implantation process, expose described turning simultaneously and be convenient to follow-uply carry out ion implantation process to described turning.
S400: ion implantation process is carried out to described turning, the ion beam that described ion implantation process uses and horizontal line are predetermined angle α, as shown in Figure 9;
In this step, described ion beam can comprise antimony ion (Sb), carbon ion (C) and Nitrogen ion (N) or comprise C
2b
10h
12with oxonium ion (O) or comprise BF
2ion, carbon ion (C) and Nitrogen ion (N); The ion energy range of described ion implantation process is 3KeV ~ 30KeV, such as, be 110KeV; The ion dose scope of described ion implantation process is 1e15/cm
2~ 1e16/cm
2, such as, be 2e15/cm
2; The ion beam of described ion implantation process and horizontal line are the scope of predetermined angle is 10 ° ~ 35 °, such as, be 20 °, thus can form the region 500 containing B or Sb around the corner, as shown in Figure 10.
Wherein C or N can play the inhibitory action to B or Sb, namely when B or Sb is injected into the corner of Semiconductor substrate 100 and described second dielectric layer 400, B or Sb can be limited in the position injecting time domain 500 by C or N, prevent it to run off, avoid causing the effect of ion implantation process greatly to reduce; Due to the stress of corner can be reduced after ion implantation, thus the breakdown characteristics of the dielectric layer that corner is formed can be improved, and then the stability of device can be improved.
S500: form the 3rd dielectric layer on described second dielectric layer 400 surface;
Wherein, described second dielectric layer 400 is all silicon dioxide with described 3rd dielectric layer, and constitutes described fleet plough groove isolation structure 600, as shown in figure 11.
To sum up, in the formation method of the fleet plough groove isolation structure provided in the embodiment of the present invention, after formation shallow channel isolation area, to described Semiconductor substrate, the corner in shallow channel isolation area carries out ion implantation process, the stress of corner can be reduced, make follow-up formation around the corner the 3rd dielectric layer not easily breakdown, and then improve the performance of device.
Above are only the preferred embodiments of the present invention, any restriction is not played to the present invention.Any person of ordinary skill in the field; in the scope not departing from technical scheme of the present invention; the technical scheme disclose the present invention and technology contents make the variations such as any type of equivalent replacement or amendment; all belong to the content not departing from technical scheme of the present invention, still belong within protection scope of the present invention.
Claims (11)
1. a formation method for fleet plough groove isolation structure, comprises step:
Semiconductor substrate is provided, forms first medium layer and hard mask layer successively on the semiconductor substrate;
Etch described hard mask layer, first medium layer and Semiconductor substrate successively, forming shallow channel isolation area, there is turning at described shallow channel isolation area place in described Semiconductor substrate;
In described shallow channel isolation area, form second dielectric layer, described second dielectric layer exposes described turning;
Carry out ion implantation process to described turning, the ion beam that described ion implantation process uses and horizontal line are predetermined angle;
The 3rd dielectric layer is formed on described second dielectric layer surface.
2. the formation method of fleet plough groove isolation structure as claimed in claim 1, is characterized in that, the ion beam that described ion implantation process uses comprises antimony ion, carbon ion and Nitrogen ion.
3. the formation method of fleet plough groove isolation structure as claimed in claim 1, is characterized in that, the ion beam that described ion implantation process uses comprises C
2b
10h
12and oxonium ion.
4. the formation method of fleet plough groove isolation structure as claimed in claim 1, is characterized in that, the ion beam that described ion implantation process uses comprises BF
2ion, carbon ion and Nitrogen ion.
5. the formation method of fleet plough groove isolation structure as claimed in claim 1, it is characterized in that, the ion energy range of described ion implantation process is 3KeV ~ 30KeV.
6. the formation method of fleet plough groove isolation structure as claimed in claim 5, it is characterized in that, the ion dose scope of described ion implantation process is 1e15/cm
2~ 1e16/cm
2.
7. the formation method of fleet plough groove isolation structure as claimed in claim 6, is characterized in that, the ion beam of described ion implantation process and horizontal line are the scope of predetermined angle is 10 ° ~ 35 °.
8. the formation method of fleet plough groove isolation structure as claimed in claim 1, it is characterized in that, after etching described hard mask layer, first medium layer and Semiconductor substrate form shallow channel isolation area, at the turning at shallow channel isolation area place, etching is carried out back to described Semiconductor substrate.
9. the formation method of fleet plough groove isolation structure as claimed in claim 1, it is characterized in that, the material of described first medium layer is silicon dioxide, and thickness range is 100 dust ~ 400 dusts.
10. the formation method of fleet plough groove isolation structure as claimed in claim 1, it is characterized in that, the material of described hard mask layer is silicon nitride, and thickness range is 400 dust ~ 800 dusts.
The formation method of 11. fleet plough groove isolation structures as claimed in claim 1, is characterized in that, the material of described second dielectric layer and described 3rd dielectric layer is silicon dioxide.
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| CN201310407724.3A CN104425345B (en) | 2013-09-09 | 2013-09-09 | The forming method of fleet plough groove isolation structure |
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| CN201310407724.3A CN104425345B (en) | 2013-09-09 | 2013-09-09 | The forming method of fleet plough groove isolation structure |
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| CN104425345B CN104425345B (en) | 2018-06-01 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106558528A (en) * | 2015-09-25 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method, electronic installation |
| CN112071900A (en) * | 2020-11-16 | 2020-12-11 | 晶芯成(北京)科技有限公司 | Semiconductor isolation structure and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63133664A (en) * | 1986-11-26 | 1988-06-06 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| WO1999025018A1 (en) * | 1997-11-07 | 1999-05-20 | Advanced Micro Devices, Inc. | Semiconductor device having an improved isolation region and process of fabrication thereof |
| US6150237A (en) * | 1999-10-18 | 2000-11-21 | United Silicon Inc. | Method of fabricating STI |
| KR20030050199A (en) * | 2001-12-18 | 2003-06-25 | 주식회사 하이닉스반도체 | Method of forming a isolation layer in a semiconductor device |
-
2013
- 2013-09-09 CN CN201310407724.3A patent/CN104425345B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63133664A (en) * | 1986-11-26 | 1988-06-06 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| WO1999025018A1 (en) * | 1997-11-07 | 1999-05-20 | Advanced Micro Devices, Inc. | Semiconductor device having an improved isolation region and process of fabrication thereof |
| US6150237A (en) * | 1999-10-18 | 2000-11-21 | United Silicon Inc. | Method of fabricating STI |
| KR20030050199A (en) * | 2001-12-18 | 2003-06-25 | 주식회사 하이닉스반도체 | Method of forming a isolation layer in a semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106558528A (en) * | 2015-09-25 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method, electronic installation |
| CN112071900A (en) * | 2020-11-16 | 2020-12-11 | 晶芯成(北京)科技有限公司 | Semiconductor isolation structure and manufacturing method thereof |
| CN112071900B (en) * | 2020-11-16 | 2021-03-09 | 晶芯成(北京)科技有限公司 | Semiconductor isolation structure and manufacturing method thereof |
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| CN104425345B (en) | 2018-06-01 |
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