CN112071900B - Semiconductor isolation structure and manufacturing method thereof - Google Patents
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Abstract
The invention provides a semiconductor isolation structure and a manufacturing method thereof. In the manufacturing method, a plurality of grooves are formed on the semiconductor substrate, then a pull-back process is carried out to enable the side walls of a pad oxide layer and a hard mask layer on the semiconductor substrate to contract inwards, a first isolation medium layer is filled in the grooves, then an ion injection process is carried out to enable a modified area to be formed at the upper part of the first isolation medium layer, the depth of the modified area is larger than or equal to the total thickness of the pad oxide layer and the hard mask layer, then partial first isolation medium layer in the modified area is removed through soaking by using etching liquid, holes in the first isolation medium layer can be opened or even removed, and a second isolation medium layer is filled in the grooves, so that the reduction of the holes in the isolation medium in the grooves is facilitated, and the filling quality of the grooves and the performance of a semiconductor. The semiconductor isolation structure is obtained by the manufacturing method.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor isolation structure and a manufacturing method thereof.
Background
In the semiconductor process technology of today, the Shallow Trench Isolation (STI) process is one of the most important and complicated processes in the front-end process. The basic requirements for the shallow trench isolation process are: when a large number of transistor devices and the like are integrated on smaller and smaller chips, the transistor devices can well isolate each tiny device without affecting the operating characteristics of the devices.
The manufacturing method of the conventional semiconductor isolation structure comprises the following processes: firstly, sequentially forming a pad oxide layer and a patterned hard mask layer on a semiconductor substrate such as a silicon wafer; then, etching the pad oxide layer and the semiconductor substrate by taking the graphical hard mask layer as a mask so as to form a groove in the laminated structure of the semiconductor substrate, the pad oxide layer and the hard mask layer; then, the trench is filled with an isolation medium.
With the rapid development of semiconductor manufacturing technology, integrated circuit manufacturing processes have entered the submicron era, and the sizes of semiconductor devices and isolation structures for isolating the semiconductor devices, such as shallow trench isolation, have also been reduced. In the manufacturing process of the high-voltage semiconductor device below 55nm, when the isolation structure is manufactured by using the manufacturing method, after a semiconductor substrate is etched to form a groove and before an isolation medium is filled, a Pull back process (Pull back) for a hard mask layer and a pad oxide layer is added, so that the side walls of the hard mask layer and the pad oxide layer are retracted to facilitate the filling of the isolation medium. However, research finds that after the pull-back process is performed, the sidewall of the pad oxide layer is easily retracted to the lower side of the hard mask layer, so that the sidewall of the trench is recessed in a step shape, and a hole is easily formed in the upper portion of the isolation medium in a subsequent filling process, thereby causing poor filling effect and affecting the performance of the isolation structure.
Disclosure of Invention
The invention provides a semiconductor isolation structure and a manufacturing method thereof, aiming at solving the problem that holes exist in an isolation medium in the semiconductor isolation structure and improving the performance of the semiconductor isolation structure.
One aspect of the present invention provides a method for manufacturing a semiconductor isolation structure, including:
providing a semiconductor substrate, wherein a pad oxide layer and a hard mask layer are sequentially formed on the semiconductor substrate in an overlapping manner, a plurality of grooves are formed on the semiconductor substrate, the grooves penetrate through the hard mask layer and the pad oxide layer, the bottom surfaces of the grooves are located in the semiconductor substrate, and the grooves expose the hard mask layer and the side walls of the pad oxide layer;
performing a pull-back process to enable the hard mask layer and the side wall of the pad oxide layer to retract inwards along the direction of expanding the groove opening;
forming a first isolation medium layer on the semiconductor substrate, wherein the groove is filled with the first isolation medium layer;
performing an ion implantation process to form a modified area on the upper part of the first isolation dielectric layer, wherein the depth of the modified area is more than or equal to the total thickness of the pad oxide layer and the hard mask layer;
removing part of the first isolation medium layer of the modified area by using etching liquid; and
and forming a second isolation medium layer on the semiconductor substrate, wherein the second isolation medium layer fills the groove.
Optionally, after the performing of the pull-back process and before forming the first isolation dielectric layer, the manufacturing method further includes:
and forming a protective layer on the semiconductor substrate, wherein the protective layer covers the inner surface of the groove and does not fill the groove, and the protective layer protects the semiconductor substrate when the ion implantation process is carried out.
Optionally, after the first isolation dielectric layer is formed and before the ion implantation process is performed, the manufacturing method further includes:
and performing a planarization process, and removing part of the thickness of the first isolation medium layer to enable the upper surface of the first isolation medium layer to be flush with the upper surface of the protective layer.
Optionally, the depth of the modified region is 150 nm-190 nm.
Optionally, the first isolation dielectric layer and the second isolation dielectric layer are silicon oxide.
Optionally, after removing a part of the first isolation dielectric layer of the modified region by using an etching solution to soak, before forming the second isolation dielectric layer, the manufacturing method further includes:
and spraying the semiconductor substrate with ozone water solution.
Optionally, the dopant injected into the first isolation dielectric layer by the ion implantation process is carbon or germanium; the energy adopted by the ion implantation process is 290 KV-310 KV, and the implantation dosage of the dopant is 2e14 atoms/square centimeter-3 e14 atoms/square centimeter.
Optionally, the etching solution includes hydrofluoric acid.
Optionally, the thickness of the pad oxide layer is 900 angstroms to 1100 angstroms.
In another aspect of the present invention, a semiconductor isolation structure is obtained by the above manufacturing method, and the semiconductor isolation structure includes:
the groove is formed on the semiconductor substrate, the bottom surface of the groove is positioned in the semiconductor substrate, and the groove exposes the side wall of the pad oxide layer positioned on the surface of the semiconductor substrate;
the first isolation medium layer is filled at the bottom of the groove and does not fill the groove; and
and the second isolation dielectric layer covers the first isolation dielectric layer and fills the groove.
In the manufacturing method of the semiconductor isolation structure, after a first isolation medium layer is deposited and formed on a semiconductor substrate, an ion implantation process is executed, so that a modified area is formed at the upper part of the first isolation medium layer, the depth of the modified area is more than or equal to the total thickness of the pad oxide layer and the hard mask layer, the first isolation medium layer of the modified area is loose, when the semiconductor substrate is soaked by etching liquid, part of the first isolation medium layer of the modified area can be quickly removed, when a hole exists in the first isolation medium layer, the part of the first isolation medium layer near the hole can be more easily removed, the hole can be opened or even removed, the part of the first isolation medium layer below the modified area is not easy to erode, a second isolation medium layer is formed on the semiconductor substrate, and the groove is filled with the second isolation medium layer, the method is favorable for reducing holes in the isolation medium in the groove, improving the filling quality of the groove and improving the performance of the semiconductor isolation structure. In addition, in the process of removing part of the first isolation medium layer of the modified area by using etching liquid for soaking, the etching selection ratio of the first isolation medium layer of the modified area is greater than that of the first isolation medium layer below the modified area, so that the first isolation medium layer below the modified area can be reserved, the filling depth of a subsequent second isolation medium layer is favorably reduced, the filling difficulty of the groove is reduced, and the filling efficiency and the filling quality of the groove are improved.
Further, after the performing the pull-back process and before forming the first isolation dielectric layer, the method may further include: and forming a protective layer on the semiconductor substrate, wherein the protective layer covers the inner surface of the groove and does not fill the groove, the protective layer protects the semiconductor substrate when the ion implantation process is executed, so that the semiconductor substrate is not influenced by the ion implantation, and meanwhile, when part of the first isolation medium layer of the modified area is removed by soaking with an etching solution, the protective layer can prevent the pad oxide layer from being removed by etching, thereby being beneficial to improving the performance of a semiconductor device adopting the semiconductor isolation structure.
The semiconductor isolation structure is obtained by the manufacturing method. The manufacturing method can improve the filling quality of the groove, so that the semiconductor isolation structure has better quality and higher reliability, and is beneficial to improving the performance of a semiconductor device adopting the semiconductor isolation structure.
Drawings
Fig. 1 to 4 are schematic cross-sectional views illustrating a plurality of steps of a conventional method for fabricating a semiconductor isolation structure.
Fig. 5 is a flowchart illustrating a method for fabricating a semiconductor isolation structure according to an embodiment of the invention.
Fig. 6 to 13 are schematic cross-sectional views illustrating steps of a method for fabricating a semiconductor isolation structure according to an embodiment of the invention.
The reference numerals of fig. 1 to 4 illustrate:
100-a semiconductor substrate; 101-pad oxide layer; 102-a hard mask layer; 103-a trench; 104-isolation medium.
The reference numerals of fig. 6 to 13 illustrate:
200-a semiconductor substrate; 201-pad oxide layer; 202-a hard mask layer; 203-a trench; 204-repair layer; 205-a protective layer; 206-a first isolation dielectric layer; 206 a-a modified region; 207-second isolation dielectric layer.
Detailed Description
The semiconductor isolation structure and the method for fabricating the same according to the present invention will be described in detail with reference to the accompanying drawings and embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In order to highlight the features and advantages of the semiconductor isolation structure and the manufacturing method thereof of the present invention, a conventional manufacturing method of the semiconductor isolation structure is described below. Fig. 1 to 4 are schematic cross-sectional views illustrating a plurality of steps of a conventional method for fabricating a semiconductor isolation structure. As shown in fig. 1 to 4, the method for fabricating the semiconductor isolation structure includes the following steps.
As shown in fig. 1, a pad oxide layer 101 and a hard mask layer are sequentially formed on a semiconductor substrate 100 in an overlapping manner, and a patterning process is performed on the hard mask layer 102 to form a patterned hard mask layer 102.
As shown in fig. 2, the patterned hard mask layer 102 is used as a mask to etch the pad oxide layer 101 and the semiconductor substrate 100, thereby forming a plurality of trenches 103, wherein the trenches 103 expose sidewalls of the pad oxide layer 101 and the hard mask layer 102 and bottom surfaces of the trenches 103 are located in the semiconductor substrate 100.
As shown in fig. 3, a pull-back process is performed to retract the sidewalls of the hard mask layer 102 and the pad oxide layer 101 in a direction to enlarge the opening of the trench 103.
As shown in fig. 4, the trench 103 is filled with an isolation dielectric 104.
In the process of pulling back the hard mask layer 102 and the pad oxide layer 101, the sidewall of the pad oxide layer 101 is easily retracted below the hard mask layer 102, so that a step-shaped recess (shown in a dotted circle in fig. 3) is generated on the sidewall of the trench 103, and thus in a subsequent filling process, a hole is easily generated in the upper isolation medium 104 in the trench, which causes poor filling effect and affects the performance of the obtained semiconductor isolation structure; moreover, the effect of the recess of the sidewall of the trench caused by the inward shrinkage of the sidewall of the pad oxide layer under the hard mask layer may not be significant when the thickness of the pad oxide layer is below 100 angstroms, but the effect on the filling quality of the trench is more and more significant as the thickness of the pad oxide layer increases.
In order to solve the problem of voids existing in the isolation medium in the semiconductor isolation structure, the present embodiment provides a method for fabricating a semiconductor isolation structure. Fig. 5 is a flowchart illustrating a method for fabricating a semiconductor isolation structure according to an embodiment of the invention.
As shown in fig. 5, the method for manufacturing the semiconductor isolation structure includes:
s1: providing a semiconductor substrate, wherein a pad oxide layer and a hard mask layer are sequentially formed on the semiconductor substrate in an overlapping manner, a plurality of grooves are formed on the semiconductor substrate, the grooves penetrate through the hard mask layer and the pad oxide layer, the bottom surfaces of the grooves are located in the semiconductor substrate, and the grooves expose the hard mask layer and the side walls of the pad oxide layer;
s2: performing a pull-back process to enable the hard mask layer and the side wall of the pad oxide layer to retract inwards along the direction of expanding the groove opening;
s3: forming a first isolation medium layer on the semiconductor substrate, wherein the groove is filled with the first isolation medium layer;
s4: performing an ion implantation process to form a modified area on the upper part of the first isolation dielectric layer, wherein the depth of the modified area is more than or equal to the total thickness of the pad oxide layer and the hard mask layer;
s5: removing part of the first isolation medium layer of the modified area by using etching liquid;
s6: and forming a second isolation medium layer on the semiconductor substrate, wherein the second isolation medium layer fills the groove.
Fig. 6 to 13 are schematic cross-sectional views illustrating steps of a method for fabricating a semiconductor isolation structure according to an embodiment of the invention.
As shown in fig. 6, a pad oxide layer 201 and a hard mask layer 202 are sequentially formed on the semiconductor substrate 200 in an overlapping manner, a plurality of trenches 203 are further formed on the semiconductor substrate 200, the trenches 203 penetrate through the hard mask layer 202 and the pad oxide layer 201, the bottom surfaces of the trenches are located in the semiconductor substrate 200, and the trenches 203 expose the hard mask layer 202 and the sidewalls of the pad oxide layer 201.
Specifically, the sub-step of S1 may include: sequentially forming a pad oxide layer 201 and a hard mask layer on the semiconductor substrate 200 in an overlapping manner; forming a graphical photoresist layer on the hard mask layer, and etching the hard mask layer by taking the graphical photoresist layer as a mask to obtain a graphical hard mask layer 202; and continuously etching the pad oxide layer 201 and the semiconductor substrate 200 downwards by using the patterned hard mask layer 202 as a mask, wherein the etching is stopped in the semiconductor substrate 200 to form a plurality of grooves 203.
The semiconductor substrate 200 may be a silicon substrate. But not limited thereto, the semiconductor substrate may also be a Germanium substrate, a Silicon On Insulator (SOI), a Germanium On Insulator (GOI), or the like, and a certain doping particle may be implanted into the semiconductor substrate according to design requirements to change electrical parameters.
The opening width of the trench 203 may be equal to the width of the bottom surface thereof, i.e., the longitudinal sectional shape of the trench 203 may be rectangular. In another embodiment, the width of the opening of the trench may be greater than the width of the bottom surface thereof, that is, the longitudinal cross-sectional shape of the trench may be an inverted trapezoid.
In this embodiment, the hard mask layer 202 may include silicon nitride. For example, the hard mask layer 202 may be a single silicon nitride layer or an ONO structure. The pad oxide layer 201 may be silicon oxide. The thickness of the pad oxide layer 201 may be 900 to 1100 angstroms, for example, 1000 angstroms.
As shown in fig. 7, a pull-back process is performed to retract the sidewalls of the hard mask layer 202 and the pad oxide layer 201 in a direction to enlarge the opening of the trench 203.
Specifically, the pulling back process may include: performing a first pull-back process to retract the sidewall of the hard mask layer 202 in a direction of enlarging the opening of the trench 203; a second pull-back process is performed to shrink the sidewall of the pad oxide layer 201 in a direction to enlarge the opening of the trench 203. The first pull-back process and the second pull-back process can both adopt wet etching processes. The etching solution used in the first pullback process may include phosphoric acid (H)3PO4). Etching adopted by the second pull-back processThe liquid may include hydrofluoric acid (HF).
As shown in fig. 8, after the performing of the pull-back process and before forming the first isolation dielectric layer, the manufacturing method may further include: depositing and forming a repair layer 204 on the semiconductor substrate 200, wherein the repair layer 204 covers the hard mask layer 202 and the inner surface of the groove 203; and depositing a protective layer 205 on the semiconductor substrate 200, wherein the protective layer 205 covers the repair layer 204 (i.e., the protective layer covers the inner surface of the trench) and does not fill the trench, and the protective layer 204 protects the semiconductor substrate when the ion implantation process is performed. The repair layer 204 may be a silicon oxide layer. The protective layer 205 may be a silicon nitride layer.
As shown in fig. 9, after the protective layer 205 is formed, a first isolation dielectric layer 206 is formed on the semiconductor substrate 200, and the trench 203 is filled with the first isolation dielectric layer 206.
The first isolation dielectric layer 206 may comprise silicon oxide. The first isolation dielectric layer 206 may be formed using a high aspect ratio deposition (HARP) process. But not limited thereto, the first isolation dielectric layer may also be formed using other deposition processes known in the art.
Since the sidewall of the pad oxide layer 201 is easily retracted to the lower side of the hard mask layer 202 after the pull-back process is performed, the sidewall of the trench is recessed, and since the pad oxide layer 201 is thicker, a hole is easily formed in the upper portion of the first isolation dielectric layer 206 filled in the trench 203. In order to avoid the influence of the hole on the subsequently obtained semiconductor isolation structure, subsequent processes such as planarization, ion implantation and the like are performed after the first isolation dielectric layer 206 is formed.
As shown in fig. 10, after the first isolation dielectric layer 206 is formed and before the ion implantation process is performed, the manufacturing method may further include: and performing a planarization process to remove a part of the thickness of the first isolation dielectric layer 206, so that the upper surface of the first isolation dielectric layer 206 is flush with the upper surface of the protection layer 205. Here, the leveling refers to controlling the height difference between the upper surface of the first isolation dielectric layer 206 and the upper surface of the protection layer 205 within a range satisfying the requirement of the planarization process. Due to the fact that the first isolation medium layer 206 with a part of thickness is removed, the implantation depth of the ion implantation process can be reduced, the control precision of the ion implantation process is improved, and the removal amount of the first isolation medium layer removed by subsequent etching liquid soaking can be reduced.
As shown in fig. 11, an ion implantation process is performed to form a modified region 206a on the first isolation dielectric layer 206, wherein the depth of the modified region 206a is greater than or equal to the total thickness of the pad oxide layer 201 and the hard mask layer 202.
Specifically, in order to avoid the implanted dopant affecting the electrical property of the isolation dielectric in the trench, the ion implantation process may implant a non-conductive dopant such as carbon (C) or germanium (Ge) into the first isolation dielectric layer 206. The ion implantation process is used for implanting dopants into the first isolation dielectric layer, so that the upper part of the first isolation dielectric layer can be loosened, the upper part (i.e. the modified region) of the first isolation dielectric layer is easier to remove than the lower part (i.e. the part not implanted with dopants) of the first isolation dielectric layer in the etching liquid soaking process, and the purpose of adjusting the etching selection ratio of the first isolation dielectric layer 206 with partial thickness can be achieved. That is, the etching selectivity of the first isolation dielectric layer of the modified region can be made larger than that of the first isolation dielectric layer at the lower part of the modified region by the ion implantation process. In the ion implantation process, the protection layer 205 may prevent the repair layer 204, the pad oxide layer 201, and the semiconductor substrate 200 from being affected by ion implantation.
The energy adopted by the ion implantation process can be 290KV to 310KV, for example 300KV, and the implantation dosage of the dopant can be 2e14 atoms/square centimeter to 3e14 atoms/square centimeter. The modified region 206a in the trench may have a depth of 150nm to 190nm, for example, 180 nm. The energy, implantation dose, etc. of the ion implantation process may be varied according to the depth of the modified region to be obtained. It is found that the position of the void defect in the first isolation dielectric layer 206 is mainly affected by the thickness of the pad oxide layer, the thickness of the hard mask layer and the depth of the trench, and generally, voids are easily generated at 1/4-1/3 of the depth of the trench, so the depth of the modified region can be set according to the thickness of the pad oxide layer, the thickness of the hard mask layer and the depth of the trench, for example, the depth of the modified region is set to be 1/3 greater than the depth of the trench.
As shown in fig. 12, a portion of the first isolation dielectric layer 206 of the modified region is removed by an etching solution. After the etching solution is soaked, the first isolation dielectric layer 206 with a part of thickness is remained, and the remained first isolation dielectric layer is filled at the bottom of the trench.
The etching liquid includes hydrofluoric acid (HF). Because the first isolation dielectric layer of the modified region 206a is relatively loose, part of the first isolation dielectric layer of the modified region 206a can be relatively easily removed and the second isolation dielectric layer 206b is retained in the etching solution soaking process. That is, the ion implantation process is used to modify the first isolation dielectric layer with a partial thickness (i.e., the upper portion), so as to improve the etching precision of removing a portion of the first isolation dielectric layer 206 by soaking, i.e., to directionally remove the first isolation dielectric layer in the modified region. During the immersion process of the etching solution, the protection layer 205 can prevent the repair layer 204 and the pad oxide layer 201 below from being etched and removed.
As shown in fig. 13, after removing a portion of the first isolation dielectric layer of the modified region by using an etching solution, a second isolation dielectric layer 207 is formed on the semiconductor substrate, and the trench 203 is filled with the second isolation dielectric layer 207.
The second isolation dielectric layer 207 may include silicon oxide. The second isolation dielectric layer 207 may be formed by a High Density Plasma (HDP) deposition process because the film formed by the HDP deposition process has a relatively high density. In another embodiment, the second isolation dielectric layer may be formed by a Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or the like.
In this embodiment, after removing a part of the first isolation dielectric layer of the modified region by using an etching solution to soak, before forming the second isolation dielectric layer, as shown in fig. 12, the manufacturing method may further include: the semiconductor substrate 200 is sprayed with an aqueous ozone solution to increase the activity of the inner surface of the trench 203.
Specifically, the ozone (O)3) The concentration of ozone in the aqueous solution may be 15ppm to 80 ppm. The flow speed of spraying the ozone water solution can be 30-60L/min. Since ozone can react with silicon on the surface of the first isolation dielectric layer 206 at the bottom of the trench to generate silicon hydroxyl (SiOH), the activity of the surface of the first isolation dielectric layer is increased, which is helpful for increasing the deposition speed of the second isolation dielectric layer 207 in the trench and improving the deposition uniformity of the second isolation dielectric layer 207, and the filling efficiency and the filling quality of the trench can be improved. Moreover, after the deposition speed of the second isolation dielectric layer in the trench is increased, the height difference of the surface of the second isolation dielectric layer 207 can be reduced, which is helpful for reducing the difficulty of subsequent planarization treatment on the second isolation dielectric layer 207.
After the second isolation dielectric layer 207 is formed by deposition, the manufacturing method may further include: and performing a chemical mechanical polishing process to remove a part of the thickness of the second isolation dielectric layer 207, so that the upper surface of the second isolation dielectric layer 207 is flush with the upper surface of the hard mask layer 202, and then removing the hard mask layer 202 to form the semiconductor isolation structure. A plurality of the semiconductor isolation structures define a plurality of active regions (AA) on a semiconductor substrate.
In the method for manufacturing the semiconductor isolation structure of this embodiment, after depositing and forming the first isolation dielectric layer 206 on the semiconductor substrate 200, an ion implantation process is performed to form a modified region 206a on the upper portion of the first isolation dielectric layer 206, the depth of the modified region 206a is greater than or equal to the total thickness of the pad oxide layer 201 and the hard mask layer 202, the first isolation dielectric layer of the modified region 206a is relatively loose, when the semiconductor substrate 200 is immersed in an etching solution, a portion of the first isolation dielectric layer of the modified region 206a can be rapidly removed, and when a hole exists in the first isolation dielectric layer 206, a portion of the first isolation dielectric layer 206 near the hole is more easily removed, the hole can be opened or even removed, and the portion of the first isolation dielectric layer below the modified region 206a is not easily eroded, and then the second isolation dielectric layer 207 is formed on the semiconductor substrate 200, the second isolation dielectric layer 207 fills the trench 203, which is beneficial to reducing holes in the isolation dielectric in the trench, improving the filling quality of the trench, and improving the performance of the semiconductor isolation structure. In addition, in the process of removing part of the first isolation dielectric layer of the modified region 206a by using etching liquid immersion, the etching selection ratio of the first isolation dielectric layer of the modified region is greater than that of the first isolation dielectric layer below the modified region, so that the first isolation dielectric layer below the modified region can be reserved, the filling depth of the subsequent second isolation dielectric layer 207 can be reduced, the filling difficulty of the trench can be reduced, and the filling efficiency and the filling quality of the trench can be improved.
Further, after the performing of the pull-back process and before the depositing of the first isolation dielectric layer 206, the manufacturing method may further include: depositing and forming a repair layer 204 on the semiconductor substrate 200, wherein the repair layer 204 covers the hard mask layer 202 and the inner surface of the groove 203; and depositing a protective layer 205 on the repair layer 204, wherein the protective layer 205 covers the repair layer 204 and does not fill the trench 203. The crystal lattices on the surface of the semiconductor substrate on the side surfaces and the bottom surfaces of the groove 203 are easily damaged when the groove is formed, the repairing layer 204 can repair the crystal lattice structure on the surface of the semiconductor substrate exposed out of the groove, and the repairing layer 204 can also cover the sharp corner of the semiconductor substrate exposed out after the pull-back process, so that the sharp corner becomes smooth, the point discharge effect of the sharp corner is relieved, and the performance of a semiconductor isolation structure is improved. When the ion implantation process is performed, the protective layer 205 may protect the repair layer 204, the pad oxide layer 201, and the semiconductor substrate 200 from the ion implantation; in the process of removing part of the first isolation dielectric layer of the modified region by using etching liquid soaking, the protective layer 205 can prevent the repair layer 204 and the pad oxide layer 201 from being etched and removed; the protective layer 205 can also prevent oxygen in the isolation medium from diffusing to the surface of the active region adjacent to the trench, thereby avoiding the problem of active region shrinkage caused by further oxidizing the active region by oxygen in the isolation medium; meanwhile, the protective layer 205 can also prevent ions in the active region from diffusing into the isolation medium to affect the performance of the semiconductor isolation structure. Moreover, after the pull-back process is performed, the sidewall of the pad oxide layer 201 is easily retracted to the lower side of the hard mask layer 202, so that the sidewall of the trench 203 generates a step-shaped recess, and the repair layer 204 and the protection layer 205 can also fill the recess, which is beneficial to optimizing the sidewall morphology of the trench and reducing the filling difficulty of the trench.
The embodiment also provides a semiconductor isolation structure, which can be manufactured by the manufacturing method. As shown in fig. 13, the semiconductor isolation structure includes:
a trench 203 formed on the semiconductor substrate 200, wherein a bottom surface of the trench 203 is located in the semiconductor substrate 200, and the trench 203 exposes a sidewall of the pad oxide layer 201 on the surface of the semiconductor substrate 200;
a first isolation dielectric layer 206 filled at the bottom of the trench 203 and not filling the trench 203; and
and a second isolation dielectric layer 207 covering the first isolation dielectric layer 206 and filling the trench 203.
In this embodiment, the semiconductor isolation structure may further include a repair layer 204 and a protection layer 205. The repair layer 204 covers the inner surface of the trench 203, and is used for repairing the lattice structure of the surface of the semiconductor substrate 200 exposed by the trench 203. The protective layer 205 covers the repair layer 204 and does not fill the trench 203, and the first isolation dielectric layer 206 is located on the protective layer 205. The repair layer 204 may be a silicon oxide layer. The protective layer 205 may be a silicon nitride layer.
The manufacturing method can improve the filling quality of the groove, so that the semiconductor isolation structure has better quality and higher reliability, and is beneficial to improving the performance of a semiconductor device adopting the semiconductor isolation structure.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.
Claims (7)
1. A method for manufacturing a semiconductor isolation structure is characterized by comprising the following steps:
providing a semiconductor substrate, wherein a pad oxide layer and a hard mask layer are sequentially formed on the semiconductor substrate in an overlapping manner, a plurality of grooves are formed on the semiconductor substrate, the grooves penetrate through the hard mask layer and the pad oxide layer, the bottom surfaces of the grooves are located in the semiconductor substrate, and the grooves expose the hard mask layer and the side walls of the pad oxide layer;
performing a pull-back process to enable the hard mask layer and the side wall of the pad oxide layer to retract inwards along the direction of expanding the groove opening;
forming a silicon oxide layer on the semiconductor substrate as a repairing layer, wherein the repairing layer covers the hard mask layer and the inner surface of the groove;
forming a silicon nitride layer on the semiconductor substrate as a protective layer, wherein the protective layer covers the repairing layer and does not fill the groove, and the protective layer protects the semiconductor substrate when a subsequent ion implantation process is performed;
forming a first isolation medium layer on the semiconductor substrate, wherein the groove is filled with the first isolation medium layer;
performing a planarization process, and removing part of the thickness of the first isolation medium layer to enable the upper surface of the first isolation medium layer to be flush with the upper surface of the protective layer;
performing an ion implantation process to form a modified area on the upper part of the first isolation dielectric layer, wherein the depth of the modified area is more than or equal to the total thickness of the pad oxide layer and the hard mask layer;
removing part of the first isolation medium layer of the modified area by using etching liquid; and
and forming a second isolation medium layer on the semiconductor substrate, wherein the second isolation medium layer fills the groove.
2. The method of claim 1, wherein the modified region has a depth of 150nm to 190 nm.
3. The method of claim 1, wherein the first and second isolation dielectric layers are silicon oxide.
4. The method for fabricating a semiconductor isolation structure according to claim 3, wherein after removing a portion of the first isolation dielectric layer in the modified region by soaking in an etching solution, and before forming the second isolation dielectric layer, the method further comprises:
and spraying the semiconductor substrate with ozone water solution.
5. The method of claim 1, wherein the dopant implanted into the first isolation dielectric layer by the ion implantation process is carbon or germanium; the energy adopted by the ion implantation process is 290 KV-310 KV, and the implantation dosage of the dopant is 2e14 atoms/square centimeter-3 e14 atoms/square centimeter.
6. The method of fabricating a semiconductor isolation structure according to claim 1, wherein said etching solution comprises hydrofluoric acid.
7. The method of claim 1, wherein the pad oxide layer has a thickness of 900-1100 angstroms.
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| CN110137132A (en) * | 2019-05-09 | 2019-08-16 | 德淮半导体有限公司 | Forming method, the chemical vapor deposition process of groove isolation construction |
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| CN110137132A (en) * | 2019-05-09 | 2019-08-16 | 德淮半导体有限公司 | Forming method, the chemical vapor deposition process of groove isolation construction |
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