JPS63306639A - Master slice type semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve the utilization factor of basic cells when a logic unit cell, a RAM and a ROM are constituted respectively by a method wherein the basic cell is composed of a CMOS forming part and an NMOS forming part. CONSTITUTION:A basic cell is composed of a CMOS forming part 10a and an NMOS forming part 10b. The CMOS forming part 10a is composed of gate electrodes 11 and 12 shown by frosted parts in the figure, a PMOS part 13 and an NMOS part 14. The PMOS part 13 is composed of P-type parts 13a and 13b and a P-type part 13c. The NMOS part 14 is composed of N-type part 14a and 14b and an N-type part 14c. The NMOS forming part 10b is composed of gate electrodes 15 and 16 shown by frosted parts in the figure and NMOS parts 17 and 18. With this constitution, when a logic unit is constituted by the CMOS forming parts 10a, the NMOS forming parts 10b can be utilized as wiring channels. Therefore, the utilization factor of the basic cells when the logic unit cell, a RAM and a ROM are formed respectively can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention is a master slice type semiconductor integrated circuit, and a logic unit cell is formed by configuring a basic cell with a CMOS forming part and an NMOS forming part.

To improve the utilization efficiency of basic cells when configuring each of RAM and ROM.

[Industrial application field]

The present invention relates to a master slice type semiconductor integrated circuit, and more particularly to a master slice type semiconductor integrated circuit with gates all over.

In general, a master slice type semiconductor integrated circuit has a plurality of basic cell rows arranged in the center of the chip, excluding the input/output cell area, with wiring channels in between.

Recent master slice type semiconductor integrated circuits (sea of gates) (hereinafter referred to as rsOGJ) have basic cells spread over the entire center of the chip except for the input/output cell area, and each logic connit cell and wiring channel is covered with the above-mentioned basic cells. Configure on the cell.

In the above SOG, the wiring channel can be minimized, so the number of gates that can be integrated is increased. As the degree of integration increases in this way, in addition to logic conit cells, RAM,
Generally, the circuit configuration includes ROM, etc., and SO
The basic cells of G include RAM and ROM in addition to logic unit cells.
There is a demand for a structure that is easy to configure.

[Conventional technology]

In a conventional SOG, a basic cell is formed based on a complementary MOS (0MO3) for configuring a logic unit cell.

In other words, the basic cell is N channel MO8 (NMO″S)
The same number of transistors and P-channel MO8 (PMO8) transistors are provided.

[Problem that the invention seeks to solve]

However, static RAM is NM as shown in Figure 9.
OS transistor N1. N2 and PMOS transistor P
1. P2 constitute a latch circuit, and NMOS transistors N3. N4 constitutes a transmission gate. In this way, static RAM does not have the same number of NMOS transistors and PMOS transistors, so
It is inefficient to configure it with conventional SOG basic cells.

In addition, in ROM, NMOS is usually used in consideration of read speed.
Generally, it is constructed with only transistors, and in this case, only half of the NMOS transistors in the basic cell of a conventional SOG can be used, resulting in a problem of poor efficiency.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a master slice type semiconductor integrated circuit in which basic cells are used efficiently when configuring each of a logic unit cell, RAM, and ROM.

[Means for solving problems]

In the master slice type semiconductor integrated circuit of the present invention, a basic cell is formed into a complementary MOS transistor using the same number of P-channel MoS transistors and N-channel MOS transistors.
A CMOS forming part (10a, 20a) for forming a CMOS forming part (10a, 20a) and an NMO3 forming part (10b) for forming a plurality of N-channel MOS transistors provided at one or both longitudinal ends of the CMO3 forming part (10a, 20a) .

2'Ob, 20c).

[Effect]

In the present invention, the basic cell is the CMO3 forming part (10a
, 20a) and an NMOS forming part (10b).

20b, 20c), therefore, when forming a CMOS forming part (10a, 20a)'r-logic unit cell, an NMOS forming part (10b.

20b, 20c) can be used as wiring channels, the RAM cell is composed of the entire basic cell, and the ROM is composed of the C
Of the MOS forming parts (10a, 20a), 3 parts of NMO (1
4) and N~103 forming part (10b).

20b, 20C), and the basic cell usage efficiency is high in all cases.

(Embodiment) FIG. 1(A) shows an overall diagram of an embodiment of the master slice type semiconductor integrated circuit of the present invention.
A plurality of input/output cells 2 are provided at the periphery of the semiconductor chip 1, and basic cells 10 are arranged in the center of the semiconductor chip 1.

FIGS. 1B and 1C show a plan view and an enlarged view of an embodiment of the basic cell 10, respectively. This figure 1 (B) and (C) are
It shows a state where no aluminum wiring is formed, a so-called mask. In master slicing, a mask with gate electrodes formed in advance is prepared, and aluminum wiring is applied to the upper layer according to the user's requests.

In FIGS. 1(B) and 1(C), the basic cell 10 is a CM
It consists of an OS forming section 10a and an NMOS forming section 10b.

The CMOS forming portion 10a has a gate electrode 11.1 shown in matte finish.
2, 8 PMO sections 13, and 14 NMOS sections. PMO8 part 13 has P type parts 13a, 13b and P
Two PMs that are similar to the mold part 13C and are common to the P-type part 13c
An OS transistor is formed. NMOS part 14 part 4
Consisting of parts 14a and 14b and an N-type part 14c, the N-type part 1
Two NMOS transistors common to 4c are formed.

Note that the wide portions 11a and 12a of the gate electrodes 11 and 12 are for connecting wiring formed in the upper layer at the slicing stage.

The NMOS forming portion 10b has a gate electrode 15.1 shown in matte finish.
6 and NMOS sections 17 and 18. N.M.
OS parts L7 and 18 are N-type parts 17a, 18a, and 17b, respectively.
, 18b and N-type part 17C118C, each NMO
Two NMo5 common to the N-type parts 17G and 18a in the S part, respectively.
A transistor is formed.

The gate electrodes 11, 12, 15, and 16 are each made of polysilicon and are integral.

Also, FIGS. 2(A), (B), (C), and (D).

(E) The dashed-dotted lines HA and JIB in FIG. 1(C), respectively.

Cross-sectional views along UC, I[D, and ICE are shown. The gate insulating film is omitted in each of FIGS. 2(A) to 2(E).

The width of the N-type part 17c in the direction of arrow Y is twice that of the N-type part 18c, so that two connection parts can be formed in each of the directions of arrows X and Y. Here, the NMOS section 18 and the CMOS forming section 10a
If it is necessary to connect the NMOS part 17 and the CMOS forming part 10a with the second layer aluminum wiring, and if you try to connect the N type part 17c to the second layer aluminum wiring, A first connecting portion that connects the N-type portion 17c to the first layer aluminum wiring, and an eleventh! A second connection portion is required to connect the aluminum wiring to the second layer aluminum wiring. In this case, 1. When the second connection parts are arranged in the direction of the arrow Y, other wiring such as a bit line can be passed over the remaining connection parts arranged in the direction of the arrow X. In other words, N.M.
There is no need to increase the width of the O3 portion 17 in the direction of the arrow X, and the width of the entire basic cell 10 in the direction of the arrow X can be reduced.

Each of the gate electrodes 15 and 16 is composed of a common electrode integrated with the gate of the NMOS formation part 10b of the basic cell adjacent to the left in the direction of the arrow X, and has wide parts 15a and 1 for wiring electrodes.
6a is provided. These two adjacent NMO3 forming portions 10b are shifted in the direction of the arrow Y and are point symmetrical with respect to a point on the boundary between them.

Furthermore, the CMOS forming section 10a and the CMOS forming section 10a of the basic cell adjacent thereto on the right in the direction of the arrow X are line symmetrical with respect to the boundary line between the two.

In this way, a plurality of basic cells 10 are lined up in the directions of arrows X and Y over the entire surface of the central part of the chip excluding the input/output cell area, as shown in FIG. 1(A).

Also, a portion 1 between adjacent basic cells 10 in the direction of arrow Y
9a and the NMOS of the basic cell 10 adjacent in the arrow X direction
A portion 19b between the forming portions 10b is a substrate contact installation portion.

In addition, in the enlarged view of the basic cell 10 shown in FIG. 1(C), the inside of the mouth shows a position where aluminum wiring can be connected.

Further, FIGS. 3(A) and 3(B) each show an equivalent circuit diagram of a basic cell corresponding to FIG. 1(C). Figure 3 (A) is a commercial
An equivalent circuit of the OS forming section 10a is shown, in which transistors Tr+ and Trz are each NMOS transistors mounted on the NMOS section 14, and transistors Tr3. T
Each of r4 is a PMOS transistor composed of a PMO8 section 13.

FIG. 3(B) shows an equivalent circuit of a pair of adjacent NMOS forming portions 10b.
rs, Trn, and TrI2 are each NMOS transistors constituted by the NMOS section 18, and the transistor T
r7. Trs and Trs.

Each of T r +e is an NMO composed of an NMOS section 17.
It is an S transistor.

Here, in FIG. 4(A), one row of basic cells 3 in the direction of arrow Y is shown.
0.31.32.33 is shown. In each of the basic cells 30 to 32, A and 8 are P of the CMOS forming portion 10a in FIG.
MO8 section 13, NMOS section 14 all 14, C indicates NMOS forming section 10b.

When configuring a 0MO8 logic unit cell using the above basic cells 30 to 33, as shown in FIG. 4(B),
Logic unit cells 34a and 34 are provided in CMOS forming portions A and B.
b is formed, and the NMOS forming portion C is a wiring channel 35a.
, 35b.

In addition, when configuring a RAM, as shown in FIG.
d are formed.

Further, when configuring a ROM, ROM sections 37a to 37d having a plurality of cells are formed in each of the NMOS section B and the NMOS forming section C, as shown in FIG. 4(D). CMOS section A is not used.

Note that there is no need to provide a wiring channel when configuring the RAM and ROM shown in FIGS. 4(C) and 4(D), respectively.

FIGS. 5(A) and 5(B) each show a wiring diagram and two circuit diagrams of a one-bottom RAM cell using the basic cell of the circuit of the present invention.

Note that in FIG. 5(A), the gate electrode is omitted for convenience, and the wiring connection positions correspond to the marks in FIG. 1(C). The same applies to each of FIG. 6(A) and FIG. 7(A), which will be described later.

Here, in the wiring diagram, the shaded area indicates the first layer aluminum wiring, and the shaded area indicates the second layer aluminum wiring.

The P type part 13C and the N type part 14c of the PMO8 part 13 and the NMOS part 14 shown in FIG. 5(A) are connected to the connecting parts C11 and CI.
The latch circuit LAT shown in FIG. 5B (PMO8 transistors 9P+, P
2 and CFNMOS transistors N+ and N2) are driven.

Each of the NMOS portions 17 and 18 of the NMOS forming portion 10b is connected to a transmission gate N3. transmission gates N3 and N4, and the gates of transmission gates N3 and N4 are the fifth transmission gate.
The N-type portions 17a are connected to the word line WL1 at the connection portion C1 shown in FIG.

17b, 18a, 18b are connected to the bit lines XBL3, BL3 at connection parts C2, C3, respectively, and the respective N-type parts 17c
, 18c are connected to the latch circuit LAT through connections C4 and C5.

In this way, all the basic cells 10 are used to form a 1-vote static RAM cell for 1 bit.

FIGS. 6A and 6B each show a circuit diagram of a two-bot RAM cell using the basic hill of the present invention.

In the same figure, the difference from FIGS. 5(A) and (B) is 2.
Book word line WL1. 4 pieces with WL2.1 bits (D
Bit line BL3. XBL3. B10°XBL4 is provided, and a transmission gate N3. The gates of N4 are commonly connected to the word line WLI at the connection C1, and the gates of the respective N-type parts 18b, 17
b is the bit line 813.b at the connection part 06, C7. XBL3, and transmission gate N5. The gates of each N6 are commonly connected to the word line WL2 at a connection C8, and the respective N type portions 188.17a are connected to the connection C9 and C10.
It is connected to bit 111BL4 and XBL4 respectively.

In this way, all the basic cells 10 are used to form a two-vote static RAM cell for one bit.

　　.

FIGS. 7(A) and (B) show RO using the basic cell of the present invention.
Wiring diagram 1 shows the circuit diagram of M.

In the figure, NMOS transistors N10. I'JMO3t-run raster N12.N11 and NMO3 part 17.18 formed. N13
Each source (that is, N type part 14C1170, 18G)
are commonly connected to the power supply Vss at connection parts C20 to C24. In addition, the P-type parts 13a and 13b of the PMO8 part 13
, 13G are connected to the power supply Voo to prevent the PMOS transistor from operating.

In addition, the word line WLI has connection parts C25 to C27 connected to NM.
o5 transistor N10. The gates of N12 and NMO are connected to the word line WL2 at connection parts C28 to C30.
S transistor N11. The gate of N13 is connected. These NMOS transistors N10. N11 and N12. N13 respective drains (that is, N-type part 14a,
14b.

17a, 17b, 18a, 18b) (○ in Figure 7 (B)
) is connected to the bit line BL4. Programming is performed depending on whether or not to connect to each BL3.

That is, this ROM is a programmable ROM.

In this way, when configuring a logic unit cell, the unnecessary NMOS forming part 10b of the basic cell 10 can be used as a wiring channel, and when configuring a RAM, the basic cell 1
0 can be used 100% without any unnecessary parts, and when configuring a ROM, most parts can be used except for the PMO 8 part 13 of the basic cell 10, and the usage efficiency is good in all cases.

FIGS. 7A and 7B show a plan view and an enlarged view of a modified example of the basic cell of the circuit of the present invention, respectively.

In the figure, 20 is a basic cell, and the CMO3 forming part 20a
and NMOS forming portions 20b and 20C. CMOS
The forming section 20a has the same configuration as the CMOS forming section 10a shown in FIG. In addition, in FIG. 7(B), the inside of the mouth indicates a position where wiring can be connected.

The NMOS forming portions 20b and 20c arranged on the left and right sides of the CMOS forming portion 20a in the direction of arrow Y are obtained by dividing the NMOS forming portion 10b in FIG.
0b is the gate 21 and NMOS section 22.23 shown in matte finish.
The NMOS forming portion 20c is made up of a gate 24 and NMOS portions 25 and 26 shown in matte finish.

Further, the NMOS forming portion 20b is adjacent to the left side in the direction of arrow X.
The gates 21 and 24 are formed of an integrated common electrode.

Similar to the basic cell 10, such a basic cell 20 can also efficiently constitute a logic unit cell, a RAM cell, and a ROM.

〔Effect of the invention〕

As described above, according to the master slice type semiconductor integrated circuit of the present invention, the basic cells are used efficiently when configuring each of the logic unit cell, RAM cell, and ROM, and there are almost no wasted parts, and the circuit This improves the degree of integration and is extremely useful in practice.

[Brief explanation of drawings]

FIG. 1 is an overall view and a plan view of a basic cell of an embodiment of a master slice type semiconductor integrated circuit according to the present invention. An enlarged view, FIG. 2 is a sectional view of each part of FIG. 1 (C), FIG. 3 is an equivalent circuit diagram corresponding to FIG. 1 (C), and FIG. 4 is a usage state of the basic hill of the circuit of the invention. A diagram for explanation, FIG. 5 shows a one-bot RAM using the basic cell of the circuit of the present invention.
6 is a wiring diagram 9 circuit diagram of an embodiment of the cell, FIG. 6 is a wiring diagram 0 circuit diagram of an embodiment of a 2-bot RAM cell using the basic cell of the present invention, and FIG. 7 is a circuit diagram of the basic cell of the present invention. FIG. 8 is a plan view of a modification of the basic cell of the circuit of the present invention, and FIG. 9 is a circuit diagram of an example of a one-bottom RAM. In the figure, 10.20 is a basic cell, 10a, 20aG, tCMO3 formation part, 10b, 20b
is the NMOS formation part, 11.12.15.16.21.24 is the gate electrode, 13 is the PMO8 part, 14.17.18.22.23.25.26 is the NMOS
34a and 34b are logic unit cells, 35a and 35b are wiring channels, 36a to 36d are RAM cells, and 37a to 37d are ROM units. X (A) Wood shavings (ear nomastasura combinated - Kyomasho Sho's stacked eyes d8 Figure 1 (〒1) Guide (B) $100 4 (e) + 1 A
Diagram -) 1 Figure 3 By state of invention 3B/) Figure 4 for explaining the 4 Tenmu

Claims (4)

[Claims] (1) In a gate-covered master slice type semiconductor integrated circuit in which multiple basic cells are spread over the entire surface of the chip except for the input/output cell area, the basic cells are formed into a complementary MOS using the same number of P-channel MOS transistors and N-channel MOS transistors. A CMOS forming section (10a,
20a) and an NMOS forming part (10a, 20a) for forming a plurality of N-channel MOS transistors provided at one or both longitudinal ends of the CMOS forming part (10a, 20a).
10b, 20b, 20c). (2) The master slice according to claim 1, wherein the gates of the plurality of N-channel MOS transistors formed in the NMOS forming section (10b, 20b, 20c) are formed by an integrated common electrode. type semiconductor integrated circuit. (3) Some of the N-channel MOS transistors formed in the NMOS forming portion (10b, 20b, 20c) are made wider in the direction perpendicular to the longitudinal direction than the other N-channel MOS transistors. A master slice type semiconductor integrated circuit according to claim 1. (4) NMOS forming portions (10b, 2
2. The master slice type semiconductor integrated circuit according to claim 1, wherein the patterns 0b, 30b) are point-symmetrical patterns.