JPH07183474A - Gate array semiconductor device - Google Patents

Abstract

PURPOSE:To restrain increase of a circuit area small and to enable easy inversion of latch data of all the memory cells in a memory circuit of a gate array semiconductor device. CONSTITUTION:A resistance element 13 is built in between an outside power supply terminal 11 and a latch part power supply terminal 12 every seven columns. Driving ability of 'H' output of an inverter 4 of a latch 7 part 3 of all the memory cells 2 becomes small due to a resistance element 13 and latch data inversion by a bit line driver 9 can be made easy.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate array semiconductor device, and more particularly to a gate array semiconductor device having a basic memory cell composed of basic cells.

[0002]

2. Description of the Related Art Referring to FIG. 7 showing the structure of a prior art gate array semiconductor device, a first conventional gate array semiconductor device of this type includes a latch portion 7 of a memory cell 703.
No. 04 P-channel transistor 727 is serially connected in two or more stages, and the latch unit 704 has a high level (hereinafter “H”).
The writing capability of the bit line 708 is reduced by the driver 713 of the bit line 708. For example, "H" data is held in the memory cell 703, and then low-level (hereinafter "L") data is stored in the bit lines 708 and 70.
When writing to the latch unit 704 of the memory cell 703 from each of the memory cell 703, the bit line driver 713 and the N-channel transfer transistor 7 of the write enable WE.
As compared with the drive capability of inverting the latch data of 12 from “H” to “L”, the drive capability of “H” of each of the inverters 705 and 706 of the latch unit 704 of the memory cell 703 is reduced, and the inversion of the latch data is easy I was doing.

A memory cell 80 having a read-only inverter 826 and an N-channel transistor 825 is also provided.
Referring to FIG. 8 showing a part of the circuit diagram of the gate array semiconductor device having the 2-port RAM configuration of the second conventional example in the case of No. 3, the second conventional gate array semiconductor device has the inverter of the latch unit 804. In order to reduce the “H” output drive capability of the P-channel transistors 805 and 806, the P-channel transistors 827 of the inverters 805 and 806 of the latch unit 804 of each memory cell 803 are serially connected in two stages.

[0004]

However, in the conventional gate array semiconductor device, the P-channel transistors of the inverters of the memory cell latch section are vertically stacked in two stages in order to facilitate the inversion of the latch data. A large number of P-channel transistors are required for each cell, resulting in a large memory circuit area.

[0005]

SUMMARY OF THE INVENTION A gate array semiconductor device of the present invention comprises a plurality of basic cells that perform desired logic operations by connecting a plurality of complementary insulation effect transistor elements in a predetermined wiring and a plurality of the basic cells. An input / output for receiving an output signal of each of the block cell and the basic cell and the block cell that performs a desired logical function operation as an external signal or receiving an external signal to each of the basic cell and the block cell In a gate array semiconductor device in which circuit cells are arranged on one main surface of a semiconductor substrate, the first and second gate array semiconductor devices are arranged in an array in each of a row direction and a column direction and are formed of the complementary insulation effect transistor elements. An inverter circuit is provided, and the output of the first inverter circuit is connected to the input of the second inverter circuit. A plurality of basic memory cells that perform memory operation by connecting the output of the second inverter circuit to the input of the first inverter circuit, and a plurality of bit lines that commonly connect these basic memory cells for each column. A memory cell array block including a plurality of word lines that are commonly connected to each pair and each of the rows, and supply voltage to the basic memory cell is supplied to the basic memory cell for each column of the memory cell array block by a power supply voltage of the gate array semiconductor device. This is a configuration having a step-down circuit that steps down to a lower voltage.

Further, the step-down circuit of the gate array semiconductor device of the present invention may have a resistance element between the voltage supply terminal to the basic memory cell and the power supply terminal of the gate array semiconductor device. it can.

Furthermore, the complementary insulation effect transistor elements of the first and second inverter circuits of the gate array semiconductor device of the present invention have P-channel MOS transistors and N-channel MOS transistors having substantially the same on-current. It can also consist of

[0008]

The present invention will be described below with reference to the drawings.

FIG. 1 is a part of a memory circuit diagram of a gate array semiconductor device according to a first embodiment of the present invention.

The memory cell 3 of the gate array semiconductor device of this embodiment includes a latch section 4, an N-channel transfer transistor 11, bit lines 8 and 9 and a word line 1.
0, and the resistance element 1 is installed between the power supply terminal 18 of the latch section 4 of the memory cell 3 and the external power supply terminal 17 for each column 7 unit.

Further, the ON currents of the P-channel transistors of the inverter circuits 5 and 6 of the latch section 4 are set to be equal.

Next, the circuit operation according to the present invention will be described with reference to FIG.
The timing chart will be described.

FIGS. 2A to 2F are timing charts of respective nodes in the gate array semiconductor device of the first embodiment shown in FIG. 1 when writing data in the memory cell 3.

Partial view FIG. 2A is a timing chart of the WE terminal 19, and FIG. 2B is a timing chart of the bit line driver terminal 14 and the bit line 9.
FIG. 2C is a timing chart of the bit line 8,
2D is a timing chart of the accessed word line 10, FIG. 2E is a timing chart of the latch unit 16, and FIG. 2F is a timing chart of the latch unit 15. .

First, with the WE terminal 19 remaining at "H",
(See FIG. 2A) Bit line driver terminal 1 at time t1
When 4 changes from "L" to "H", the bit line 8 changes from "H" to "L", and the bit line 9 changes from "L" to "H" (FIG. 2B and FIG. 2). 2 (c)).

Next, when the word line 10 of a certain memory cell changes from "L" to "H" at time t2 (see FIG. 2D), the N-channel transfer transistor connected to the changed word line 10 is formed. 11 is turned on,
The bit line driver 13 tries to change the holding potential of each of the latch units 15 and 16. At this time, paying attention to the latch section 15, the resistance element 1 composed of the P-channel transistor 2 reduces the driving capability of the “H” output of the inverter 5 of the latch section 3, and the bit line driver 13 causes the latch section 15 to operate. This facilitates the inversion of "H" to "L". The change from "H" to "L" in the latch unit 15 causes the latch unit 16 to change from "L" to "H" (see FIGS. 2E and 2F).

Similarly, when the bit line driver terminal 14 changes from "H" to "L" at time t3 and the word line 10 changes from "L" to "H" at time t4, the bit line driver 13 latches. When it is attempted to change the holding potential of each of the sections 15 and 16, the resistance element 1 reduces the "H" output drive capability of the inverter 6, and the bit line driver 13 shifts from "H" to "L" of the latch section 16. Flipping is easy.

Next, a gate array semiconductor device according to the second embodiment of the present invention will be described.

Referring to FIG. 3 which is a circuit diagram of the gate array semiconductor device of the second embodiment, the gate array semiconductor device of this embodiment has the P-channel transistors 302 forming the resistance element 301 in three stages. As compared with the gate array semiconductor device of the first embodiment, the driving capability of the “H” output of each of the inverters 305 and 306 of the latch unit 304 becomes smaller, and the bit line driver 313.
Makes it easier to invert latch data.

Next, referring to FIG. 4, which is a circuit diagram of a memory cell in which a read-only circuit of a gate array semiconductor device of a third embodiment of the present invention is installed, the gate array of the third embodiment is shown. The memory cells of the semiconductor device include latch inverters 405 and 406, a write N-channel transfer gate 424, a read inverter 26, a read N-channel transfer gate 425, and write digit lines 421 and 22.
, A read digit line 423, a write word line 427, and a read word line 420.

In the memory cell shown in FIG. 4, since the word line and the digit line are separated by the read and write operations, there is an advantage that the 2portRAM is easy to construct and the read speed does not decrease.

FIG. 5 is a layout plan view of a part of the circuit shown in FIG.

FIG. 6 is a diagram showing a part of the circuit of the 2-port RAM when the memory cell shown in FIG. 4 is applied.

As described above, the present invention has a thickness of 0.5 μm.
When applied to a rule SOG (Sea of Gate) gate array semiconductor device, the memory circuit occupies an area of 512 words × 8b.
If it is it, the area is reduced by 8.19 mm ² .

[0025]

As described above, according to the present invention, in a memory circuit of a gate array semiconductor device, a circuit for lowering a power supply voltage of a memory cell latch unit to a voltage lower than an external power supply in a column unit or a memory latch unit in a column unit. Since a resistance element is built in between the power supply terminal of and the external power supply terminal, the increase of the area of the memory circuit is suppressed small, the drive capacity of the latch section inverter of all memory cells is reduced, and the inversion of the latch data is performed. It has the effect of facilitating.

[Brief description of drawings]

FIG. 1 is a memory circuit diagram of a gate array semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a timing chart of each node of the gate array semiconductor device shown in FIG.

FIG. 3 is a memory circuit diagram of a gate array semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a memory cell circuit diagram with a read-only circuit in a gate array semiconductor device according to a third embodiment of the present invention.

FIG. 5 is a plan view showing a layout of the memory cell shown in FIG.

6 is a memory circuit diagram of a gate array semiconductor device using the memory cell shown in FIG.

FIG. 7 is a memory circuit diagram of a first conventional gate array semiconductor device.

FIG. 8 is a memory circuit diagram of a second conventional gate array semiconductor device.

[Explanation of symbols]

1, 301, 401 resistance element 2, 302 P-channel transistor for resistance element 3, 303, 403, 703, 803 memory cell 4, 304, 404, 704, 804 latch section 5, 6, 305, 306, 405, 406, 705, 7
06, 805, 806 Latch unit inverter 7, 307, 407, 707, 807 Column block 8, 9, 308, 309, 408, 409, 708, 7
09,808,809 Bit line 10,310,410,710,810 Word line 11,311,411,711,811 N channel transfer transistor 12,312,412,712,812 WEN channel transfer transistor 13,313,413,13 713, 813 Bit line driver 14, 314, 414, 714, 814 Bit line driver terminal 15, 16, 315, 316, 415, 416, 71
5, 716, 815, 816 Latch section node 17, 317 External power supply terminal 18, 318 Latch section power supply terminal 19, 319, 419, 719, 819 WE terminal 20, 320, 420, 720, 820 Read word line 21, 22 , 321, 322, 421, 422, 82
1,822 Writing bit line 23,323,423,723,823 823 Reading bit line 24,324,424,724,824 N channel transfer transistor 25,325,425,725,825 825 reading N channel transfer transistor 26, 326, 426, 726, 826 Inverter 27, 327, 427 Write word line 727, 827 P-channel transistor

Claims (3)

[Claims] 1. A basic cell that performs a desired logic operation by connecting a plurality of complementary insulation effect transistor elements in a predetermined wiring manner, and a block cell that includes a plurality of the basic cells and performs a desired logic function operation and the basic cell. Each of the input / output circuit cells for receiving the output signals of the cells and the block cells and outputting them as external signals or for transmitting the signals to the basic cells and the block cells, respectively, on one main surface of the semiconductor substrate. In an arrayed gate array semiconductor device, the first and second inverter circuits, which are arranged in an array in the row and column directions, respectively, and which are composed of the complementary insulation effect transistor elements, are provided. Is connected to the input of the second inverter circuit and the output of the second inverter circuit is connected to the first input. A plurality of basic memory cells that are connected to the input of the burner circuit to perform a memory operation, a plurality of bit line pairs that commonly connect these basic memory cells to each column, and a plurality of words that commonly connect to each row. And a step-down circuit for stepping down the supply voltage to the basic memory cell to a voltage lower than the power supply voltage of the gate array semiconductor device for each column of the memory cell array block. Gate array semiconductor device. 2. The gate array semiconductor according to claim 1, wherein the step-down circuit has a resistance element between a voltage supply terminal to the basic memory cell and a power supply terminal of the gate array semiconductor device. apparatus. 3. The complementary insulation effect transistor element of each of the first and second inverter circuits is composed of a P-channel type MOS transistor and an N-channel type MOS transistor having substantially the same on-state current. The gate array semiconductor device according to claim 1.