JPH0387064A - Master slice type semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To automatically achieve element isolation and improve area utilizing efficiency, by arranging an MOS transistor formed in a well so as to be adjacent to a bipolar junction transistor, which well has the conductivity type opposite to the collector region of the bipolar transistor. CONSTITUTION:After a p-type and an n-type buried layers are formed on a p-type substrate 40, a p-type epitaxial layer 42 is formed. In this layer 42, n-type wells 44a, 44b, 44c are formed. The p-type epitaxial layer is left between these regions, and p-type wells are formed. The number of elements arranged in one unit is set as follows; four pairs of PMO's, four pairs of NMOS's, one pair of bipolar junction transistors BJT, and two pairs of impedance elements. Thereby the possibility that a superflous number of BJT's are formed is reduced, so than the formed elements can be used with excellent efficiency. Further, since a pair of BJT's is arranged to be adjacent, connection is facilitated. By arranging the NMOS's so as to be adjacent to the npn BJT, elements are automatically isolated, and the area of an isolation region can be reduced.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figs. 11 and 12) Problems to be solved by the invention Means for solving the problems First invention (Fig. 1) > Second invention (Fig. 2) Third invention (Fig. 3) Effect of the first invention Effect of the second invention Effect of the third invention Embodiment 1 (Fig. 4, Fig. 3) Figure 5) Second embodiment (Figures 6 to 1O) Other effects of the invention First effect of the invention Second effect of the invention Third effect of the invention [Summary] In a semi-custom type semiconductor integrated circuit device Regarding a master slice type semiconductor integrated circuit device, that is, a semiconductor integrated circuit device formed by regularly arranging certain basic cells, it is possible to reduce the number of unused elements when configuring various logic circuits, and thereby, In order to be able to increase the area utilization efficiency and improve the degree of integration, at least one of the basic cells has a first insulator of a first type in which carriers of a first conductivity type transport current. a gate field effect transistor, a second insulated gate field effect transistor of a second type in which carriers of a second conductivity type opposite in polarity to the first conductivity type transport a current; a second insulated gate field effect transistor in which carriers of a second conductivity type transport a main current; a bipolar junction transistor of the type; a third insulated gate field effect transistor of the second type in which carriers of the second conductivity type transport current; a fourth insulated gate field effect transistor of the first type in which carriers of the first conductivity type transport current; The transistors are arranged in sequence in a predetermined first direction.

[Industrial Field of Application] The present invention is applicable to semi-custom (seat-custom)
In this type of semiconductor integrated circuit device, a master slice (mast
The present invention relates to an erslice type semiconductor integrated circuit device, that is, a semiconductor integrated circuit device formed by regularly arranging certain basic cells (basic cells).

If such master slice type semiconductor integrated circuit devices are classified by device structure, (1) TTL (transistor tran)
(2) ECL (emitter-coupled)
CMOS (complementary) structure (3) CMOS (complementary)
M OS ) can be classified into those with f11 structure (4) those with BiCMO8 structure. Here, a master slice type semiconductor integrated circuit device having a BiCMO8 structure has high current drivability (high load drivability) due to bipolar technology and zero
It has the advantage of low power consumption provided by MO8 technology, and has been attracting attention as a device that can respond to larger scale and higher integration of semiconductor integrated circuit devices.

[Prior Art] Conventionally, as a master slice type semiconductor integrated circuit device having a BiCMO3 structure, FIG.
A plan view of the basic cell is shown in FIG. 2A, and a sectional view of the basic cell is shown in FIG. 12B (a sectional view taken along the line Y-Y' in FIG. 12A).

Here, in FIG. 11, 60 is a chip body, 61 is an I10 cell, and 62 is a basic cell, and this master slice type semiconductor integrated circuit device is constructed by laying basic cells 62 all over the internal area. . Such semiconductor integrated circuit devices are generally channelless master slice semiconductor integrated circuit devices or SOG (sea o
f gate) (Japanese Patent Application Laid-Open No. 63-3066
(See Publication No. 39).

Next, regarding the basic cell 62, referring to FIG. 12A,
To explain its planar structure, two p-channel MO3)
Transistors (hereinafter referred to as PMOS) 11.15 are arranged side by side with their drain regions 19a in common. Similarly, two n-channel MOS transistors (hereinafter referred to as NMO8) 12.14 are arranged side by side with a common drain region 19b.

The source regions 17a of the PMOS II 15 are arranged on opposite sides of the drain region 19a. Similarly, the source regions 17b of the NMOS 12.14 are arranged on opposite sides of the drain region 19b.

A gate electrode 18 (18-1, 18-2) is arranged between the source region and drain region of each MOS transistor. Note that the source region and drain region of each MO3) transistor are symmetrical and can be used interchangeably. Therefore, hereinafter, the source region and the train region will be collectively referred to as a source/drain region.

The configuration shown in the central part of FIG. 12A includes two PMOS II, 15, arranged side by side in this way, and two NMOS 12, 14, also arranged side by side, with PMOS 1 and NMOS 12, 12 on one side. One common gate electrode 18-1 is arranged on the PMOS 15 on the other side.
Another gate electrode 18-2 common to the NMOS 14 and the NMOS 14 is arranged. That is, these MOS transistors form a CMO3 ellipse. n on both sides of such 0MO8
pn-type bipolar junction transistor (hereinafter referred to as npnB)
Although not shown, two impedance elements are further arranged on the left and right outer sides. For example, one two-input NAND circuit can be formed using these elements.

Next, the cross-sectional structure of the basic cell 62 will be explained with reference to FIG. and PMOS11.
15, NMOS12.14, and two npnBJT1
3.16, that is, the n-type region 32b
, p-type head region 31a, p-type region 32c, and p-type head region 3
2a are formed respectively. Further, a p-type head region 39 for element isolation is provided between the n-type regions 32a and 32b. And, in the central n-well 32b, there is a PMOS
II, 15 is formed, and the p-well 31 on the right side is filled with NM.
OS12.14 is formed. Further, a p+ region 17a is formed on the surface of the n-well 32b, and an n+ region 17b is formed on the surface of the p-well 31, and a PMOS 15 and an NMOS are formed, respectively.
14 source/drain regions are configured. Further, in the outer n-type regions 32a and 32c, npnBJTs are respectively provided.
16.13 is formed. Here, the n-type region 32a is
Since it acts as a collector region of the n p n B J T 16, a p-type region 39 is required to form an element isolation region between the n-type region 32a and the n-type region 32b.

Note that the basic cell 62 shown in FIG. 12A has P in a horizontal row.
This is an example of a basic cell configured by arranging MO3, NMO3, and npnBJT, but some of them may also be arranged vertically.
Figure C shows an example of such a basic cell, in this example an arrangement of PMOSII, 15 and NMOS 12.14 and npnBJTlB, 16 and impedance elements 21.
22 are arranged separately, that is, in two rows in the horizontal direction, and this point is different from the basic cell structure shown in FIGS. 12A and 12B.

[Problems to be Solved by the Invention] By the way, in such a master slice type semiconductor integrated circuit device, when various logic circuits or functional blocks are constructed using a cell or a plurality of basic cells, n p
n B J T 13.16 refers to parts such as output buffers that require high load driving capability (for example, connecting the output terminal of a logic circuit or functional block to the input of another logic circuit or functional block via relatively long wiring). (or when connecting the output terminal of a logic circuit or functional block to the input terminals of multiple other logic circuits or functional blocks) and does not require such a part. P without using npnBJTlB,16
It is common to use only MOS II, 15, NMOS 12.14. Therefore, like the basic cell 62 shown in FIG. 12A and the basic cell shown in FIG. 12C, four MOS transistors, namely PMOS II, 15, N
2 Hp n B J T for MOS12.14
In a conventional master slice type semiconductor integrated circuit device provided with 13.16, the number of n p n B J T 13.16 is large compared to the MOS transistor.
When looking at this as a whole, there is a problem that a large number of npn BJTs remain unused, resulting in poor device usage efficiency. In other words, the area utilization efficiency of the chip was poor, which hindered the improvement of the degree of integration.

Furthermore, for example, in the case of the basic cell 62 shown in FIG.
In the case of the basic cell shown in Figure 2C, PMOS15 and n
An element isolation region (not shown) must be provided between the pnBJT 16 and this also reduces the area utilization efficiency and hinders the improvement of the degree of integration.

Furthermore, in recent years, when configuring a semiconductor integrated circuit device having a certain function using such a master slice type semiconductor integrated circuit device, it has become common to incorporate RAM or ROM. For example, when configuring a 1-boat type static RAM cell, two PMO3 and two NMOS transistors are used as MOS transistors that configure the memory element section (flip-flop, latch).
and two NMO3 are required as MOS transistors forming the transfer gate (see Figure 9B).
That is, the required numbers of PMO3 and NMO8 do not match. Therefore, such a static RAM cell is
If the basic cell 62 shown in FIG. 12A or the basic cell shown in FIG. 12C has the same number of PMO3 and NMO3, there will be a large number of unused PMO3. In this case, ROM cells are generally constructed of NMOS in order to improve read speed in the case of ROM. However, there will be a large number of unused PMOs 8.

Here, the first object of the present invention is to reduce the number of unused and remaining elements when configuring various logic circuits, thereby increasing the area utilization efficiency and improving the degree of integration. It is an object of the present invention to provide a master slice type semiconductor integrated circuit device having a BiCMO3 structure that enables the following.

A second object of the present invention is to provide not only various logic circuits but also R
It has a BiCMOS structure that reduces the number of unused elements when configuring memories such as AM and ROM, thereby increasing area utilization efficiency and improving the degree of integration. An object of the present invention is to provide a master slice type semiconductor integrated circuit device.

[Means for Solving the Problems] The above objects are distantly related to the following first, second and third inventions.

B1 of 1 According to the first aspect of the present invention, a basic cell configuration is provided that satisfies the required number of bipolar junction transistors by a plurality of basic cell configurations.

Further, a semiconductor integrated circuit device is provided that does not particularly require an element isolation region for a bipolar junction transistor. In other words, when configuring various logic circuits, BiCM can increase area utilization efficiency and improve the degree of integration.
A master slice type semiconductor integrated circuit device having an O3 structure is provided.

Fig. 1 is a diagram explaining the principle of the present invention, in which Fig. 1A is a plan view and Fig. 1B is a sectional view (a sectional view taken along the line W-W' in Fig. 1A).
It is.

In the figure, from left to right, a first type insulated gate field effect transistor (hereinafter referred to as IGFET) 1 in which carriers of the first conductivity type transport current, a transistor 1 in which carriers of the second conductivity type transport current Type 2 IGFET2. BJT
3. A second type IGFET 4 and a first type IGFET 5 are arranged.

The BJT 3 is one in which the main current is transported by a carrier of the second conductivity type, and is formed in a first conductivity type well for forming the second type IGFET 2.4 and a second conductivity type well of an opposite conductivity type. (See Figure 1B).

Preferably, as shown by broken lines in FIG.
, 2.4.5, and is formed in a vertically symmetrical configuration. On this occasion,
The number of BJT3 does not increase.

It is preferable to use the configuration shown by the solid line in FIG. 1A as a subunit, and to arrange two subunits one above the other as shown by the broken line to form one unit.

Furthermore, it is preferable to arrange a plurality of impedance elements between the subunits.

Using these configurations, various logic circuits made of CMOS and various logic circuits made of BiCMO3 can be configured.

Part 2 B 2゛Among the present invention, the second invention is directed to various logic cells, RAM,
A master slice type semiconductor integrated circuit device having a BiCMO3 structure that can improve area utilization efficiency when configuring a memory such as a ROM, and in particular, for example, a one-board static RAM.
This is a master slice type semiconductor integrated circuit device suitable for configuring a master slice type semiconductor integrated circuit device.

As shown in FIG. 2A, the principle of which is shown in FIG. IG
A first CMOS transistor section 65 consisting of one FETI and two second type IGFETs 2.2;
A second type BJT section 66 consisting of a type BJT3, two second type IGFETs 4.4 and two first type IGFETs.
5.5) transistor section 67,
The second type IGFET section 69 is composed of two second type IGFETs 68 and 68, and a basic cell is formed by sequentially arranging a second type IGFET section 69 in a predetermined first direction.

Note that it is also possible to have a configuration in which the impedance element is placed at an arbitrary position.

3.B 3゛The third aspect of the present invention is that various logic cells, RAM,
A master slice type semiconductor integrated circuit device having a BiCMO9 structure capable of improving area utilization efficiency when configuring a memory such as a ROM, in particular, for example, a two-port static RAM.
This is a master slice type semiconductor integrated circuit device that is effective when configuring cells and ROMs.

As shown in FIG. 3A, the third invention includes four second-type IGFETs 63, 63, 71, .
A third second type IGFET section 72 consisting of 71, two first type IGFETIs, and one and two second type IGFETs.
First CMO3) consisting of T2.2 - transistor section 65
and a second type BJT section 6 consisting of one second type BJT 3.
6, two second type IGFETs 4.4 and two first
A second 0M03 section 67 consisting of a type IGFET 5.5 and a fourth second type IGFET section 74 consisting of four second type IGFETs 68, 68, 73, and 73 are sequentially aligned in a predetermined first direction. It consists of a basic cell consisting of: Note that it is also possible to have a configuration in which the impedance element is placed at an arbitrary position.

[Effect] The effects of the first, second and third inventions are as follows.

As shown in Figure 1A, the relative density of BJTs can be reduced and the number of unused BJTs can be reduced by arranging four or more IGFETs for one BJT. can be reduced.

As shown in Figure 1B, the second
By arranging the type BJT, a pn junction is formed between the wells, so a special element isolation region can be omitted. Therefore, the area utilization efficiency becomes high.

By reducing the number of unnecessary JTs and reducing the area of the isolation region, the overall area utilization efficiency can be increased and the degree of integration can be improved.

According to the second invention, which involves two generations of "Mugi Iriki" type, similar to the first invention, IG
Since the number of BJTs can be reduced relative to the number of FETs, it is possible to reduce the number of unnecessary JTs, increase the overall area utilization efficiency, and improve the degree of integration. 63 and two second type IGFETs 68.6.
Since the second type 2 IGFET section 69 consisting of 8 is provided, ROM and RAM, especially one boat type that requires two type 1 IGFETs and four type 2 IGFETs, are provided. When configuring a static RAM cell, the second type IGFET 63 can be used as a transfer gate transistor.

In FIG. 2, FIG. 2B is a diagram showing the area used when configuring a 0MO3 type logic cell, for example, a 0MO3 type 2-input NAND circuit, and FIG. , A diagram showing the area used when configuring a BiCMO8 type 2-input NAND circuit and an 0MO3 type logic cell, for example, a 0MO3 type 2-input NAND circuit. FIG. 3 is a diagram showing areas used when configuring a static RAM cell. Here, the wiring area shown in FIGS. 2B and 2C indicates that the area above the second type IGFET portions 64 and 69 can be used as a wiring area. The same applies to FIGS. 3B and 3C.

Star j! According to the third invention, which requires 4 months of harvest, similar to the first invention, IG
Since the number of BJTs can be reduced relative to the number of FETs, the number of unnecessary JTs can be reduced, the overall area utilization efficiency can be increased, and the degree of integration can be improved. A first second type IGFET section 72 consisting of 71.71 and four second type IGFETs
A second type 2 IGF consisting of T68.68.73.73
Since the ET section 74 is provided, a ROM or RAM, in particular, for example, a two-boat type static RAM cell which requires two first type IGFFi, T, and six second type IGFETs is configured. In case, the second type IGFE
T63.71 can be used as a transistor for the transfer gate.

In FIG. 3, FIG. 3B shows the area used when configuring a CMOS type logic cell, for example, a 0MO3 type 2-input NAND circuit, and FIG. , A diagram showing the area used when configuring a BiCMO3 type 2-input NAND circuit and a CMOS type logic cell, for example, a 0MO3 type 2-input NAND circuit. The third diagram is a RAM cell, for example, a 2-port type static FIG. 3 is a diagram showing areas used when configuring a RAM cell.

[Embodiments] Hereinafter, embodiments of the master slice type semiconductor integrated circuit device according to the present invention will be described with reference to FIGS. 4 to 10.

1 4 5 In the first embodiment of the present invention, the fourth cell is used as the basic cell.
A basic cell is provided whose plan view is shown in FIG. A and whose sectional view is shown in FIG.

In the plan view of FIG. 4A, PMO8IA, NMOS2
A, npnBJT3A, NMOS4A, and PMO85A are arranged horizontally. Another PMO3IB is placed at the bottom in the figure, facing PMO3IA, and NM
Matched with OS2A, another NMOS 2B
is placed below. NMOS4A, PMOS5B
Also, NMOS4B and PMOS5B are arranged butt against each other. One BJT3A is placed in the center for these eight MOS) transistors.

Another set of configurations equivalent to these configurations is arranged further below. That is, a pair of PMO5IC11D,1
Pair NMOS2C12D, 1 npnBJ73B, 1
A pair of NMOS4C14D, a pair of PMOS5C15
D are arranged horizontally. That is, 8 MOS
) A transistor and one BJT constitute one subunit, and two subunits are arranged one above the other to constitute one unit. Four impedance elements 10A, 10B, l are arranged in a row in the horizontal direction between these subunits.
0C1IOD are arranged. In other words, in one unit, there are 4 pairs of PMOS, 4 pairs of NMO3, and 1 pair of B
JT, two pairs of impedance elements are arranged. In addition, NMOS2 is installed on both sides of npnBJT3・A and 3B.
Since A, 2B, 2C12D, 4A, 4B, and 4C14D are arranged, pn separation for npnBJT is automatically achieved.

Referring to the cross-sectional view of FIG. 4B, a semiconductor integrated circuit is formed on a p-type substrate 40. After forming a p-type buried region and an n-type buried region on a desired region of the p-type substrate 40, a p-type epitaxial layer 42 is formed. In the p-type epitaxial layer, n-type wells 44a, 44b, 44
c is formed.

A p-type epitaxial layer remains between each n-type region 44a, 44b, and 44c, forming a p-type well. A pair of p1 type regions 7a are formed on the surface of the n type well 44a, forming source/drain regions of a p channel MO8) transistor. Similarly, a pair of p
A + type region 7a is formed to form a PMOS. A p-wall region 50 and an n++ region 51 of the p-wall region 50 are formed on the surface of the central n-type well 44b, forming an npn bipolar junction transistor 3A. n-type well 44b
Since it is separated from the peripheral region by a pn junction, there is no need to form another isolation region.A gate electrode 8 made of polycrystalline silicon or the like is formed on the 0MO3 structure through a thin gate oxide film. -2.8-4 is formed.

The number of elements arranged in one unit is 4 pairs of 2MO8,
By using four pairs of NMOS, one pair of BJT, and two pairs of impedance elements, the possibility of forming an excessive number of BJTs is reduced, and the formed elements can be used efficiently. Since a pair of BJTs are placed adjacent to each other, connection is easy.

By arranging NMO3 adjacent to the npnBJT, element isolation is automatically achieved and the area of the isolation region can be reduced.

FIG. 5 shows an example of configuring a logic circuit using the basic units shown in FIGS. 4A and 4B.

FIG. 5 is a diagram showing a BiCMO8 type two-input NAND circuit, in which FIG. 5A is a plan view and FIG. 5B is an equivalent circuit diagram.

The configuration shown in FIG. 5 utilizes the basic cell unit configuration shown in FIGS. 4A and 4B. In other words, within the unit, there is 1
CMOS consisting of a pair of PMOS and a pair of NMO3
Four sets of structures (55A, 55B, 55C155D) are arranged in a matrix, 0MO355A, 55C and CMOS
Two BJTs 3A and 3B are arranged between 55B and 55D, and impedance elements 10A and 1 are arranged between the upper and lower CMOS.
0B, 10C1 IOD are arranged.

The elements required to configure a 2-input NAND circuit are 2
1 PMO3, 2 NMO3, 2 impedance elements, and 2 BJTs. Therefore, as for CMO3, it is sufficient to use 1/4 of the one shown. Further, as for the impedance element, it is sufficient to use the one shown in the figure 172.

Regarding the BJT, all of the ones shown are used.

That is, regarding CMO3 and impedance elements,
There are some things that are not used, but they can be used for other circuits. Indicates the position of the connection hole, ◎ mark indicates the position of the connection hole between the first and second wiring layers, and the vertical broken line indicates the power line and ground line included in the first layer wiring. Figures 6 to 10 below
The same is true in the figure. Further, within each BJT region, an emitter region 56, a base region 57, and a collector region 58 are arranged.

To explain the circuit configuration with reference to FIG. 5A, two inputs A1 and A2 are PMOS and NMO8 common gate 8-1.
．． 8-2. A pair of PMOSIAs on the left, I
B has its source/drain region 7a connected to the power supply line VDD.
The other source/drain region 9a is connected to the base region 57 of the BJT at the top in the figure via the first layer wiring and the second layer wiring. Emitter region 56 of this BJT
is connected to the collector region 58 of the lower BJT via the first layer wiring.
It is connected to the. The emitter region 56 of the lower BJT is
It is connected to the ground line ■SS via the first layer wiring. The base region 57 of the lower BJT is connected via the first layer wiring,
It is connected to one source/drain region 7b of NMOS 2A, and is also connected to the impedance element 10A. This impedance element 10A is the first layer wiring,
It is connected to the ground line vSS via the second layer wiring. NMO32A and NMOS2B are connected in series, and the other end is connected to PMOSIA, 1 through impedance element 10B.
It is connected to the intermediate connection point of B.

Furthermore, the emitter region 56 of the upper BJT and the collector region 58 of the lower BJT are commonly connected and led out to the output terminal X.

Therefore, for two inputs A1A2 as shown in FIG. 5B, N
An AND circuit is constructed and output X is provided.

2 Nos. 6 to 10) The second embodiment of the semiconductor integrated circuit device according to the present invention includes a basic cell as shown in the plan view of FIG. 6 as a basic cell, and is otherwise the same as the first embodiment. It is composed of Here, in the figure, 63A, 63B, 71A, 71B
, 68A, 68B, 73A, and 73B are NMO3.

Next, using this basic cell, we will create a 0MO8 type 2-input N
AND circuit, B iCMO3 type 2-input NAND circuit,
The case of configuring a 1-boat type static RAM cell and a 2-boat type static RAM cell will be explained.

(1) CMO3 type 2-input NAND circuit Figure 7 A and B
1 and 2 respectively show the planar configuration of the CMO9 type 2-input NAND circuit of this example and its equivalent circuit. In this example, P
MOS IA, IB and NMO32A, 2B are used.

Here, the PMOSIA, 1B has its source/drain regions 7a, 7a connected to the power supply line VDD, and its source/drain region 9a is connected to the 2nd layer via the first layer wiring 75.
It is connected to the layer wiring 76. Further, the NMOS 32A has its source/drain region 7b connected to the second layer wiring 76 via the first layer wiring 75, and the NMOS 2B has the
Its source/drain region 7b is connected to ground line VSS.

In such a two-input NAND circuit, the gate! 18-
Inputs A1 and A2 are supplied to the terminals 1 and 8-2, respectively, and an output X=A1·A2 can be obtained at the second layer wiring 76.

Now, hypothetically, PMOS5A, 5B and NMOS4A, 4
If B is used for other logic circuits and npnBJ73B is not used, npnB is not used for this part.
There is one JT for every eight MOS transistors.

(2) BiCMO8 type 2-input NAND circuit Figure 8 A and B are respectively the BiCMO8 type 2-input NAND circuit of this example.
It shows the planar configuration of the circuit and its equivalent circuit. In this example, PMOSIA, IB, NMOS2A, 2B,
Impedance elements 10A, 10B and npnBJT3
A and 3B are used.

Here, the PMOSIA, IB has its source/drain region 7a connected to the power supply line VDD, and its source/drain region 7a is connected to the power supply line VDD.
Drain region 9a is connected to first layer wiring 77, second layer wiring 78.
It is connected to the base region 57 of the npn BJT 3A via the first layer wiring 79, and also the first layer wiring 77,
Via the impedance element 10A and the first layer wiring 80,
It is connected to the second layer wiring 81.

Further, the NMOS 2A has its source/drain region 7b.
to the second layer wiring 81, n p n via the first layer wiring 82
Collector region 58 of B J T 3 B and npnB
It is connected to the emitter region 56 of JT3A. Also,
The NMOS 2B connects its source/drain region 7b to the base region 57 of the npnBJT 3b via the first layer wiring 83.
It is also connected to the ground line SS via the first layer wiring 83, the impedance element 10B, and the first layer wiring 84.

Further, the collector region 58 of n p n B J T 3 A is connected to the power supply line VDD via a first layer wiring 85 and a second layer wiring 86. Also, npnBJT3
The B emitter region 56 is connected to the ground line VSS via a first layer wiring 87.

In such a two-input NAND circuit, the gate electrode 8-
The inputs A1 and A2 are supplied to the terminals 1 and 8-2, respectively, and the output X=A1·A2 can be obtained at the second layer wiring 81.

Here are the other PMOSIA, IB, 5A of this unit
, 5B and NMOS 2A, 2B, 4A, and 4B can be used for other logic circuits, so in this case, no unnecessary npnBJT is generated for this unit portion.

(3) 1-boat type static RAM cell No. 9
Figures A and B respectively show the planar configuration of a one-boat type static RAM cell of this example and its equivalent circuit. In this example, PMOSIA, IB, and NMOS
2A, 2B, 63A, and 71A are used.

Here, the PMOSIA 1B has its source/drain region 9a connected to the power supply line VSS. Also,
PMO3IB and NMOS2B have their gate electrodes 8-2
are connected to the source/drain regions 7a of the PMOSIA and the source/drain regions 7b of the NMOS 2A via the first layer wiring 88. Further, the source/drain region 7a of the PMOS IB is connected to the source/drain region 9b of the NMOS 71A via a first layer wiring 89, a second layer wiring 90, and a first layer wiring 91. Here, N
The MOS 71A has its source/train region 7b connected to one bit line BL via a first layer wiring 92, and its gate electrode 70-1 connected to a word line WL via a first layer wiring 93. .

Further, the NMOS 2A has its gate electrode 8-1 connected to the source/drain region 9b of the NMOS 71 via a first layer wiring 94 and a second layer wiring 90. Also, NM
The OS 2B has its source/drain region 7b connected to the source/drain region 9b of the NMOS 71 via a first layer wiring 95 and a second layer wiring 90. Also, PMO
3IB, the gate electrode 8-2 of the NMo52B is connected to the source/drain region 9b of the NMOS 63A via a first layer wiring 96. Further, the source/drain regions 9b of the NMOSs 2A and 2B are connected to the ground line VSS.

Note that the NMOS 63A has its source/drain region 7
b is connected to the other bit line BL via the first layer wiring 97.

Note that, as shown by broken lines in FIG. 9B, the NMOSs 71B and 63B can be connected in parallel to the NMOSs 71A and 63A, respectively, and in this case, access speed can be increased.

(4) 2-boat type static RAM cell 1st
FIGS. 0A and 0B respectively show the planar configuration of the two-boat type static RAM cell of this example and its equivalent circuit. In this example, PMO8IA, IB, and NMO
S 2 A, 2B, 63A, 63B, 71A, and 71B are used.

In this example, the NMOS 71A has its source/drain region 7b connected to one first bit line BLI via a first layer wiring 92. Further, the NMOS 63A has its source/drain region 7b connected to the other first bit line BLL via a first layer wiring 97. Furthermore, the gate electrodes 70-1 of the NMOSs 71A and 63A are 1
It is connected to the first word line WLI via the layer wiring 93.

Further, the NMOS 71B has its source/drain region 7
b is connected to one second bit line BL2. Further, the NMOS 63B has its source/drain region 7b connected to the other second bit &1BL2. Also,
Gate voltage of NMOS71°B, 63B [70-2 is 1
It is connected to the second word line WL via a layer wiring 98.

The rest of the structure is the same as that of the static RAM cell shown in FIG. 9.

In the above-described embodiment, the present invention is applied to a so-called channel-less master slice semiconductor integrated circuit device (SO
Although the case where the present invention is applied to item G) has been described, the present invention can also be applied to a master slice type semiconductor integrated circuit device in which a channel region is provided.

Further, in the first embodiment, the case of configuring a BiCMO3 type 2-input NAND circuit was described, but other than that,
It will be obvious to those skilled in the art that various logic circuits can be constructed.

In addition, in the second embodiment, a CMOS type 2-input NA
Although we have described the case of an ND circuit, BiCMO3 type 2-input NAND circuit, 1-port type static RAM cell, and 2-port type static RAM cell, it can also be used to configure various other logic circuits, ROM cells, etc. Of course, what you can do is possible.

In addition, in the second embodiment, pMO3IA and IB are n
Although we have described the case where MO32A and 2B are placed on the left side in the diagram, instead of this, nMO32A and 2B are placed on the p
It can also be placed on the left side of MO3IA and IB in the figure. In this case, pMO3IA, 1B and npnB
Although it is necessary to form an element isolation region between JT3A and JT3A, at least the effect that a static RAM cell can be efficiently formed can be obtained. 9MO8
The same applies to the positional relationship between 5A, 5B and nMO34A, 4B.

Furthermore, it will be obvious to those skilled in the art that the first and second embodiments can be configured with all conductivity types reversed.

[Effects of the Invention] According to the present invention, the following effects can be obtained.

According to the first invention, since the B iCMO3 basic cell is constructed using a small number of BJTs and impedance elements, the number of unused elements can be reduced.

In addition, since a MOS (MOS) transistor formed in a well of a conductivity type opposite to the collector region of the BJT is placed adjacent to the BJT, element isolation is automatically distanced, increasing the area utilization efficiency and improving the degree of integration. can do.

According to the second invention, similar to the first invention, IGFET
Since the number of BJTs can be reduced relative to the number of BJTs, the number of unnecessary JTs can be reduced, increasing the overall area utilization efficiency,
The degree of integration can be improved, and the two first
A first type IGFET consisting of a type IGFET and two second type IGFETs.
(CMOS) transistor part, two second type IGs
A first second type IGFET consisting of a FET is provided, and two first type IGFETs and two second type GFEs are provided.
For the second CMOS transistor section consisting of T, 2
A second second type IGFET consisting of two second type IGFETs.
are provided, so the ROM and RAM, especially, for example, two first type IGFETs and four second type IGFETs.
It is possible to provide a master slice type semiconductor integrated circuit device having an iCMO8 structure, which is suitable for configuring a one-board type static RAM that requires.

"Scheme"! According to the third invention, similarly to the first invention, IGFET
Since the number of BJTs can be reduced relative to the number of BJTs, the number of unnecessary JTs can be reduced, increasing the overall area utilization efficiency,
The degree of integration can be improved, and the two first
A first type IGFET consisting of a type IGFET and two second type IGFETs.
CMOS) - For the transistor section, four second type I
A third type 2 IGFET consisting of a GFET is provided;
And two 1st type IGFETs and 2 2nd type ■GF
For the second CMOS) transistor section consisting of ET,
Fourth type 2 IGFET consisting of four type 2 IGFETs
Since T is provided, ROM and RAM, especially, for example, two first type IGFETs, six second type IGFETs,
2-boat type static RAM that requires T
It is possible to provide a master slice type semiconductor integrated circuit device having an iCMO3 structure, which is suitable for configuring an iCMO3 structure.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the first invention of the present invention,
Figure 1A is a plan view, Figure 1B is a sectional view (w--
w' line sectional view), FIG. 2 is a diagram illustrating the principle of the second invention of the present invention,
Figure 2A is a plan view, Figure 2B is a CMOS type logic cell,
For example, FIG. 2C is a diagram showing the area used when configuring a 2-input NAND circuit, and FIG. The second diagram shows the area used in case of 1-boat type static R.
FIG. 3 is a diagram showing the area used when configuring an AM cell, and is a diagram explaining the principle of the third invention of the present invention, and FIG.
is a plan view, and FIG. 3B is a CMOS type logic cell, for example,
FIG. 3C is a diagram showing the area used when configuring a 2-input NAND circuit, and FIG.
A diagram showing areas used when configuring an input NAND circuit,
The third diagram shows the area used when configuring a two-boat type static RAM cell, and FIG. 4 shows the master slice type semiconductor integrated circuit device according to the first embodiment of the present invention. Figure 4A is a plan view, Figure 4B is a cross-sectional view (
FIG. 5 is a diagram showing a B1CMOS type two-input NAND circuit constructed using the first embodiment of the present invention (the example in FIG. 4). 5A is a plan view, FIG. 5B is an equivalent circuit diagram, FIG. 6 is a plan view showing a master slice type semiconductor integrated circuit device according to a second embodiment of the present invention, and FIG. 8 is a diagram showing a CMOS type two-input NAND circuit configured using the second embodiment (example in FIG. 6), FIG. 7A is a plan view, FIG. 7B is an equivalent circuit diagram, and FIG. 8 is a diagram showing a B1CMOS type two-input NAND circuit configured using the second embodiment (example in FIG. 6) of the present invention, in which FIG. 8A is a plan view and FIG. 8B is an equivalent circuit diagram. , FIG. 9 is a diagram showing a one-boat type static RAM cell configured using the second embodiment (example in FIG. 6) of the present invention, FIG. 9A is a plan view, and FIG. B is an equivalent circuit diagram, FIG. 10 is a diagram showing a two-boat type static RAM cell constructed using the second embodiment of the present invention (example in FIG. 6), and FIG. 10A is a plan view. 10B is an equivalent circuit diagram, FIG. 11 is a plan view showing an example of a master slice type semiconductor integrated circuit device having a conventional BiCMO3 structure, and FIG. 12 is a basic cell configuring the conventional example shown in FIG. 11. FIG. 12A is a plan view of an example of a basic cell;
Figure 2B is a cross-sectional view of an example of a basic cell (Y-Y in Figure 12A).
12C is a plan view showing another example of the basic cell. In the figure, ■... first conductivity type ■... second conductivity type 5... first type IGFET 4... Second type IGFET 3... Second type BJT 9a... First conductivity type source/drain region 9b...
Second conductivity type source/drain region 8... Insulated gate electrode 15... PMO3 14... NMO3 16... n p n B J T 19... Source/drain region 18... Gate electrode 20... ...Isolation region 21.22...Impedance element 40...P type substrate 42...P type epitaxial layer 44...N type well 50...P type base region 51...N type emitter region 55...CMO3 56...Emitter region 1. 7a, 2. 11. 12. 13. 17. 7b, 57...Base region 58...Collector region, 6 (A) Plan view (B) Cross-sectional view (FIG. 1 Acr) WW' line cross-sectional view) The principle of the first invention in the present invention Explanatory drawings Figure 1 (A) Plan view (B) Cross sectional view (cross sectional view taken along the line Q-Q' in Figure 4 A) Master slice type semiconductor integrated circuit device according to the first embodiment of the present invention Master slice type semiconductor integrated circuit An example of a circuit device FIG. 11 (A) A plan view of an example of a basic cell (B) A sectional view of an example of a basic cell (YY' in FIG. 12A)
Line sectional view〉(C) Plan view showing another example of basic cell Fig. 11 Basic cell with n4 precepts of conventional example Fig. 12

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device having a cell region in which basic cells are arranged, wherein at least one of the basic cells is arranged in a first
A first insulated gate field effect transistor (1) of a first type in which carriers of a conductivity type transport current;
an insulated gate field effect transistor (2), a bipolar junction transistor of the second type in which carriers of the second conductivity type transport the main current (3), a third insulator of the second type in which the carriers of the second conductivity type transport the current; Gate field effect transistor (4
), a fourth insulated gate field effect transistor (5) of the first type in which carriers of the first conductivity type transport current is connected to a predetermined first
A master slice type semiconductor integrated circuit device having a configuration in which the semiconductor integrated circuit device is sequentially arranged in a direction. 2. The first insulated gate field effect transistor, the second insulated gate field effect transistor, the third insulated gate field effect transistor, and the fourth insulated gate field effect transistor are arranged in a second direction intersecting the first direction, respectively. two of the second type bipolar junction transistors are aligned, and one second type bipolar junction transistor is arranged between two second insulated gate field effect transistors and two third insulated gate field effect transistors to form one subunit. 2. The master slice type semiconductor integrated circuit device according to claim 1. 3. The master slice type semiconductor integrated circuit device according to claim 2, wherein two sets of said subunits are arranged successively in said second direction to constitute one unit. 4. The master slice type semiconductor integrated circuit device according to claim 3, further comprising a plurality of impedance elements arranged between the subunits. 5. two second type bipolar junction transistors of the two subunits and two of the impedance elements;
and wherein the two first type first insulated gate field effect transistors and the two second type second insulated gate field effect transistors in one subunit constitute a two-input NAND circuit. The master slice type semiconductor integrated circuit device described above. 6. Two second type insulated gate field effect transistors (
a first second type insulated gate field effect transistor section (64) consisting of two first type insulated gate field effect transistors (1, 1) and two second type insulated gate field effect transistors (63, 63); A first transistor consisting of field effect transistors (2, 2)
a complementary insulated gate field effect transistor section (65), a second type bipolar junction transistor section (66) consisting of one second type bipolar junction transistor (3), and two second type insulated gates. Field effect transistor (4,
4) and a second complementary insulated gate field effect transistor section (67) consisting of two first type insulated gate field effect transistors (5, 5), and two second type insulated gate field effect transistors. (68
, 68) and a second type insulated gate field effect transistor section (69) sequentially arranged in a predetermined first direction. Semiconductor integrated circuit device. 7. Two second type insulated gate field effect transistors (
a first second type insulated gate field effect transistor section (64) consisting of two first type insulated gate field effect transistors (1, 1) and two second type insulated gate field effect transistors (63, 63); A first transistor consisting of field effect transistors (2, 2)
a complementary insulated gate field effect transistor section (65), a second type bipolar junction transistor section (66) consisting of one second type bipolar junction transistor (3), and two second type insulated gates. Field effect transistor (4,
4) and a second complementary insulated gate field effect transistor section (67) consisting of two first type insulated gate field effect transistors (5, 5), and two second type insulated gate field effect transistors. (68
, 68) are sequentially aligned in a predetermined first direction, and one or more impedance elements are arranged at arbitrary positions. A master slice type semiconductor integrated circuit device comprising a basic cell. 8. Four second type insulated gate field effect transistors (
a third second type insulated gate field effect transistor section (72) consisting of two first type insulated gate field effect transistors (1, 63, 71, 71);
1) and two second type insulated gate field effect transistors (2, 2); and one second type bipolar junction transistor (3). ), and two second type insulated gate field effect transistors (4,
4) and a second complementary insulated gate field effect transistor section (67) consisting of two first type insulated gate field effect transistors (5, 5), and four second type insulated gate field effect transistors. (68
, 68, 73, 73) and a fourth second type insulated gate field effect transistor section (74) arranged in sequence in a predetermined first direction. Master slice type semiconductor integrated circuit device. 9. Four second type insulated gate field effect transistors (
a third second type insulated gate field effect transistor section (72) consisting of two first type insulated gate field effect transistors (1, 63, 71, 71);
1) and two second type insulated gate field effect transistors (2, 2); and one second type bipolar junction transistor (3). ), and two second type insulated gate field effect transistors (4,
4) and two first-type insulated gate field effects (5, 5)
A second complementary insulated gate field effect transistor section (67) consisting of transistors, and four second type insulated gate field effect transistors (68).
, 68, 73, 73) are sequentially aligned in a predetermined first direction, and one
Alternatively, a master slice type semiconductor integrated circuit device comprising a basic cell having two or more impedance elements arranged therein.