JPH0828486B2 - Master slice type semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION [Table of Contents] Outline Industrial field of application Conventional technology (Figs. 11 and 12) Problem to be solved by the invention Means for solving the problem 1st invention (Fig. 1) ) Second invention (Fig. 2) Third invention (Fig. 3) Action Action of first invention Action of second invention Action of third invention Embodiment 1st embodiment (Fig. 4, Fig. 4) 5) Second embodiment (FIGS. 6 to 10) Others Effects of the invention Effects of the first invention Effects of the second invention Third effects [Overview] In a semi-custom type semiconductor integrated circuit device The present invention relates to a master slice type semiconductor integrated circuit device, that is, a semiconductor integrated circuit device in which certain basic cells are regularly arranged, and when configuring various logic circuits, the number of unused elements is reduced, Make it possible to improve the area utilization efficiency and improve the degree of integration At least one of the basic cells is a first insulated gate field effect transistor of a first type in which carriers of a first conductivity type carry a current, and a second conductivity type of a polarity opposite to that of the first conductivity type. The second conductivity type carrier has a second conductivity type second insulated gate field effect transistor, a collector region in contact with a region where a channel of the second insulation gate field effect transistor is formed, and the second conductivity type carrier is a main current. A second-type bipolar junction transistor for transporting an electric field, and a region for forming a channel in contact with the collector region of the second-type bipolar junction transistor. 3 insulated gate field effect transistors,
The first-type fourth insulated gate field effect transistor, in which the first-conductivity-type carriers transport current, is configured to be sequentially arranged in a predetermined first direction.

[Field of Industrial Application] The present invention relates to a master-slice type semiconductor integrated circuit device in a semi-custom type semiconductor integrated circuit device, that is, a certain basic cell.
ll) are regularly arranged in the semiconductor integrated circuit device.

Such master slice type semiconductor integrated circuit devices are classified by device structure: (1) those having a TTL (transistor transistor logic) structure (2) those having an ECL (emitter-coupled logic) structure (3) CMOS (complementory MOS) ) Those having a structure (4) Those having a BiCMOS structure can be classified. Here, the master slice type semiconductor integrated circuit device having a BiCMOS structure has the advantages of high current driveability (high load driveability) by bipolar technology and low power consumption by CMOS technology. Conventionally, attention has been paid to the fact that the integrated circuit device can cope with large scale and high integration.

[Prior Art] Conventionally, as a master slice type semiconductor integrated circuit device having a BiCMOS structure, FIG. 11 is its plan view, FIG. 12A is a plan view of a basic cell, and FIG. 12B is a sectional view of the basic cell. (No. 12
As shown in FIG. A, which is a sectional view taken along the line YY ') has been proposed.

Here, in FIG. 11, 60 is the chip body, and 61 is the I / O.
A cell, 62 indicates a basic cell, and such a master slice type semiconductor integrated circuit device is configured by spreading the basic cell 62 over the entire surface of the internal region. Such a semiconductor integrated circuit device is generally called a channelless type master slice type semiconductor integrated circuit device or SOG (sea of gate) (see Japanese Patent Laid-Open No. 63-306639).

Next, the planar structure of the basic cell 62 will be described with reference to FIG. 12A. Two p-channel MOS transistors (hereinafter referred to as PMOSs) 11 and 15 have their drain regions 19a in common. , Are arranged to meet each other.
Similarly, two n-channel MOS transistors (hereinafter referred to as NMO
12 and 14 (referred to as S) are arranged side by side with the drain region 19b in common. Source regions of PMOS 11 and 15
17a are arranged on the opposite sides of the drain region 19a. Similarly, the source regions 17b of the NMOSs 12 and 14 are arranged on opposite sides with the drain region 19b interposed therebetween. A gate electrode 18 (18-1, 18-2) is arranged between the source region and the drain region of each MOS transistor. The source region and the drain region of each MOS transistor are symmetrical and can be used interchangeably. Therefore, hereinafter, the source region and the drain region are collectively referred to as a source / drain region.

The configuration shown in the central portion of FIG. 12A includes two PMOSs 11 and 15 arranged in abutment in this manner, and two NMOSs 12 and 14 arranged in abutment in the same manner.
And the NMOS 12 have a common gate electrode 18-1 and the other side of the PMOS 15 and the NMOS 14 have a common gate electrode 18-2. That is, these MOS transistors are C
Form a MOS structure. Npn type bipolar junction transistors (hereinafter referred to as npnBJTs) 13 and 16 are arranged on both sides of the CMOS. Although not shown, two impedance elements are further arranged on the left and right outer sides. Using these elements, for example, one 2-input NAND circuit can be formed.

Next, referring to FIG. 12B, the cross-sectional structure of the basic cell 62 will be described. On the p-type substrate 30, n ⁺ -type buried regions 34a, 34b and 34c and p ⁺ -type buried regions 35a and 35b are provided. Is formed on top of which PMOS 11, 15 and NMOS 12, 14 and two np
Regions for forming nBJTs 13 and 16, that is, n-type regions 32b
, A p-type region 31a, a p-type region 32c, and a p-type region 32a are formed, respectively. Further, a p-type region 39 for element isolation is provided between the n-type regions 32a and 32b. Then, the PMOSs 11 and 15 are formed in the central n-well 32b, and the NMOSs 12 and 14 are formed in the right p-well 31. Also,
On the surface of the n-well 32b, the p ⁺ region 17a and on the surface of the p-well 31 are n ⁺
Regions 17b are formed and form the source / drain regions of the PMOS 15 and the NMOS 14, respectively. Furthermore, the outer n-type region
NpnBJTs 16 and 13 are formed on 32a and 32c, respectively. Here, since the n-type region 32a functions as a collector region of the npnBJT16, the p-type region 39 forming an element isolation region is required between the n-type region 32a and the n-type region 32b.

In addition, the basic cells 62 shown in FIG.
This is an example of a basic cell configured by arranging S, NMOS, and npnBJT, but some may be arranged vertically. FIG. 12C shows an example of such a basic cell. In this example, PMOS 11, 15 and
The arrangement of the NMOSs 12 and 14 and the arrangement of the npnBJTs 13 and 16 and the impedance elements 21 and 22 are arranged separately, that is, in two rows in the lateral direction. This point is shown in FIG. The cell and its configuration are different.

[Problems to be Solved by the Invention] In such a master slice type semiconductor integrated circuit device, when various logic circuits or functional blocks are constructed by using one or a plurality of basic cells, npnBJT
Reference numerals 13 and 16 denote portions such as output buffers that require high load driving capability (for example, the output terminal of a certain logic circuit or functional block is connected to the input terminal of another logic circuit or functional block through a relatively long wiring). Or when connecting the output terminal of a certain logic circuit or functional block to the input terminals of a plurality of other logic circuits or functional blocks, etc., the npnBJT
It is common to use only PMOS 11, 15 and NMOS 12, 14 without using 13, 16. Therefore, like the basic cell 62 shown in FIG. 12A and the basic cell shown in FIG.
In a conventional master slice type semiconductor integrated circuit device in which two npnBJTs 13 and 16 are provided for MOS transistors, that is, PMOSs 11 and 15 and NMOSs 12 and 14, the number of npnBJTs 13 and 16 is large for MOS transistors. However, when looking at this as a whole, there was a problem that the number of remaining npnBJTs that were not used and remained was large, and the efficiency of use of the device was poor. In other words, the area utilization efficiency of the chip was poor, which hindered improvement in the degree of integration.

Further, for example, in the case of the basic cell 62 shown in FIG. 12A, the element isolation region 20 must be provided between the PMOS 11, 15 and npnBJT16. In the case of the basic cell shown in FIG. 12C, an element isolation region (not shown) must be provided between the PMOS 15 and npnBJT16. This also reduces the area utilization efficiency and hinders the improvement of the degree of integration.

Further, in recent years, when a semiconductor integrated circuit device having a certain function is configured using such a master slice type semiconductor integrated circuit device, it has become common to incorporate a RAM or a ROM. Here, for example, when configuring a 1-port type static RAM cell, two PMOSs and two NMOSs are required as MOS transistors that configure the storage element section (flip-flop, latch), and the transfer gate Two NMOs as MOS transistors that compose the
Requires S (see FIG. 9B). That is, the required PMO
The numbers of S and NMOS do not match. Therefore, when such a static RAM cell is composed of the basic cell 62 shown in FIG. 12A and the basic cell shown in FIG. 12C in which the numbers of PMOS and NMOS are the same, there are many PMOSs that are not used. This reduces the area utilization efficiency and hinders the improvement of the degree of integration. Further, in the case of a ROM, the ROM cell is generally composed of an NMOS in order to improve the reading speed, and in this case also, there are many unused PMOSs.

Here, a first object of the present invention is to reduce the number of elements that are not used and remain when configuring various logic circuits, thereby increasing area utilization efficiency and improving integration degree. It is an object of the present invention to provide a master slice type semiconductor integrated circuit device having a BiCMOS structure.

A second object of the present invention is not only to implement various logic circuits,
When configuring a memory such as RAM or ROM, it has a BiCMOS structure that reduces the number of elements that are not used and remains, thus increasing the area utilization efficiency and improving the degree of integration. It is to provide a master slice type semiconductor integrated circuit device.

[Means for Solving the Problems] The above object is achieved by the following first, second and third inventions.

First Invention (FIG. 1) In the present invention, according to the first invention, there is provided a basic cell configuration satisfying the required number of bipolar junction transistors by a plurality of basic cell configurations. Further, there is provided a semiconductor integrated circuit device which does not require an element isolation region for a bipolar junction transistor. That is, there is provided a master slice type semiconductor integrated circuit device having a BiCMOS structure which can improve the area utilization efficiency and improve the degree of integration when configuring various logic circuits.

FIG. 1 is a diagram for explaining the principle of the first invention in the present invention, wherein FIG. 1A is a plan view and FIG. 1B is a sectional view (a sectional view taken along line WW ′ of FIG. 1A). is there.

In the figure, from the left to the right, first conductivity type carriers carry a current, a first type insulated gate field effect transistor (hereinafter referred to as IGFET) 1, second conductivity type carriers carry a current. Type 2 IGFET2, BJT3, Type 2
An IGFET 4 and a first type IGFET 5 are arranged.

The BJT3 is for transporting the main current by the second conductivity type carrier, and is formed in the first conductivity type well for forming the second type IGFETs 2 and 4 and the second conductivity type well of the opposite conductivity type. (See Figure 1B). That is, the BJT3 is formed so as to have a collector region in contact with the region where the channel of the IGFET2 is formed, and the IGFET4 is formed so as to have a region where the channel is formed in contact with the collector region of the BJT3.

Preferably, four IGFETs having the same structure as the first type IGFETs 1, 5 and the second type IGFETs 2, 4 are vertically symmetrical to the IGFETs 1, 2, 4, 5 as shown by the broken lines in FIG. 1A. It is formed with various configurations. At this time, the number of BJT3 does not increase.

It is preferable that the configuration shown by the solid line in FIG. 1A be a subunit, and that two subunits be arranged vertically as shown by a broken line to be one unit.

Further, it is preferable to arrange a plurality of impedance elements between the subunits.

By using these configurations, various logic circuits made of CMOS and various logic circuits made of BiCMOS can be formed.

Second invention (Fig. 2) In the present invention, the second invention is various logic cells, RAM, R
A master slice type semiconductor integrated circuit device having a BiCMOS structure capable of improving area utilization efficiency in the case of configuring a memory such as an OM. Particularly, for example, a 1-port static RAM is configured. This is a master slice type semiconductor integrated circuit device suitable for the case.

The second aspect of the present invention is, as shown in FIG. 2A, an explanatory view of its principle, that is, a first second type IGFET section 64 composed of two second type IGFETs 63, 63 and two first type IGFET parts 64. IGFET 1, 1 and 2
First type CMOS transistor section 65 consisting of two second type IGFETs 2 and 2 and second type BJT type 66 consisting of one second type BJT3
And two second type IGFETs 4, 4 and two first type IGFEs
A basic cell in which a second CMOS transistor section 67 composed of T5 and 5 and a second second type IGFET section 69 composed of two second type IGFETs 68 and 68 are sequentially arranged in a predetermined first direction. It is configured with. Here, BJT3 is formed so as to have a collector region in contact with the region where the channels of IGFET2, 2 are formed, and IGFET4, 4 is formed so as to have a region where the channel is formed in contact with the collector region of BJT3. It The impedance element may be arranged at any position.

Third invention (Fig. 3) In the present invention, the third invention is various logic cells, RAM, R
A master slice type semiconductor integrated circuit device having a BiCMOS structure capable of improving area utilization efficiency when configuring a memory such as an OM, and particularly, for example, a 2-port static RAM cell or This is a master slice type semiconductor integrated circuit device that is effective when configuring a ROM.

As shown in FIG. 3A, which illustrates the principle of the third invention, the third invention includes a third second type IGFET section 72 composed of four second type IGFETs 63, 63, 71 and 71, and two IGFET sections 72. First type IGFET1,
A first CMOS transistor section 65 consisting of one and two second-type IGFETs 2 and 2, and a second type consisting of one second-type BJT3.
BJT section 66 and two second type IGFETs 4, 4 and two first IGFETs
-Type IGFETs 5, 5, second CMOS section 67 and four second
Type IGFETs 68, 68, 73, 73
And 74 are sequentially arranged in a predetermined first direction. Here, BJT3 is formed so as to have a collector region in contact with the region where the channels of IGFET2, 2 are formed, and IGFET4, 4 is formed so as to have a region where the channel is formed in contact with the collector region of BJT3. It The impedance element may be arranged at any position.

[Operation] The operation of the first, second and third inventions is as follows.

Action of First Invention As shown in FIG. 1A, by arranging four or more IGFETs for one BJT, the relative density of BJTs is reduced and the number of unused BJTs is reduced. You can

As shown in FIG. 1B, the second type B is sandwiched between the second type IGFETs.
Since the pn junction is formed between the wells by arranging the JT, the special element isolation region can be omitted. Therefore, the area utilization efficiency becomes high.

By reducing the number of unnecessary BJTs and the area of the isolation region, the overall area utilization efficiency is improved and the degree of integration can be improved.

Operation of the Second Invention According to the second invention, the IG is the same as in the first invention.
Since the number of BJTs with respect to the number of FETs can be reduced, the number of unnecessary BJTs can be reduced, the overall area utilization efficiency can be increased, and the degree of integration can be improved, and two second type IGFET63, Since the first second type IGFET section 64 composed of 63 and the second second type IGFET section 69 composed of two second type IGFETs 68, 68 are provided, ROM or RAM, particularly, for example, two When constructing a 1-port type static RAM cell that requires four 1st type IGFETs and 4 2nd type IGFETs,
The second type IGFET 63 can be used as a transistor for a transfer gate.

In FIG. 2, FIG. 2B shows a CMOS type logic cell, for example, an area used when a CMOS type two-input NAND circuit is formed, and FIG. 2C shows a BiCMOS type logic cell, for example. , BiCMOS type 2-input NAND circuit and CMOS type logic cell,
For example, FIG. 2 is a diagram showing a used area in the case of forming a CMOS type two-input NAND circuit, and FIG. 2D is a diagram showing a used area in the case of forming a RAM cell, for example, a 1-port type static RAM cell. . Here, the wiring region in FIGS. 2B and 2C indicates that the second type IGFET portions 64 and 69 can be used as the wiring region.
The same applies to FIGS. 3B and 3C.

Operation of Third Invention According to the third invention, as in the first invention, the IG
Since the number of BJTs with respect to the number of FETs can be reduced, the number of unnecessary BJTs can be reduced, the overall area utilization efficiency can be increased, and the integration degree can be improved.
Since the first second type IGFET section 72 including the IGFETs 63, 63, 71 and 71 and the second second type IGFET section 74 including the four second type IGFETs 68, 68, 73 and 73 are provided, ROM or RAM, especially, for example, two first type IGFETs, six second type IGFETs
The second-type IGFETs 63 and 71 can be used as transistors for the transfer gate when a 2-port type static RAM cell requiring the above is constructed.

In FIG. 3, FIG. 3B shows a CMOS type logic cell, for example, a region used when forming a CMOS type two-input NAND circuit, and FIG. 3C shows a BiCMOS type logic cell, for example. , BiCMOS type 2-input NAND circuit and CMOS type logic cell,
For example, FIG. 3D is a diagram showing a use area in the case of forming a CMOS type two-input NAND circuit, and FIG. 3D is a view showing a use area in the case of forming a RAM cell, for example, a 2-port type static RAM cell. .

[Embodiment] An embodiment of a master slice type semiconductor integrated circuit device according to the present invention will be described below with reference to FIGS.

First Embodiment (FIGS. 4 and 5) In the first embodiment of the present invention, as a basic cell, FIG. 4A is a plan view thereof, and FIG. 4B is a sectional view thereof (FIG. 4A).
A basic cell as shown in FIG.

In the plan view of FIG. 4A, PMOS1A, NMOS2A, npnBJT
3A, NMOS4A, PMOS5A are arranged side by side. Another PMOS 1B is arranged in the lower part in the figure in abutment with the PMOS 1A, and another NMOS 2B is arranged in a lower part in the same manner as it is in contact with the NMOS 2A. The NMOS 4B and the PMOS 5B are also arranged in abutting relationship with the NMOS 4A and the PMOS 5B. One BJT3A is arranged in the center for these eight MOS transistors.

Another set equivalent to these configurations is arranged further below. That is, a pair of PMOS 1C, 1D, a pair of NM
OS2C, 2D, 1 npnBJT3B, 1 pair of NMOS4C, 4D, 1 pair
The PMOSs 5C and 5D are arranged in the horizontal direction. That is, eight MOS transistors and one BJT form one subunit, and two subunits are arranged one above the other to form one unit. Four impedance elements 10A, 10B, 10C, 1 are arranged in a row in the horizontal direction between these subunits.
0D is arranged. In other words, within one unit,
Four pairs of PMOS, four pairs of NMOS, one pair of BJT, and two pairs of impedance elements are arranged. Moreover, since the NMOSs 2A, 2B, 2C, 2D, 4A, 4B, 4C, and 4D are arranged on both sides of the npnBJT3A and 3B, pn separation for the npnBJT is automatically achieved.

Referring to the sectional view of FIG. 4B, the semiconductor integrated circuit is formed on the p-type substrate 40. After forming the p-type buried region and the n-type buried region on the desired region of the p-type substrate 40, the p-type epitaxial layer 42 is formed. N-type wells 44a, 44b and 44c are formed in the p-type epitaxial layer. A p-type epitaxial layer remains between the n-type regions 44a, 44b and 44c to form a p-type well. n-type well 44
A pair of p ⁺ type regions 7a are formed on the surface of a, and the source / drain regions of the p channel MOS transistor are formed. Similarly, a pair of p ⁺ -type regions 7a is formed in the n-type region 44c, and a PMOS is formed. On the surface of the central n-type well 44b, a p-type region 50 and an n ⁺ region 51 thereof are formed to form an npn bipolar junction transistor 3A.
Since the n-type well 44b is separated from the peripheral region by the pn junction,
In particular, it is not necessary to form another isolation region. Gate electrodes 8-2 and 8-4 made of polycrystalline silicon or the like are formed on the CMOS structure via a thin gate oxide film.

The number of elements arranged in one unit is 4 pairs of PMOS, 4
By using a pair of NMOSs, a pair of BJTs, and a pair of impedance elements, the possibility that an extra number of BJTs will be formed is reduced, and the formed elements can be used efficiently.
Since a pair of BJTs are arranged adjacent to each other, it is easy to connect them.

By arranging the NMOS adjacent to the npnBJT, element isolation is automatically achieved and the area of the isolation region can be reduced.

An example of forming a logic circuit using the basic units shown in FIGS. 4A and 4B is shown in FIG.

FIG. 5 is a diagram showing a BiCMOS type two-input NAND circuit. FIG. 5A is a plan view and FIG. 5B is an equivalent circuit diagram.

The structure of FIG. 5 uses the basic cell unit structure shown in FIGS. 4A and 4B. That is, in the unit,
4 pairs of CMOS structure (55A, 55B, 55C, 55D) composed of 1 pair of PMOS and 1 pair of NMOS are arranged in a matrix and CM
Two BJTs 3A, 3B are arranged between OS55A, 55C and CMOS 55B, 55D, and impedance elements 10A, 10B are placed between the upper and lower CMOSs.
10C and 10D are arranged.

The elements required to construct a 2-input NAND circuit are two PMOSs, two NMOSs, two impedance elements, and two BJTs. So for CMOS, one of the ones shown
It is enough to use / 4. As for the impedance element, it is sufficient to use 1/2 of that shown in the figure. For BJT, use all of the ones shown. That is, although some CMOSs and impedance elements are not used, they can be used for other circuits. In the figure, -indicates the first-layer wiring and = indicates the second-layer wiring. Further, a cross mark indicates the position of the connection hole between the substrate and the first-layer wiring, and a double mark indicates the position of the connection hole between the first and second wiring layers. Also, vertical broken lines indicate the power supply line and the ground line included in the first layer wiring. The same applies to FIGS. 6 to 10 below.
Also, within each BJT region, an emitter region 56 and a base region 5
7. A collector region 58 is arranged.

The circuit configuration will be described with reference to FIG. 5A. Two inputs A1 and A2 are applied to gates 8-1 and 8-2 common to PMOS and NMOS. The source / drain regions 7a of the pair of left PMOSs 1A and 1B are connected to the power supply line VDD, and the other source / drain regions 9a are connected through the first-layer wiring and the second-layer wiring,
It is connected to the base region 57 of the upper BJT in the figure. This BJT
The emitter region 56 of the BJT is connected to the collector region 58 of the lower BJT via the first layer wiring. The emitter region 56 of the lower BJT is connected to the ground line VSS via the first layer wiring. The base region 57 of the lower BJT is connected to one of the source / drain regions 7b of the NMOS 2A and the impedance element 10A via the first layer wiring.
The impedance element 10A is connected to the ground line VSS via the first layer wiring and the second layer wiring. NMOS2A and NMO
S2B is connected in series, and the other end is connected to the intermediate connection point between the PMOSs 1A and 1B via the impedance element 10B.

The upper BJT emitter region 56 and the lower BJT collector region 58 are commonly connected and led to the output terminal X.

Therefore, as shown in FIG. 5B, NA is applied to two inputs A1 and A2.
An ND circuit is constructed and provides an output X.

Second Embodiment (FIGS. 6 to 10) In the second embodiment of the semiconductor integrated circuit device according to the present invention, a basic cell as shown in FIG. The configuration is similar to that of the first embodiment. In the figure, 63A, 63B, 71A, 71B, 68A, 68
B, 73A and 73B are NMOS.

Next, using this basic cell, CMOS type 2-input NAND
A circuit, a BiCMOS type 2-input NAND circuit, a 1-port type static RAM cell, and a 2-port type static RAM cell will be described.

(1) CMOS type 2-input NAND circuit FIGS. 7A and 7B are CMOS type 2-input NAND circuits of this example, respectively.
The plane structure of a circuit and its equivalent circuit are shown. In this example, PMOS 1A, 1B and NMOS 2A, 2B are used.

Here, PMOS1A and 1B are the source / drain regions 7
The a and 7a are connected to the power supply line VDD, and the source / drain regions 9a thereof are connected to the second layer wiring 76 through the first layer wiring 75. In addition, NMOS2A is the source / drain region
7b is connected to the second layer wiring 76 via the first layer wiring 75,
OS2B connects the source / drain region 7b to the ground line VSS.
It is connected to the.

In such a 2-input NAND circuit, the gate electrode 8-1
, And inputs 8 and 8-2, respectively,
Output to the second layer wiring 76 Can be obtained.

If the PMOSs 5A, 5B and the NMOSs 4A, 4B are used for other logic circuits and the npnBJT3B is not used, one npnBJT is not used for this portion for every eight MOS transistors.

(2) BiCMOS type 2-input NAND circuit FIGS. 8A and 8B show BiCMOS type 2 input NA of this example, respectively.
The plane structure of an ND circuit and its equivalent circuit are shown. In this example, PMOSs 1A and 1B, NMOSs 2A and 2B, impedance elements 10A and 10B, and npnBJT3A and 3B are used.

Here, the PMOS 1A and 1B are the source / drain regions 7a.
Is connected to the power supply line VDD, and its source / drain region 9a is connected to the base region 57 of the npnBJT3A via the first layer wiring 77, the second layer wiring 78, and the first layer wiring 79, and
Similarly, it is connected to the second layer wiring 81 via the first layer wiring 77, the impedance element 10A, and the first layer wiring 80.

The NMOS 2A has its source / drain region 7b connected to the second layer wiring 81, the collector region 58 of the npnBJT3B and the emitter region 56 of the npnBJT3A via the first layer wiring 82.
The NMOS 2B has its source / drain region 7b connected to the base region 57 of the npnBJT3b via the first-layer wiring 83, and also has the same first-layer wiring 83 and impedance element 10
B is connected to the ground line VSS via the first layer wiring 84.

The collector region 58 of the npnBJT3A is connected to the power supply line VDD via the first layer wiring 85 and the second layer wiring 86. The emitter region 56 of npnBJT3B is connected to the ground line VSS via the first layer wiring 87.

In such a 2-input NAND circuit, the gate electrode 8-1
, And inputs 8 and 8-2, respectively,
Output to the second layer wiring 81 Can be obtained.

Here are the other PMOS 1A, 1B, 5A, 5B and
Since the NMOSs 2A, 2B, 4A, and 4B can be used for other logic circuits, in this case, wasteful npnBJT does not occur for this unit part.

(3) 1-port type static RAM cell FIGS. 9A and 9B respectively show the planar configuration of the 1-port type static RAM cell of this example and its equivalent circuit. In this example, PMOS1A, 1B and NMOS2A, 2B,
63A and 71A are used.

Here, PMOS 1A and 1B are the source / drain regions 9a.
Is connected to the power supply line VSS. Also, PMOS1B, NMO
S2B connects the gate electrode 8-2 with P through the first-layer wiring 88.
Source / drain region 7a of MOS1A and source / drain of NMOS2A /
It is connected to the drain region 7b. The PMOS1B has a source / drain region 7a whose first layer wiring 89 is the second layer wiring.
90 is connected to the source / drain region 9b of the NMOS 71A via the first layer wiring 91. Here, the NMOS 71A has its source / drain region 7b connected to one bit line BL via a first layer wiring 92, and its gate electrode 70-1 has a first layer wiring.
It is connected to the word line WL via 93.

In addition, the NMOS 2A has its gate electrode 8-1 wired in the first layer.
It is connected to the source / drain region 9b of the NMOS 71 via 94 and the second layer wiring 90. The source / drain region 7b of the NMOS 2B is connected to the source / drain region 9b of the NMOS 71 via the first-layer wiring 95 and the second-layer wiring 90. The gate electrodes 8-2 of the PMOS 1B and NMOS 2B are connected to the source / drain regions 9b of the NMOS 63A via the first layer wiring 96. The source / drain regions 9b of the NMOS 2A and 2B are connected to the ground line VSS.

The NMOS 63A has a source / drain region 7b of 1
The other bit area 7b is connected to the first layer wiring 97 through the first layer wiring 97.
Is connected to the other bit line ▲ ▼.

As shown by the broken line in FIG. 9B, NMOS 71B and 63B
Can be connected in parallel to NMOS 71A and 63A respectively,
In this case, the access speed can be increased.

(4) Two-port type static RAM cell FIGS. 10A and 10B respectively show the planar structure of the two-port type static RAM cell of this example and its equivalent circuit. In this example, PMOS1A, 1B and NMOS2A, 2B,
63A, 63B, 71A, 71B are used.

In this example, the NMOS 71A has its source / drain region 7b via one of the first bit lines BL1 via the first layer wiring 92.
It is connected to the. The NMOS 63A has its source / drain region 7b connected to the other first bit line BL1 via the first-layer wiring 97. The gate electrodes 70-1 of the NMOS 71A and 63A are connected to the first word line WL1 via the first layer wiring 93.

The NMOS 71B has its source / drain region 7b connected to one of the second bit lines BL2. Also, NMOS63B
Is the source / drain region 7b of the other second bit line
It is connected to BL2. The gate electrodes 70-2 of the NMOS 71B and 63B are connected to the second word line WL via the first layer wiring 98.

Others are the same as those of the static RAM cell shown in FIG.

Others In the above-described embodiment, the present invention is applied to a so-called channelless master slice semiconductor integrated circuit device (SO
Although the case of application to G) has been described, the present invention can also be applied to a master slice type semiconductor integrated circuit device provided with a channel region.

In addition, in the first embodiment, a BiCMOS type 2-input NAND is used.
Although the case of configuring a circuit has been described, it will be apparent to those skilled in the art that various other logic circuits can be configured.

Further, in the second embodiment, a CMOS type two-input NAND circuit, a BiCMOS type two-input NAND circuit, a one-port type static RAM cell, and a two-port type static R
Although the case of configuring an AM cell has been described, it goes without saying that various logic circuits, ROM cells, and the like can be configured.

Also, in the second embodiment, pMOS1A, 1B is replaced by nMOS2A,
I described the case of arranging it on the left side in the figure for 2B,
Instead of this, nMOS2A and 2B are replaced by pMOS1A and 1B in the figure,
It can also be placed on the left side. In this case, pMOS1A,
An element isolation region must be formed between 1B and npnBJT3A, but at least the effect that a static RAM cell can be efficiently formed is obtained. pMOS5
The same applies to the positional relationship between A, 5B and nMOS 4A, 4B.

It will also be apparent to those skilled in the art that the first and second embodiments can be configured with all conductivity types reversed.

[Effects of the Invention] According to the present invention, the following effects can be obtained.

Advantageous Effects of the First Invention According to the first invention, the number of BiCMOS basic cells is reduced.
Since the BJT and the impedance element are used, the number of elements not used can be reduced.

Since the MOS transistor formed in the well of the opposite conductivity type to the collector region of the BJT is arranged adjacent to the BJT,
Element isolation is automatically achieved, area utilization efficiency is increased,
The degree of integration can be improved.

Effect of the Second Invention According to the second invention, as in the first invention, it is possible to reduce the number of BJTs with respect to the number of IGFETs.
The number of JTs can be reduced, the overall area utilization efficiency can be increased, and the integration level can be improved.
And a first CMOS transistor part composed of two second type IGFETs, and a first second composed of two second type IGFETs.
Type IGFET is provided and a second second type of two second type IGFETs is provided for a second CMOS transistor part of two first type IGFETs and two second type IGFETs. Since IGFET is provided, it is suitable for ROM or RAM, especially when constructing a 1-port type static RAM that requires, for example, two first type IGFETs and four second type IGFETs.
A master slice type semiconductor integrated circuit device having an iCMOS structure can be provided.

Effect of the third invention According to the third invention, since the number of BJTs with respect to the number of IGFETs can be reduced as in the first invention, unnecessary B
The number of JTs can be reduced, the overall area utilization efficiency can be increased, and the integration level can be improved.
And a first CMOS transistor part composed of two second type IGFETs, and a third second composed of four second type IGFETs.
Type IGFET is provided, and a second CMOS transistor unit including two first type IGFETs and two second type IGFETs, and a fourth second type including four second type IGFETs Since IGFET is provided, it is suitable for ROM and RAM, especially when constructing a 2-port type static RAM that requires, for example, two first type IGFETs and six second type IGFETs.
A master slice type semiconductor integrated circuit device having an iCMOS structure can be provided.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the first invention in the present invention,
1A is a plan view and FIG. 1B is a sectional view (W- in FIG. 1A).
W'line sectional view), FIG. 2 is an explanatory view of the principle of the second invention in the present invention,
2A is a plan view, FIG. 2B is a diagram showing a use area when a CMOS logic cell, for example, a 2-input NAND circuit is configured, and FIG. 2C is a BiCMOS logic cell, for example, 2 Input NA
ND circuit and CMOS type logic cell, for example, a diagram showing a use area when configuring a 2-input NAND circuit, FIG. 2D is a diagram showing a use area when configuring a 1-port type static RAM cell, FIG. 3 is an explanatory view of the principle of the third invention in the present invention,
3A is a plan view, FIG. 3B is a view showing a use area when a CMOS type logic cell, for example, a 2-input NAND circuit is formed, and FIG. 3C is a BiCMOS type logic cell, for example, 2 Input NA
ND circuit and CMOS type logic cell, for example, a diagram showing a use area when forming a 2-input NAND circuit, FIG. 3D is a diagram showing a use area when forming a 2-port type static RAM cell, FIG. 4 is a diagram showing a master slice type semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 4A is a plan view and FIG. 4B is a sectional view (Q-Q in FIG. 4A). 5 is a diagram showing a BiCMOS type two-input NAND circuit constructed by using the first embodiment (example of FIG. 4) of the present invention, and FIG. 5A is a plan view. 5B is an equivalent circuit diagram, FIG. 6 is a plan view showing a master slice type semiconductor integrated circuit device of a second embodiment of the invention, and FIG. 7 is a second embodiment of the invention (example of FIG. 6). ) Is a diagram showing a CMOS type two-input NAND circuit configured by using
FIG. A is a plan view, FIG. 7B is an equivalent circuit diagram, and FIG. 8 is a diagram showing a BiCMOS type two-input NAND circuit configured by using the second embodiment (example of FIG. 6) of the present invention. FIG. 8A is a plan view, FIG. 8B is an equivalent circuit diagram, and FIG. 9 is a 1-port type static RAM cell constructed by using the second embodiment (example of FIG. 6) of the present invention. FIG. 9A is a plan view, FIG. 9B is an equivalent circuit diagram, and FIG. 10 is a two-port structure constructed by using the second embodiment (example of FIG. 6) of the present invention. 10A is a plan view, FIG. 10B is an equivalent circuit diagram, and FIG. 11 is an example of a master slice type semiconductor integrated circuit device having a conventional BiCMOS structure. FIG. 12 is a plan view showing a basic cell constituting the conventional example of FIG. 11, FIG. 12A is a plan view of an example of the basic cell, and FIG. 12B is a basic cell. An example cross-sectional view (cross-sectional view taken along the line YY 'in FIG. 12A) and FIG. 12C are plan views showing other examples of the basic cell. In the figure, I ... first conductivity type II ... second conductivity type 1,5 ... first type IGFET 2,4 ... second type IGFET 3 ... second type BJT 7a, 9a ... first conductivity Type source / drain regions 7b, 9b …… second conductivity type source / drain regions 8 …… insulated gate electrodes 11,15 …… PMOS 12,14 …… NMOS 13,16 …… npnBJT 17,19 …… source / drain Region 18 ... Gate electrode 20 ... Isolation region 21,22 ... Impedance element 40 ... P-type substrate 42 ... P-type epitaxial layer 44 ... N-well 50 ... P-type base region 51 ... N-type emitter Region 55 …… CMOS 56 …… Emitter region 57 …… Base region 58 …… Collector region

Claims (9)

[Claims] 1. A semiconductor integrated circuit device having a cell region in which basic cells are arranged, wherein at least one of the basic cells is a first-type first insulated gate in which carriers of a first conductivity type carry a current. Field-effect transistor (1), second carrier of the second conductivity type having a polarity opposite to that of the first conductivity type transports current
Type second insulated gate field effect transistor (2) and a collector region in contact with a region where a channel of the second insulated gate field effect transistor (2) is formed, the second conductivity type carrier transporting a main current. A second-type bipolar junction transistor (3), and a region in which a channel is formed in contact with the collector region of the second-type bipolar junction transistor (3). A configuration in which a second type third insulated gate field effect transistor (4) and a first type fourth insulated gate field effect transistor (5) in which carriers of the first conductivity type transport a current are sequentially arranged in a predetermined first direction. Master-slice type semiconductor integrated circuit device having: 2. The first insulated gate field effect transistor, the second insulated gate field effect transistor, the third insulated gate field effect transistor, and the fourth insulated gate field effect in a second direction intersecting the first direction. Two transistors are arranged respectively, and one second type bipolar junction transistor is arranged between two second insulated gate field effect transistors and two third insulated gate field effect transistors to form one subunit. The master slice type semiconductor integrated circuit device according to claim 1, which is configured as follows. 3. The master slice type semiconductor integrated circuit device according to claim 2, wherein two sets of the subunits are arranged in succession in the second direction to form one unit. 4. The master slice type semiconductor integrated circuit device according to claim 3, further comprising a plurality of impedance elements arranged between said subunits. 5. Two second type bipolar junction transistors of the two subunits, two of the impedance elements, and two first type first insulated gate field effect transistors in one of the subunits. Two second-type second insulated gate field-effect transistors and two-input NAND
5. The master slice type semiconductor integrated circuit device according to claim 4, which constitutes a circuit. 6. A carrier of the second conductivity type transports an electric current 2.
Second type insulated gate field effect transistors (63, 6)
A first second type insulated gate field effect transistor section (64) consisting of 3), and two first type insulated gate electric field in which carriers of the first conductivity type having a polarity opposite to that of the second conductivity type carry current. A first complementary insulated gate field effect transistor section (which includes an effect transistor (1, 1) and two second type insulated gate field effect transistors (2, 2) in which carriers of the second conductivity type carry a current ( 65) and a collector region that is in contact with the regions where the channels of the two second type insulated gate field effect transistors (2, 2) of the first complementary insulated gate field effect transistor section (65) are formed. Then, a second type bipolar junction transistor section (66) consisting of one second type bipolar junction transistor (3) in which the second conductivity type carrier transports the main current, and the second type bipolar junction transistor (66) ), Two second-type insulated gate field-effect transistors (4, 4) having a region where a channel is formed in contact with the collector region and carriers of the second-conductivity type transport current, and a first-conductivity-type carrier. A second complementary insulated gate field effect transistor section (67) consisting of two first type insulated gate field effect transistors (5, 5) in which carriers carry current, and a second conductivity type carrier carry current. A basic structure in which a second second type insulated gate field effect transistor section (69) composed of two second type insulated gate field effect transistors (68, 68) to be transported is sequentially aligned in a predetermined first direction. A master slice type semiconductor integrated circuit device comprising a cell. 7. A carrier of the second conductivity type transports an electric current 2.
Second type insulated gate field effect transistors (63, 6)
A first second type insulated gate field effect transistor section (64) consisting of 3), and two first type insulated gate electric field in which carriers of the first conductivity type having a polarity opposite to that of the second conductivity type carry current. A first complementary insulated gate field effect transistor section (which includes an effect transistor (1, 1) and two second type insulated gate field effect transistors (2, 2) in which carriers of the second conductivity type carry a current ( 65) and a collector region that is in contact with the regions where the channels of the two second type insulated gate field effect transistors (2, 2) of the first complementary insulated gate field effect transistor section (65) are formed. Then, a second type bipolar junction transistor section (66) consisting of one second type bipolar junction transistor (3) in which the second conductivity type carrier transports the main current, and the second type bipolar junction transistor (66) ), Two second-type insulated gate field-effect transistors (4, 4) having a region where a channel is formed in contact with the collector region and carriers of the second-conductivity type transport current, and a first-conductivity-type carrier. A second complementary insulated gate field effect transistor section (67) consisting of two first type insulated gate field effect transistors (5, 5) in which carriers carry current, and a second conductivity type carrier carry current. A second second type insulated gate field effect transistor section (69) consisting of two second type insulated gate field effect transistors (68, 68) to be transported is sequentially aligned in a predetermined first direction, and A master slice type semiconductor integrated circuit device comprising a basic cell in which one or more impedance elements are arranged at an arbitrary position. 8. A carrier of the second conductivity type transports an electric current 4.
Second type insulated gate field effect transistors (63, 6)
A first second type insulated gate field effect transistor section (72) composed of 3, 71, 71) and two first types in which carriers of a first conductivity type having a polarity opposite to that of the second conductivity type carry current. First insulated gate field effect transistor (1, 1) and second complementary insulated gate field effect transistor (2, 2) in which carriers of the second conductivity type carry current The effect transistor section (65) is in contact with the regions of the first complementary insulated gate field effect transistor section (65) where the channels of the two second type insulated gate field effect transistors (2, 2) are formed. A second second bipolar transistor (3) having a collector region and having a second conductivity type carrier carrying a main current.
Type bipolar junction transistor section (66) and a region where a channel is formed in contact with the collector region of the second type bipolar junction transistor (3), and two carriers of the second conductivity type transport current. A second complementary type consisting of a second type insulated gate field effect transistor (4, 4) and two first type insulated gate field effect transistors (5, 5) in which carriers of the first conductivity type carry current. Insulated gate field effect transistor section (67) and second second composed of four second type insulated gate field effect transistors (68, 68, 73, 73) in which carriers of the second conductivity type carry current.
A master slice type semiconductor integrated circuit device, comprising a basic cell in which a type insulated gate field effect transistor section (74) is sequentially aligned in a predetermined first direction. 9. Carriers of the second conductivity type transport current 4.
Second type insulated gate field effect transistors (63, 6)
A first second type insulated gate field effect transistor section (72) consisting of 3, 71, 71) and two first types in which carriers of a first conductivity type having a polarity opposite to that of the second conductivity type carry current. First insulated gate field effect transistor (1, 1) and second complementary insulated gate field effect transistor (2, 2) in which carriers of the second conductivity type carry current The effect transistor section (65) is in contact with the regions of the first complementary insulated gate field effect transistor section (65) where the channels of the two second type insulated gate field effect transistors (2, 2) are formed. A second second bipolar transistor (3) having a collector region and having a second conductivity type carrier carrying a main current.
Type bipolar junction transistor section (66) and a region in which a channel is formed in contact with the collector region of the second type bipolar junction transistor (3), and two carriers of the second conductivity type transport current. A second complementary type consisting of a second type insulated gate field effect transistor (4, 4) and two first type insulated gate field effect transistor (5, 5) in which carriers of the first conductivity type carry current. A second second structure comprising an insulated gate field effect transistor section (67) and four second type insulated gate field effect transistors (68, 68, 73, 73) in which carriers of the second conductivity type carry current.
Type insulated gate field effect transistor section (74) is sequentially aligned in a predetermined first direction, and 1 or 2 is arranged at an arbitrary position.
A master slice type semiconductor integrated circuit device, comprising a basic cell in which the above impedance elements are arranged.