JPS6265439A - Gate array type semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To scale up the scale of a circuit constituted by using fundamental cells of a predetermined kind as main bodies without lowering the degree of integration of the circuit by organizing an excess section in the circuit by employing fundamental cells of a different kind and forming the expanding section of the circuit by using the excess of the fundamental cells. CONSTITUTION:A peripheral circuit region ap is formed regularly to the peripheral section of a semiconductor chip 11, and an A cell region aA and a B cell region aB are distributed at a prescribed ratio and shaped in a region on the inside of the region aP. Said A cell region aA consists of four elements advantageous for forming apparatus such as logic gates, and has pattern structure favorable for shaping the logic gates, and first fundamental cells A mainly functioning as the formation of the logic gates are aligned and disposed. The B cell region aB is composed of six elements advantageous for forming an SRAM, and has pattern structure favorable for shaping the SRAM, and second fundamental cells B mainly serving as the formation of the SRAM are aligned and arranged. Accordingly, when the scale of the SRAM is scaled up, excess SRAM cells, which cannot be constituted sufficiently by the second fundamental cells, are organized of the first fundamental cells leaving a margin by the variation of usage.

Description

[Detailed Description of the Invention] (Summary) For example, a first basic cell mainly used for forming a logic gate and formed with an advantageous number of elements and a pattern structure, and a first basic cell formed mainly for forming a memory circuit and advantageous for this purpose. When attempting to expand the circuit scale of either a logic circuit or a memory circuit by arranging the number of elements and second basic cells formed in a patterned structure on the same substrate at a predetermined ratio, the circuit can be expanded. A gate array type semiconductor integrated circuit that makes it possible to expand the scale of a desired circuit without significantly reducing the degree of integration by forming the remaining basic cells of a type that is not primarily used to form the circuit. circuit.

[Industrial application field]

The present invention relates to a gate array type semiconductor integrated circuit which is versatile and has an improved degree of integration.

As large-scale integrated circuits become larger, there is a remarkable trend towards high-mix, low-volume production.In order to reduce manufacturing costs and shorten manufacturing time, master slice type, ie gate array type, large-scale integrated circuits are often used. It has come to be like this.

It is desirable for gate array type large-scale integrated circuits to have multiple functions, and gate array type large-scale integrated circuits with built-in memory are also available, but the ratio of logic gates to memory and the degree of integration have been greatly improved. There is a need for a general-purpose gate array that can be changed to a certain extent without degrading the performance.

[Prior Art] A conventional gate array type semiconductor integrated circuit incorporating a memory is of a type in which the memory is formed as a fixed pattern in a predetermined area, and only the logic circuit is configured by a master slice.

Therefore, the scale of logic circuits and memory circuits is limited. For example, if you want to expand the scale of logic circuits, even if there is room for memory circuits, you will not be able to use this, so you will have to use an even larger gate array. First, there was a problem of increased manufacturing costs.

Therefore, recently, basic cells having six elements (transistors), which are advantageous for memory formation, are arranged on the entire surface of the substrate.
A general-purpose gate array has been proposed in which a memory and a logic gate are configured using a master slice using this basic cell, thereby allowing circuits to be formed in any scale ratio.

[Problem that the invention seeks to solve]

However, the conventional gate array described above has four n-channel MOS transistors (n-Tr) and two p-channel MOS transistors (p-Tr), which are advantageous for forming, for example, a six-transistor static random access memory (SRAM). Since one type of basic cell consisting of 1000 µm is arranged on the entire surface of the substrate, this basic cell can be used to form a logic gate which is composed of fewer elements than the above-mentioned SRAM, which usually has 2 n-Trs and 2 p-Trs. When formed,
There is a problem in that a large number of unused elements are generated, and the degree of integration of the circuit is reduced accordingly.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention.

As shown in the figure, the above problem is caused by the fact that multiple types of basic cells (A) and (B) with different numbers of elements (Tr) and pattern structures are arranged on one semiconductor substrate, and a predetermined type of basic cell The redundant portion of the circuit (CA) mainly using cells (A) is solved by the gate array type semiconductor integrated circuit according to the present invention, which is formed using different types of basic cells (B).

[For production]

That is, the gate array type semiconductor integrated circuit of the present invention has a first basic cell mainly for forming logic gates, which has a number of elements and a pattern structure that allow logic gates to be formed efficiently, and a memory that can be formed efficiently. A second basic cell, which has a possible number of elements and a pattern structure, and is mainly used to form a memory, is arranged on the same substrate at a predetermined ratio with a high probability of use. The shortage of logic gates caused by configuring using basic cells of In order to cope with the above specification change, the memory shortage caused by the memory configuration using the above-mentioned configuration can be compensated for by configuring the memory using the first basic cell which is not mainly used for memory formation and which has a margin. Since only the surplus generated in the main cell part of either the logic gate or memory is composed of cells that do not mainly form the circuit, the number of surplus elements generated on land is significantly reduced. decreases to

Therefore, the degree of circuit integration is improved, and the circuit scale of the gate array type semiconductor integrated circuit can be expanded.

〔Example〕

The gate array type semiconductor integrated circuit of the present invention will be described below as a four-element basic cell mainly composed of logic gates and a six-transistor static random access memory.
The present invention will be specifically explained using an illustrated embodiment having a six-element basic cell mainly composed of (SRAM).

FIG. 3 is an equivalent circuit diagram (a) and a schematic plan view fbl of the first basic cell in the same embodiment, and FIG. 4 is an equivalent circuit diagram (al) and a schematic plan view (fbl) of the second basic cell in the same embodiment.
bl, Fig. 5 is an equivalent circuit diagram (al and schematic plan view fb of wiring structure) of a two-stage inverter constructed from the same first basic cell, and Fig. 6 is a six-transistor type inverter constructed from the same second basic cell. An equivalent circuit diagram (a) of the SRAM and a schematic plan view (bl) of the wiring structure; FIG. 2 composed of 2 basic cells
FIG. 2 is a schematic plan view showing the wiring structure of a stage inverter.

Identical objects are indicated by the same reference numerals throughout the figures.

In the gate array chip 7 of the above embodiment, as shown in FIG. 2, a peripheral circuit area a is provided at the periphery of the semiconductor chip 11 as usual, and a logic gate is formed in the inner area. A cell area a in which first basic cells A, which are composed of four elements (transistors) that are advantageous for the formation of logic gates and are mainly used to form logic gates, are arranged in an aligned manner; The second semiconductor device is composed of six elements that are advantageous for forming SRAM, has a pattern structure that is advantageous for forming SRAM, and is mainly used for forming SRAM.
B cell areas all are provided in which basic cells 8 are arranged in a predetermined proportion.

In this embodiment, the B cell area a is large and the RAM
It is increasing the capacity.

In FIG. 3, (al indicates an equivalent circuit diagram of the first basic cell mainly consisting of the formation of logic gates arranged in the A cell region a).

As shown in the figure, the first basic cell in this embodiment includes, for example, two independent n-channel transistors TN1
．． It is composed of four elements: TN2 and two independent p-channel transistors (O3) transistors TPI and TP2.

Also, in the same figure (bJ shows the pattern structure,
In the figure, l is an n-type silicon substrate, 2 is a p-type well, 3 is an n'substrate contact 6U region, and 4 is a p'-type upper well contact region 5a, 5b, 5c, and 5d, which will be a source or drain.゛-type regions 6a, 6b, 6c, 6
d is a p-type region 7a which becomes a source or a drain;
7b, 7c, and 7d are gate electrodes.

In this embodiment, the wells are strip-shaped and are formed along the substrate surface at predetermined intervals as usual.

The substrate contact region 3 and the well contact region 4 may be provided for each basic cell as shown in the figure, or may be provided for each plurality of cells.

FIG. 4 shows a second basic cell mainly forming an SRAM arranged in the B cell region a, (al is an equivalent circuit diagram, and fb is a schematic plan view).

The basic cell B is an equivalent circuit diagram (as shown in al, two n-channel MO5I-
A C having transistors TN3 and TN4 and p-channel MOS transistors TP3 and TP4, and configured such that two different pairs of transistors share a gate.
4-element part with MO3 structure and 2 independent n-channel M
It is composed of OS transistors TN5 and TN6.

The schematic plan view fb) shows the pattern structure.
In the figure, l is an n-type silicon substrate, 2 is a p-type well, 3 is an n° type substrate contact) 8i area, and 4 is a p-type substrate.

Type well contact area, 5e, 5f, 5g, 5h, 5
i, 5j, and 5 have n-type regions 6e that become sources or drains.

6f and 6g are p'-type regions 7c and 7f, which serve as sources and drains, respectively, and are n-channel transistors and p-type regions 7c and 7f, respectively.
Gate electrode common to channel transistors, 7g, 7
h indicates an independent gate electrode.

The first basic cell shown in FIG. 3 mainly includes a logic circuit as described above.

FIG. 5 shows an equivalent circuit diagram (a) of a two-stage inverter configured with the first basic cell and a schematic plan view (b) of its wiring structure.
) is shown.

In the figure, 8 is a wiring made of aluminum or the like formed by the master slicing method, 9 is a wiring connection part, and ■. . VS3 is a high potential power supply, VS3 is a low potential (ground) power supply, Vin is an input end, Vout is an output end, and other symmetrical objects are represented by the same symbols as in FIG. 3.

The second basic cell shown in FIG. 4 mainly includes a memory circuit as described above.

FIG. 6 shows an equivalent circuit diagram (al) of a six-transistor type SRAM configured with the second basic cell and a schematic plan view (bl) of its wiring structure.

In the figure, 8 is a wiring formed by master slicing method etc., 9 is a wiring connection part, VDD is a high potential power supply, V33 is a low potential (ground) power supply, -1 is a word line, BL is a bit line, Other objects are designated by the same reference numerals as in FIG.

For example, if you want to form an integrated circuit with a reduced number of logic gates and increased SRAM capacity compared to the normal configuration due to changes in specifications, or if you want to form an integrated circuit with reduced SRAM capacity and increased logic circuit scale, etc. This becomes possible with the gate array shown in this embodiment.

That is, when expanding the scale of the SRAM, the extra SRAM cells that cannot be configured by the second basic cells are configured by the first basic cells that have a surplus due to the above change in use.

FIG. 7 schematically shows the wiring structure in this case.

As shown, two first basic cells A1 and A2 are used for one SRAM, and the n-channel transistor TNII and the n-channel transistor T of the basic cell A,
By connecting the gates of PII, n-channel transistor TN12, and n-channel transistor TP12 in common, and performing wiring similar to that shown in FIG. 6, a transfer gate (TN
5. TN6) are formed, and the n-channel transistors TN21 and TN of basic cell A2 are formed.
22 are connected as transfer gates corresponding to TN5 and TN6 in FIG. 6 to form a six-transistor type SRAM. In addition, in the same figure, 15a-15d and 25
a to 25d are n° type regions 16a to 16d, which become sources or drains, and p' type regions 17a to 17d, and 26a to 26b, which become sources or drains.
7a to 27d indicate gate electrodes, and the same symbols as in FIG. 6 are used for the other symbols.

Also, when reducing the capacity of the SRAM and increasing the scale of the logic circuit, as shown in the schematic plan view of the wiring structure shown in Figure 8,
The two sets of n-channel transistors and n-channel transistors TN13 and TP13 and TN14 and TP14, which share the gate, arranged in the second basic cell B are connected as shown in FIG. A two-stage inverter similar to that shown in is formed. At this time, independent n-channel transistors TN15 and TN16 are not used.

In the same figure, n-type regions 16e-16g that become sources or drains are included in 15e-15, and p-type regions 17e and 17f that become sources or drains are n-type regions 16e-16g that become sources or drains.
The gate electrodes 17g and 17h are common to the channel transistor and the n-channel transistor, respectively, and individual gate electrodes are used. Reference numerals other than the above are the same as in FIG. 5 and FIG. 6.

In the above embodiment, when forming a 6-transistor SRAM with the first basic cell A, the first basic cell 2
two n-channel transistors TP21 and TP22 for each second elementary cell and, if a logic gate is formed in the second elementary cell B, two n-channel transistors TN15 and TN16 for one second elementary cell B. However, since such quantitative specification changes are usually made in a small proportion of the original circuit scale of the integrated circuit, the above does not significantly reduce the circuit integration scale.

In the gate array according to the present invention, as in the above embodiment, a plurality of types of general-purpose basic cells are arranged, so the specifications are changed to expand some functions of the gate array type semiconductor integrated circuit. In this case, all the basic cells in the gate array can be used interchangeably to cope with this, so there is no need to use a larger gate array, leading to shorter delivery times and lower costs.

In the above embodiment, two types of basic cells are arranged, but it is of course possible to arrange three or more types of basic cells.

〔Effect of the invention〕

As explained above, according to the present invention, a versatile gate array is provided in which a decrease in circuit integration degree is suppressed, and therefore manufacturing costs can be reduced when changing the specifications of a gate array type large-scale integrated circuit. This has the effect of shortening the manufacturing delivery time.

[Brief explanation of drawings]

1 is a schematic plan view showing the principle of the present invention, FIG. 3 is an equivalent circuit diagram (al) and a schematic plan view (BL) of the first basic cell in the same embodiment, and FIG. 4 is a schematic plan view (BL) of the first basic cell in the same embodiment. The equivalent circuit diagram (al and schematic plan view) of the second basic cell in
b), Fig. 5 is an equivalent circuit diagram (al) of a two-stage inverter constructed from the same first basic cell and a schematic plan view (bl) of the wiring structure, and Fig. 6 is a six-transistor inverter constructed from the same second basic cell. Figure 7 is a schematic plan view showing the wiring structure of a 6-transistor type SRAM constructed from the same first basic cell; It is a schematic plan view showing the wiring structure of a two-stage inverter configured with a second basic cell. p9 type well contact region, 5a to 5, 15a to 15, 25a to 25d are n
"Mold area, 6a~6g, 16a~16g, 26a~
26d are p° type regions 7a to 7h, 17a to 17h,
27a to 27d are gate electrodes, 8 is a wiring, A, A+, Az are first basic cells, B is a second basic cell, CA is a circuit formed by the first cell, Tr is an element, and a and a are Peripheral circuit area, aa is first cell array area, a is second cell array area, TNI to TN6. TN11-TN16. TN21. TN
22 is an n-channel MO3) transistor, TPI to TP4. TPII to TP14 are p-channel MOs
S transistor, VDIll is a high potential power supply, VSS is a low potential power supply, 2, , , are input terminals, V out is an output terminal, sushi is a word line, and BL and BL are bit lines.

Claims (1)

[Claims] A plurality of types of basic cells (A) and (B) having different numbers of elements (Tr) and pattern structures are respectively arranged on one semiconductor substrate, and a predetermined type of basic cell (A) is arranged on one semiconductor substrate. A gate array type semiconductor integrated circuit characterized in that a surplus portion of a circuit (C_A) configured using a main cell is configured using a different type of basic cell (B).