JPH07130876A - Static memory cell - Google Patents

Abstract

PURPOSE:To realize a static memory cell wherein a wide line space of a bit line can be acquired, increase of capacity across bit lines and bit line resistance can be restrained, a fine Al wiring can be readily processed when a bit line is formed of Al and reliability of a wiring can be improved. CONSTITUTION:In an SRAM cell, a gate GTWT of word transistors WT1, WT2 and gates GTDT1, GTDT2 of a driver transistor are arranged approximately parallel, each of the gates GTWT, GTDT1, GTDT2 is arranged approximately vertical to a bit line direction and the GTWT of the word transistors WT1, WT2 and the gates GTDT1, GTDT2 of a driver transistor are formed of another conductive layer. Thereby, it is possible to restrain increase of capacity across bit lines and bit line resistance, to readily process bit lines BL, BL- and to improve wiring reliability.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a static random access memory (SRAM).
ry) and other static storage cell cell pattern structures.

[0002]

2. Description of the Related Art FIG. 18 is a diagram showing an equivalent circuit of a TFT load type SRAM cell. In FIG. 18, WL is a word line, BL, BL Is a bit line, V _DD is a power supply voltage, LT
₁ and LT ₂ are P-type metal oxide semiconductors (MOS; Metal Oxide S
DT ₁ and DT ₂ are driver transistors made of N-type MOS transistors, and WT ₁ and WT ₂ are word transistors made of N-type MOS transistors.

In this SRAM, the load transistor LT is used.
₁And driver transistor DT₁Drains of
The gates are connected to each other to form a first inverter,
Load transistor LT₂And driver transistor DT
₂The drains and the gates of the
An inverter is configured and is the output of the first inverter
First node n₁And the drive that will be the input to the second inverter
Iva transistor DT ₂Is connected to the gate of the second
The second node n, which is the output of the inverter₂And the first inn
Driver transistor DT that is the input of the burner₁The game
Are connected to each other to form a basic memory cell.
In this SRAM, the first node n₁Is a bit line
Word transistor WL for BL₁Operatively
Connected to the second node n₂Is the bit line BL Against
Word transistor WL₂Operatively connected by
It Also, each word transistor WT₁, WT₂The game
Connected to the word line WL.

In such an SRAM cell, a cell pattern layout called a split word line cell has been conventionally used.

FIG. 19 is a layout diagram showing a cell pattern structure of the spirit word line cell. In FIG. 19, DUF ₁ and DUF ₂ represent diffusion layers.

The spirit word line cell is shown in FIG.
As shown, the bit lines BL, BL 2 in the direction perpendicular to
Word line WL₁, WL₂Is arranged, the diffusion layer DU
F₁, DUF₂Word Transis in the overlapping area with
Data WL₁, WL₂Are formed and two word lines W are formed.
L₁And WL₂Between the bit lines BL, BL Distribution of
Driver transistor DT in the horizontal direction₁, DT₂Placed
Has been. That is, this memory cell
Dista WL₁, WL₂Gate and driver transistor
DT₁, DT₂And the gate of are arranged almost vertically,
The cells were formed long in the bit line direction. this is,
Not only TFT type SRAM but also high resistance load type SRAM
The same is true.

[0007]

However, in the above-mentioned conventional cell pattern structure, as shown in FIG.
Assuming that the minimum design rule is F (μm), the short side length of the memory cell size is about 5F (μm) and the long side length is about 10F (μm).
Therefore, in order to pass two bit lines through the short side length of 5F (μm), the line space of the bit lines is 5F / 4 = 1.
It becomes as thin as 25F (μm).

For example, in the 16MSRAM generation, since the minimum design rule F = 0.4 μm, the short side length of the memory cell size to 5 F = 2.0 μm the long side length of the memory cell size to 10 F = 4.0 μm Line space ~ 1.25F = 0.5
.mu.m, and the bit line space is reduced.

In such a bit line having a small space,
An increase in capacitance between bit lines becomes a problem. In addition, a bit line is usually formed by using a processing technique such as lithography or etching.
It is formed by 1 layer, but using these processing techniques, 0.5
It is difficult to form a thin Al pattern of μm, and there is a problem that the reliability of the thin Al wiring is deteriorated. At the same time, the increase in resistance of the thin bit line was a problem.

The present invention has been made in view of the above circumstances, and an object thereof is to allow a wide line space of bit lines, suppress an increase in capacitance between bit lines and an increase in bit line resistance, and process a bit line. An object of the present invention is to provide a static memory cell that is easy and can improve the reliability of wiring.

[0011]

In order to achieve the above object, according to the present invention, the input and output of the first and second inverters each consisting of a load element and a driver transistor are connected, and the first and second inverters are connected. A static memory cell operatively connected to the first and second bit lines by word transistors, respectively.
The gate of the driver transistor and the gate of the word transistor are arranged substantially parallel to each other, and these gates are arranged substantially perpendicular to the bit line direction.

Further, in the present invention, the gate of the driver transistor and the gate of the word transistor are formed of different conductive layers.

Further, in the present invention, the gates of the two word transistors in one cell are separated by the layer of the gates and are connected by the upper conductive layer.

[0014]

According to the present invention, for example, in the SRAM cell pattern, the gate of the driver transistor and the gate of the word transistor are formed of different conductive layers, and these gates are arranged substantially perpendicular to the bit line direction. A cell pattern long in the word line direction can be realized. As a result, the line space of the bit line can be increased.

Further, according to the present invention, for example, an SRAM
In the cell pattern, the gate of the driver transistor and the gate of the word transistor are arranged substantially parallel to each other and substantially perpendicular to the bit line direction, and the word line is formed in a layer different from the word transistor gate. Also, a cell pattern long in the word line direction can be realized. As a result, the line space of the bit line can be increased.

[0016]

[First Embodiment] FIG. 1 is a layout diagram showing a first embodiment of a cell pattern structure of an SRAM according to the present invention.
18 and 19 described above are designated by the same reference numerals. That is, BL, BL Is the bit line, D
UF ₁ and DUF ₂ are diffusion layers, GT _DT1 and GT _DT2 are gates of driver transistors, WT ₁ and WT ₂ are word transistors, and GT _WT is a word transistor gate.

As shown in FIG. 1, the memory cell according to this embodiment has the gate G of the word transistors WT ₁ and WT ₂ .
T _WT and the gate of the driver transistor GT _DT1 , GT
_DT2 and the gates GT are arranged substantially parallel to each other.
_WT , GT _DT1 and GT _DT2 are in the bit line direction (vertical direction in the figure)
And are arranged vertically. The gates GT _{WT of} the word transistors WT ₁ and WT ₂ and the gates GT _DT1 and GT _{DT2 of the} driver transistors are formed of different conductive layers, and the gates GT _{WT of the} word transistors WT ₁ and WT ₂ are formed.
Are continuously formed without being separated.

As described above, this cell is provided with each gate GT _WT , G
Since T _DT1 and GT _DT2 are arranged substantially parallel to each other and perpendicular to the bit line direction, as shown in FIG. 2, as compared with the conventional memory cell, the word line direction (horizontal direction in FIG. ), The memory cell size is as large as 5F to 10F. Therefore, the bit lines BL, BL that are perpendicular to the word line direction The line and space can be wide. As a result, increase in capacitance between bit lines and increase in bit line resistance can be suppressed, and the bit lines BL, BL When Al is formed, the processing is easy, and the wiring reliability can be improved.

Further, in this cell, as shown in FIG. 2, since the cell size in the bit line direction can be reduced from 10F to 5F in the prior art, the memory cell area does not become larger than that in the prior art. Furthermore, since the gates GT _{WT of} the word transistors WT ₁ and WT ₂ and the gates GT _DT1 and GT _{DT2 of the} driver transistors are formed of different conductive layers, the cell size can be reduced.

Next, a method of constructing the memory cell of FIG. 1 will be described with reference to FIG.
~ It demonstrates using FIG. First, as shown in FIG. 3, regions of diffusion layers DUF ₁ and DUF ₂ are formed. Next, as shown in FIG. 4, the gates GT _DT1 and GT _DT2 of the driver transistor are formed. At this time, the gate material may be a polysilicon single layer. Next, as shown in FIG. 5, the gate GT _{WT of the} word transistor is formed. At this time, the gate material preferably has a polycide structure. The gate GT _{DT1 of the} driver transistor,
It is also possible to form the gate GT _WT of the word transistor before forming GT _DT2 .

Next, ion implantation for forming a diffusion layer was performed.
Then, as shown in FIG. 6, the TFT gate, that is, for the load
Transistor LT₁, LT₂Gate of V_SScontact
Contact hole CNT to pad_LT1, CNT_LT2，
CNT_VSSAnd polysilicon layer GT_LT1, GT_LT2，
PAD_VSSTo form. Next, as shown in FIG.
V_DD, Contact hole CN to TFT channel
T _CH1, CNT_CH2And polysilicon layer CHP₁, C
HP₂To form. Next, as shown in FIG._SS,
Contact hole CN to contact pad
T_VSS, CNT_BLPAnd polycide layer POL_VSS, P
AD_BLTo form. Next, as shown in FIG.
BL, BL Contact CNT_BL, CNT _BL And
And bit lines BL, BL To form. Through each of the above steps
Then, the configuration of the memory cell of FIG. 1 is completed.

As described above, according to this embodiment,
In the SRAM cell, word transistors WT ₁ and W
The gate GT _{WT of} T ₂ and the gate G of the driver transistor
T _{DT 1} and GT _DT2 are arranged substantially parallel to each other, and these gates GT _WT , GT _DT1 and GT _DT2 are arranged almost perpendicular to the bit line direction, and further, the gates GT _{WT of the} word transistors WT ₁ and WT ₂ are arranged. Gate G of driver transistor
Since T _DT1 and GT _DT2 are formed of different conductive layers, the cell size in the word line direction is increased (-10 F), and the line space of the bit line can be doubled (-2.5 F). ). Further, by forming these gates in different layers, the cell size in the bit line direction becomes smaller (up to 5F), and the memory cell area does not become larger than the conventional one (up to 50F ² ). As described above, the bit line capacitance and the bit line resistance can be reduced to 1/4 and 1/4, respectively.
As a result, increase in capacitance between bit lines and increase in bit line resistance can be suppressed, and the bit lines BL, BL Can be easily processed, and the wiring reliability can be improved.

[0023]

[Embodiment 2] FIG. 10 is a diagram showing a SRAM cell pack according to the present invention.
It is a layout diagram showing a second embodiment of the turn structure.
The memory cell of this embodiment is the same as the memory cell of the first embodiment described above.
Like the word transistor WT₁, WT₂The game
GT_WTAnd the gate GT of the driver transistor _DT1, G
T_DT2And are arranged substantially parallel to each other, and
The gates of the two word transistors are the layers of this gate
Then GT_WT1And GT_WT2Separated into and
Gate GT of the transistor_WT1, GT_WT2But further up
Of polysilicon, polycide, W, Al wiring, etc.
They are connected by a conductive layer formed. In addition, in FIG.
CNT_WT1, CNT_WT2Is a contact with the word line
Shows Tohor.

Next, a method of forming the memory cell of FIG. 10 will be described with reference to FIGS. First, as shown in FIG. 11, regions of diffusion layers DUF ₁ and DUF ₂ are formed. Next, as shown in FIG. 12, the gates GT _DT1 and GT _{DT 2} of the driver transistors and the gates GT _WT1 and GT _WT2 of the word transistors are formed. Next, after ion implantation for forming the diffusion layer is performed, as shown in FIG. 13, the TFT gate, that is, the load transistor L is _passed through the contact holes CNT _LT1 and CNT _LT2.
T ₁ and LT ₂ are formed (note that the load pattern is not shown here). Next, as shown in FIG. 14, V _SS is formed through the contact hole CNT _VSS (note that
The pattern of the V _SS line is not shown here).

Next, as shown in FIG.
Gista's Gate GT_WT1, GT_WT2With the word line on
Contact hole CNT_WL1, CNT_WL2Forming the next
Then, as shown in FIG.
GT_WT1And GT_WT2And are connected by a word line WL. So
Finally, as shown in FIG. 17, the connection with the bit line is
Tact Hall CNT _BL, CNT _BL After forming
Line BL, BL To form. Figure through the above steps
The configuration of 10 memory cells is completed. In addition, the above
Before opening the tact hole, all
There is Seth. Also, TFT load, V_SSLine, word line shape
The order of formation does not necessarily have to be this order.

Also in this embodiment, since the gates GT _DT1 and GT _{DT2 of} the driver transistors and the gates GT _WT1 and GT _{WT2 of the} word transistors are arranged perpendicularly to the bit line direction, the cell size in the word line direction is set. Can be increased (~ 10F) and the line space of the bit line can be increased (~ 2.5F). Further, by providing the word line WL separately from the gate of the word transistor, the cell size in the bit line direction becomes smaller (up to 5F), and the memory cell area does not become larger than the conventional one (up to 50F ^2). ).

[0027]

As described above, according to the present invention,
A cell that is long in the word line direction can be formed. As a result, the line space of the bit line can be widened, the increase in the capacitance between bit lines and the increase in the bit line resistance can be suppressed, and the bit line B
L, BL Can be easily processed, and the wiring reliability can be improved. In addition, restrictions on design rules for element isolation can be relaxed.

[Brief description of drawings]

FIG. 1 is a layout diagram showing a first embodiment of a cell pattern structure of an SRAM according to the present invention.

FIG. 2 is a diagram showing a cell size, a cell area, a bit line, and a space between the cell of the present invention and the conventional cell.

3 is an explanatory diagram of a method of configuring the memory cell of FIG. 1, showing a step of forming a diffusion layer.

FIG. 4 is an explanatory diagram of a method of configuring the memory cell of FIG. 1, showing a step of forming a gate of a driver transistor.

5 is an explanatory diagram of a method of configuring the memory cell of FIG. 1, showing a step of forming a gate of a word transistor.

FIG. 6 is an explanatory diagram of a method of configuring the memory cell of FIG.
It is a figure which shows the formation process of the pad of a T gate and a V _SS contact.

[7] an explanatory view of the configuration method of the memory cell of FIG. 1, V _DD
6A and 6B are diagrams showing a process of forming a TFT channel.

[8] In illustration of how to configure the memory cell of FIG. 1, V _SS
FIG. 6 is a diagram showing a step of forming a pad of the bit contact and the bit contact.

9 is an explanatory diagram of a method of configuring the memory cell of FIG. 1, showing a step of forming a bit line.

FIG. 10 is a layout diagram showing a second embodiment of the cell pattern structure of the SRAM according to the present invention.

11 is an explanatory diagram of a method of configuring the memory cell of FIG.
It is a figure which shows the formation process of a diffusion layer.

12 is an explanatory diagram of a method of configuring the memory cell of FIG.
It is a figure which shows the formation process of the gate of a driver transistor and a word transistor.

13 is an explanatory diagram of a method of configuring the memory cell of FIG.
It is a figure which shows the formation process of the contact hole with TFT.

14 is an explanatory diagram of a method of configuring the memory cell of FIG.
It is a figure which shows the formation process of the contact hole with V _SS .

15 is an explanatory diagram of a method of configuring the memory cell of FIG.
It is a figure which shows the formation process of the contact hole with a word line.

16 is an explanatory diagram of a method of configuring the memory cell of FIG.
It is a figure which shows the formation process of a word line.

17 is an explanatory diagram of a method of configuring the memory cell of FIG.
It is a figure which shows the formation process of a bit line.

FIG. 18 is a diagram showing an equivalent circuit of a TFT load type SRAM cell.

FIG. 19 is a layout diagram showing a cell pattern structure of a spirit word line cell.

[Explanation of symbols]

WL ... Word line BL, BL ... bit lines DT _1, DT ₂ ... driver transistor GT _DT1, GT _DT2 ... gate WT _1, WT ₂ ... word transistors GT _WT1, GT _WT2 ... word gate of the transistor DUF _1, DUF ₂ ... diffusion layer of the driver transistor

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[Procedure amendment]

[Submission date] March 11, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction content]

The spirit word line cell is shown in FIG.
As shown, the bit lines BL, BL 2 in the direction perpendicular to
Word line WL₁, WL₂Is arranged, the diffusion layer DU
F₁, DUF₂Word Transis in the overlapping area with
Data WL₁, WL₂Are formed and two word lines W are formed.
L₁And WL₂Between the bit lines BL, BL Distribution of
Driver transistor DT in the horizontal direction₁, DT₂Placed
Has been. That is, this memory cell
Dista WL₁, WL₂Gate and driver transistor
DT₁, DT₂And the gate of are arranged almost vertically,
Long in bit line directionIWas configured in Le. This is T
Not only FT type SRAM but also high resistance load type SRAM
The same is true.

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Correction target item name] Figure 8

[Correction method] Change

[Correction content]

[Figure 8]

Claims (3)

[Claims] 1. Inputs and outputs of a first and a second inverter, which are composed of a load element and a driver transistor, are connected to each other, and outputs of the first and the second inverters are word transistors to form first and second bit lines, respectively. A static storage cell operatively connected to the gate of the driver transistor and the gate of the word transistor are arranged substantially parallel to each other, and these gates are arranged substantially perpendicular to the bit line direction. A static storage cell characterized by being present. 2. The static memory cell according to claim 1, wherein the gate of the driver transistor and the gate of the word transistor are formed of different conductive layers. 3. The static storage cell according to claim 1, wherein the gates of two word transistors in one cell are separated by a layer of the gates and are connected by a conductive layer as an upper layer.