JPH07130877A - Complete cmos type static memory cell - Google Patents

Abstract

PURPOSE:To be hardly affected by mask alignment, to enable low voltage operation and to realize reduction of a cell size. CONSTITUTION:In a complete CMOS type SRAM cell, a gate of word transistors WT1 and WT2 is formed of one word line ML. A gate GT1 of a loading transistor LT1 and a driver transistor DT1 constituting a first inverter is formed at one side of the word line. A gate GT2 of a loading transistor LT2 and a driver transistor DT2 constituting a second inverter is formed in the other side of the word line. The word line WL is arranged approximately at a center of a cell, and the word line WL and each of the gates GT1, GT2 are arranged approximately parallel. Thereby, it is possible to constitute a symmetrical type cell, to be hardly affected by mask alignment and to reduce a memory size.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a static random access memory (SRAM).
ry) and other static memory cells, especially complete CMOS (Complementary Metal Oxide Semiconductor)
The present invention relates to a cell pattern structure of a static memory cell.

[0002]

2. Description of the Related Art FIG. 11 is a diagram showing an equivalent circuit of a complete CMOS type SRAM cell. In FIG. 11, WL is a word line, BL, BL Is a bit line, V _DD is a power supply voltage, L
T ₁ and LT ₂ are load transistors composed of P-channel MOS (hereinafter referred to as PMOS) transistors, and D 1
T ₁ and DT ₂ are driver transistors composed of N-channel MOS (hereinafter referred to as NMOS) transistors, WT
Reference numerals ₁ and WT ₂ respectively represent word transistors composed of NMOS transistors.

In this SRAM, the load transistor LT is used.
₁And driver transistor DT₁Drains of
The gates are connected to each other to form a first inverter,
Load transistor LT₂And driver transistor DT
₂The drains and the gates of the
An inverter is configured and is the output of the first inverter
First node n₁And the drive that will be the input to the second inverter
Iva transistor DT ₂Is connected to the gate of the second
The second node n, which is the output of the inverter₂And the first inn
Driver transistor DT that is the input of the burner₁The game
Are connected to each other to form a basic memory cell.
In this SRAM, the first node n₁Is a bit line
Word transistor WL for BL₁Operatively
Connected to the second node n₂Is the bit line BL Against
Word transistor WL₂Operatively connected by
It Each word transistor WT₁, WT₂The gate is
It is connected to the ground line WL.

In such a complete CMOS type SRAM cell, conventionally, a cell pattern layout called an asymmetrical cell or a split word line cell has been adopted.

FIG. 12 is a layout diagram showing a cell pattern structure of the spirit word line cell. In FIG. 12, DUF ₁ and DUF ₂ represent diffusion layers.

The spirit word line cell is shown in FIG.
As shown, the bit lines BL, BL 2 in the direction perpendicular to
Word line WL₁, WL₂Is arranged, the diffusion layer DU
F₁, DUF₂Word Transis in the overlapping area with
Data WL₁, WL₂Are formed and two word lines W are formed.
L₁And WL₂Bit line BL, BL between In the placement direction
Driver transistor DT₁, DT₂Is located
It That is, this memory cell is a word transistor
WL₁, WL₂Gate and driver transistor D
T₁, DT₂The gates of the
The cells were long in the line direction.

[0007]

However, in the asymmetric type cell, a full CMOS type SRAM cell, that is, T
In the case of the FTPMOS load type cell, it is disadvantageous for low voltage operation due to the fluctuation of the element characteristics due to the mask misalignment. That is, if the characteristics of the elements in the cell vary, especially if the characteristics of the paired elements in one cell are different, it does not operate as an SRAM cell when the voltage is lowered (1.5 to 2.0 V). There was a problem.

Further, in the case of the spirit word line type cell, as described above, two word lines W are set in the memory cell.
Since L ₁ and WL ₂ are arranged, there is a problem that the memory cell size becomes large.

The present invention has been made in view of the above circumstances, and an object thereof is a complete CMOS static device which is hardly affected by mask alignment, can operate at a low voltage, and can reduce the cell size. To provide a memory cell.

[0010]

In order to achieve the above object, according to the present invention, the input and output of the first and second inverters composed of a PMOS transistor and an NMOS transistor are connected to each other, and the first and second inverters are connected. Output of each is operatively connected to the first and second bit lines by word transistors, and the gate of each word transistor is connected to a word line arranged substantially parallel to the bit line. In the cell, the gate of the word transistor is formed by one word line, and the gates of the PMOS transistor and the NMOS transistor of the first inverter are formed on one side of the word line. On the other side,
PMOS transistor and NMO of the second inverter
A gate for the S transistor is formed.

Further, in the present invention, the word line and the gates are arranged substantially parallel to each other.

[0012]

According to the present invention, in the complete CMOS type SRAM cell pattern, the gate of the word transistor is formed by one word line, and the PMOS transistor and the NMOS transistor of the first inverter are formed on one side of the word line. The gate is formed substantially parallel to the word line, and the gates of the PMOS transistor and the NMOS transistor of the second inverter are formed substantially parallel to the word line on the other side of the word line. Can be configured. As a result, the memory size is reduced, and the influence of mask alignment is reduced.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a complete CMOS SRA according to the present invention.
FIG. 13 is a layout diagram showing an example of a cell pattern structure of M, and the same components as those in FIGS. 11 and 12 described above are represented by the same reference numerals. That is, WEL _P1 , WEL _P2
Is P well, WEL _N1 is N well, DUF _N1 and DUF _N2
Is an NMOS diffusion layer, DUF _P1 and DUF _P2 are PMOS diffusion layers, WL is a word line, GT ₁ and GT ₂ are gates of PMOS and NMOS transistors in a CMOS inverter, and WT ₁ and WT ₂ are word transistors composed of NMOS transistors, DT ₁ , DT ₂ are driver transistors composed of NMOS transistors, LT ₁ and LT ₂
Indicates load transistors each of which is a PMOS transistor.

In the complete CMOS memory cell according to this embodiment, as shown in FIG. 1, the gates of the word transistors WT ₁ and WT ₂ are formed by one word line WL and one side of the word line WL (in the drawing) , The lower side with respect to the word line), the gate G of the load transistor LT ₁ and the driver transistor DT ₁ forming the first inverter.
T ₁ is formed, and on the other side of the word line (the upper side with respect to the word line in the drawing), the load transistor LT ₂ and the driver transistor D that form the second inverter.
The gate GT _{2 of} T ₂ is formed and the word line WL
Are arranged substantially in the center of the cell, and the word line WL and the gates GT ₁ and GT ₂ are arranged substantially parallel to each other to form a symmetrical cell.

As described above, since this cell is a symmetrical memory cell, it is hardly affected by mask alignment, and since it has only one word line, the memory size is smaller than that of the spirit word line type cell. It has been reduced.

Next, the method of constructing the memory cell of FIG. 1 will be described with reference to FIG.
~ It demonstrates using FIG. First, as shown in FIG. 2, diffusion layers DUF _N1 and DUF _N2 and DUF _P1 and DUF are provided.
_{The P2} region is defined in the P wells WEL _P1 and WEL _P2 ,
And N well WEL _N1 . Next, as shown in FIG. 3, the first polysilicon layer is used to form a pattern of the word line WL at substantially the center of the cell, and the word line W is formed.
A gate GT _{1 of} a load transistor LT ₁ and a driver transistor DT ₁ which form a first inverter on both sides centering on L, and a gate GT _{1 of} a load transistor LT ₂ and a driver transistor DT ₂ which form a second inverter. Form GT ₂ .

Next, as shown in FIG. 4, the second poly silicon
Contact hole CNT_N21, CNT_N22And C
NT_P21, CNT_P22To form. Contact hole C
NT _N21, CNT_N22Is the drain of the NMOS transistor
Contact to in area, contact hole CN
T_P21, CNT_P22Is the drain of the PMOS transistor
Contact area.

Next, as shown in FIG. 5, second polysilicon layers 2POL ₁ and 2POL ₂ are formed. With these second polysilicon layers 2POL ₁ and 2POL ₂ , driver transistors DT ₁ and DT ₂ which are NMOS transistors which form first and second inverters, and PMO.
Load transistors LT ₁ and L composed of S transistors
The drains of T ₂ are connected to each other.

Next, as shown in FIG. 6, a third polysilico
Contact hole CNT₃₁₁, CNT₃₁₂And C
NT₃₁₃, CNT₃₁₄To form. Contact hole C
NT ₃₁₁, CNT₃₁₂Is connected to the first polysilicon layer.
Tact, contact hole CNT₃₁₃, CNT₃₁₄Is
For contact with the second polysilicon layer.

Next, as shown in FIG. 7, a third polysilico
Contact hole CNT_N31, CNT_N32And C
NT_P31, CNT_P32To form. Contact hole C
NT _N31Is the diffusion layer DUF_N1Above the contact hole CN
T_N32Is the diffusion layer DUF_N2Contact hole CNT on top
_P31Is the diffusion layer DUF_P1Contact hole CNT on top
_P32Is the diffusion layer DUF_P2Respectively formed on top. In addition,
Thus, the third polysilicon contact hole CN
T₃₁₁, CNT ₃₁₂, CNT₃₁₃, CNT₃₁₄And CNT
_N31, CNT_N32, CNT_P31, CNT _P32Another mask
The contact hole CNT is formed in_P31，
CNT_{P3 2}Is a self-aligned contact hole,
CNT that is a contact hole with the first polysilicon layer
₃₁₁, CNT₃₁₂At the same time difficult to etch
It depends.

Next, as shown in FIG. 8, third polysilicon layers 3POL _{1 to} 3POL ₅ are formed. The third polysilicon layer 3POL ₁ is the V _DD line, the third polysilicon layer 3
POL ₂ and 3POL ₃ connect the outputs (drains) and inputs (gates) of the first and second inverters forming the flip-flop to each other. The third polysilicon layers 3POL ₄ and 3POL _{5 form} bit contact pads.

Next, as shown in FIG. 9, first Al contact holes CNT _{Al1 to} CNT _{Al 4} are formed. The contact holes CNT _Al1 and CNT _Al2 are for contact with V _SS , and the contact holes CNT _Al3 and CNT _Al4 are for contact with the bit line.

Next, as shown in FIG. 10, the bit lines BL, BL are formed by the first Al layer. And V _SS line. After this, overpassivation if necessary,
Alternatively, the upper layer Al wiring is formed to complete the configuration of the memory cell of FIG.

As described above, according to this embodiment,
In the complete CMOS type SRAM cell, the gates of the word transistors WT ₁ and WT ₂ are connected to one word line WL.
And the gate GT ₁ of the load transistor LT ₁ and the driver transistor DT ₁ forming the first inverter are formed on one side of the word line WL, and the second inverter is formed on the other side of the word line. Forming the gate GT ₂ of the load transistor LT ₂ and the driver transistor DT ₂ , and arranging the word line WL at approximately the center of the cell, and making the word line WL and the respective gates GT ₁ and GT ₂ substantially parallel to each other. Since they are arranged, a symmetrical cell can be configured, and since there is only one word line, it is less affected by mask alignment, low voltage operation is possible, and the memory size is smaller than that of the spirit word line type cell. There is an advantage that it can be reduced.

[0025]

As described above, according to the present invention,
Complete CMOS that is not easily affected by mask alignment, can operate at low voltage, and can reduce cell size
Type static memory cells can be realized.

[Brief description of drawings]

FIG. 1 is a layout diagram showing an embodiment of a cell pattern structure of a full CMOS SRAM according to the present invention.

FIG. 2 is an explanatory diagram of a method of configuring the memory cell of FIG. 1, showing a step of forming a diffusion layer region.

FIG. 3 is an explanatory diagram of a method of configuring the memory cell of FIG. 1 and is a diagram showing a step of forming a word line (gate of a word transistor) and a gate of a driver transistor.

FIG. 4 is an explanatory diagram of a method of configuring the memory cell of FIG.
It is a figure which shows the formation process of the contact hole for polysilicon layers.

5 is an explanatory diagram of a method of configuring the memory cell of FIG.
It is a figure which shows the formation process of a polysilicon layer.

FIG. 6 is an explanatory diagram of a method of configuring the memory cell of FIG.
It is a figure which shows the formation process of the contact hole for polysilicon layers (for 1st and 2nd polysilicon).

FIG. 7 is an explanatory diagram of a method of configuring the memory cell of FIG.
It is a figure which shows the formation process of the contact hole (for diffusion layers) for polysilicon layers.

FIG. 8 is an explanatory diagram of a method of configuring the memory cell of FIG.
It is a figure which shows the formation process of a polysilicon layer.

FIG. 9 is an explanatory diagram of a method of configuring the memory cell of FIG.
It is a figure which shows the formation process of the contact hole for Al.

10 is an explanatory diagram of a method of configuring the memory cell of FIG. 1, showing a step of forming a first Al layer.

FIG. 11 is a diagram showing an equivalent circuit of a complete CMOS SRAM cell.

FIG. 12 is a layout diagram showing a cell pattern structure of a spirit word line cell.

[Explanation of symbols]

WEL _P1 , WEL _P2 ... P-well WEL _N1 ... N-well DUF _N1 , DUF _N2 ... NMOS diffusion layer DUF _P1 , DUF _P2 ... PMOS diffusion layer WL ... Word line BL, BL ... Bit lines GT ₁ , GT ₂ ... PMOS in CMOS inverter
And gates of NMOS transistors WT ₁ , WT ₂ ... word transistors DT ₁ , DT ₂ ... driver transistors LT ₁ , LT ₂ ... load transistors

Claims (2)

[Claims] 1. Inputs and outputs of first and second inverters each comprising a P-channel metal oxide film semiconductor transistor and an N-channel metal oxide film semiconductor transistor are connected to each other, and outputs of the first and second inverters are word output, respectively. A fully CMOS static storage cell operatively connected to the first and second bit lines by transistors, with the gate of each word transistor connected to a word line located substantially parallel to the bit line, The gate of the word transistor is formed by one word line, and the gates of the P-channel metal oxide semiconductor transistor and the N-channel metal oxide semiconductor transistor of the first inverter are formed on one side of the word line. , On the other side of the word line, the P-channel metal oxide semiconductor of the second inverter. A complete CMOS type static memory cell in which the gates of the body transistor and the N-channel metal oxide semiconductor transistor are formed. 2. The complete CMOS static memory cell according to claim 1, wherein the word line and the gates are arranged substantially parallel to each other.