JPH0334569A - Static type semiconductor storage device - Google Patents

Abstract

PURPOSE:Not only to ease the pattern layout but also to take the ratio of length to width of the gate of an FET large enough by complimentarily forming a pair of P-channel MOS transistors of the conductive film at the second layer and the conductive layer at the third layer. CONSTITUTION:By the polysilicon film at the third layer which is formed through a thin gate insulating film 16 on a polysilicon film at the second layer, the source region SP2, the channel region CP2, and the drain region DP2 of a second P-channel MOS transistor P2 are formed. The gate electrode GP1 of a first P-channel MOS transistor P1 is so formed as to range from this drain region DP2. By the polysilicon film at the fourth layer, which is formed through an insulating film 18 on the polysilicon film at the third layer, VSS wiring 19 in contact with the source region SN1 of a driving transistor N1 is formed.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention relates to a memory cell of a static semiconductor memory device, and in particular to a P-channel insulated gate field effect transistor ( Thin Film Transistor (P-channel MOS transistor)
The present invention relates to the structure of a memory cell using a transistor (hereinafter referred to as TPT).

(Conventional technology) Conventionally, static random access memory (hereinafter referred to as
The circuit of the memory cell of the SRAM (hereinafter referred to as SRAM) is configured as shown in FIG. That is, a first inverter is made up of a polysilicon resistor R1 for a high resistance load element and a driving N-channel MOS (N-channel MOS), and a second inverter is made of a polysilicon resistor R2 and a driving N-channel MOS (N-channel MOS) N2. are cross-connected with the inverters to form a flip-flop, and two complementary data storage nodes (N-channel MOS
) An N-channel MO for a transfer gate is connected between each drain of range metas N1 and N2) D, D and a complementary pair of bit lines (BL, BL) of the memory cell array, respectively.
S transistors T1 and T2 are connected, and each gate of the transfer gate transistors T1 and T2 is connected to a word line WL of the memory cell array.

Note that the above memory cell is, for example, “A Hl-CMO3
11 *8. b 5tatic RAM, Osamu
Mi, nato et, al, p25BDlgest
of' Technical Paper o
f' 19g2 1EEE International
l 5olid-8taie C1rcuitsC
onf'error.

Next, the operation of the memory cell shown in FIG. 4 will be briefly explained. In the data holding state, word line WL is not selected and transfer gate transistors T1 and T2 are turned off. When a memory cell is selected during reading, that is, when the word line WL is selected and activated for a certain period of time, transfer gate transistors T1 and T2 are turned on, and the data held in the data storage node DSD is transferred to the bit line pair. Output to BLSBL. In this case, bit line pair BLS
One of the bit lines BL is pulled down and the bit line pair BL,
A potential difference occurs between BL. And this bit line pair BL
, BL are selected, and the potential difference therebetween is detected and amplified by a sense amplifier circuit (not shown) and becomes a read data output.

Furthermore, when a memory cell is selected during writing, complementary data is written from the bit line pair BL, BL determined by inputting write data.

By the way, in the data holding state, when data "1" is being held, for example, the data storage node D must be held at a high potential and the data storage node D must be held at a low potential. In comparison, the current of the driving transistor N2 in the off state must be several orders of magnitude smaller.

In addition, large-capacity SRAM (for example, 1 M bit SRAM
), it is necessary to achieve a standby current of 2 μA or less as a typical value at room temperature. On the other hand, the holding current consumed by one memory cell is approximately equal to the current flowing through the high resistance load element R1 or R2, as can be seen from the operation in the holding state described above.

Considering the element characteristics of the cell required for the IM bit SRAM, the resistance value of the high resistance load elements R1 and R2 is approximately 3TΩ (3×1012Ω), and the off-state current of the drive transistors Nl and N2 has a margin. If you take 3 digits, you will need 2fA (2xlO” A).In addition, 4
Considering the cell element characteristics required for M-bit SRAM, the resistance value of high resistance load elements R1 and R2 is approximately 12
TΩ, and 0.5 fA is required as the off-state current of the driving transistors N1 and N2. As described above, the 4M bit level is approaching the limit of what can be achieved in terms of device characteristics, and when considering the variations in 4M memory cells, the manufacturing margin is becoming extremely tight.

On the other hand, FIG. 5 shows another conventional memory cell, and compared to the memory cell shown in FIG. 4, the polysilicon resistance R
1 and R2, P channel MOS transistors P1 and P2 are used as high resistance load elements, and these two P channel MOS transistors P1 and P2
Each gate corresponds to two N-channel MOS for driving.
The difference is that the transistors are connected to the respective gates of transistors N1 and N2, and the rest are the same, so the same reference numerals as in FIG. 4 are used.

However, since this memory cell is configured as a flip-flop using CMO8, it is possible to secure a margin in terms of electrical characteristics as described above, but since one cell is configured with six transistors, it is difficult to manufacture at the same level. As long as this technology is used, the cell area will increase, and at the 4M bit level, the chip size will become extremely difficult.

In addition, we have proposed an SRAM cell using TPT as a P-channel MOS transistor for high-resistance load elements.
NT, BOUNCING-NOISE-IMMUNE
ON IMb SRAM.

M,ANDOet,al, 1988 SYMPO9I
UM ON VLSICIRCυITS P49'' or ■'A 25um 2NewPoly-8i PM
O3Loas(PPL) SRAM Ce1l Hav
ingExcellent 5of Erro
r 1mmun1ty, T+Yagganaka
et, al, 19881 EDH (Internatl
onal ElectronDevlees Meet
ing) p4g'', etc. The circuit configuration of the proposed example ■■ SRAM cell is similar to that shown in Fig. 5, but its structure is a conventional cross-connected N-channel MOS A thin polysilicon layer is formed on transistors N, 1, and N2 to form a P-channel MOS transistor P.
1 and P2, respectively.

That is, the SRAM cell of proposal example (3) has a cross-sectional structure as partially shown in FIG. 6, where 60 is a P-type silicon substrate;
61 is an element isolation region selectively formed on the substrate surface; D
NI and SNI are N formed on the substrate surface in the element region.
The drain and source regions of the driving transistor N1 are made of a ten-shaped impurity diffusion region, 62 is a thin gate oxide film on the substrate, GNI is the gate electrode of the driving transistor N1 formed on the gate oxide film 62, and 63 is the drain These are polysilicon wirings formed on the substrate in contact with the region DNI, and these polysilicon wirings 63 and gate electrode GNI are formed of an N◆ type first layer polysilicon film.

64 is an interlayer insulating film (S i 02 film), 69 is a P-shaped second layer polysilicon film formed on the gate electrode GNI via a thin gate insulating film 65, and the first P-channel MOS A source region (V cc power supply wiring>SPI), a channel region CP1, and a drain region DPI of the transistor P1 are formed, and this drain region DP
I is in contact with the drain region DN1 of the driving transistor N1 via a polysilicon wiring 63. 66
is an interlayer insulating film (Si02 film), 67 is a ground potential wiring (Vss wiring) made of silicide, and 68 is an interlayer insulating film (S
i02 film), BL and BL are bit line pairs made of aluminum wiring.

Further, the SRAM cell of proposal example (3) has a cross-sectional structure as shown in FIG. 7, where 70 is a P-type silicon substrate, 71
72 is an N-type well region, 72 is a P-type well region, 73 is an element isolation region (Si02) selectively formed on the substrate surface,
DTI and ST1 are the drain and source regions of the transfer gate transistor T1, which is an n-doped impurity diffusion region formed on the surface of the substrate in the element region, 74 is a thin gate oxide film on the substrate, and GTl is on the gate oxide film 74. a gate electrode of a transfer gate transistor T1 formed in
75 is a first polysilicon wiring formed on the substrate in contact with the drain region DTI;
The polysilicon wiring 75 and gate electrode GTI of
It is formed from a layer of polysilicon film.

76 is an interlayer insulating film, and GPI is a gate electrode of the first P-channel MOS transistor P1 made of a second layer of polysilicon film formed on the gate electrode GNl via the insulating film 77. SPI, CPI, and DPI are the gate electrodes G of this first P-channel MOS transistor P1.
A third layer formed on the PI with a thin gate insulating film 78 interposed therebetween.
These are the source region (V ce wiring), channel region, and drain region of the first P-channel MOS transistor P1 made of a polysilicon film of a second layer, and this drain region DPI is connected to a second polysilicon film made of a second polysilicon film. First polysilicon wiring 75 via silicon wiring 79
is in contact with. Further, 80 is a Vcc wiring made of a third layer polysilicon film. 81 is an interlayer insulating film;
82 is the source region ST of the transfer gate transistor T1
1, 83 is an interlayer insulating film, and BL is a bit line made of aluminum wiring.

According to the structure of the proposed example ■■ as described above, the polysilicon resistor R1 is used as a high resistance load element as shown in FIG.
, R2 can be realized with a cell area comparable to that of a conventional memory cell, and as shown in FIG. P-channel MO whose current supply to the data storage node on the high level side is on
Since this is performed using an S transistor, there is an advantage that the margin against defective leakage defects occurring in a large-capacity memory chip is significantly improved, but there are problems as described below.

That is, the structure of the memory cell of the above-mentioned proposal example (2) has a thin gate insulating film on the first layer of polysilicon film used as the gate electrode of each of the two conventional driving N-channel MOS transistors Nl and N2. 2 TP via 65
A second layer of polysilicon film is formed to be used as the source region, channel region, and drain region of each T.
The first layer of polysilicon film is also used as the gate electrode of each of the two TPTs.

However, such a structure requires (1) TPT gate length/
Since the gate width ratio cannot be made large enough, T
It is difficult to reduce the off-state current of the FT, and (2) it is necessary to form a second layer of polysilicon film on the first layer of polysilicon film with a thin gate insulating film 65 interposed therebetween. 1 to pursue faster memory peripheral circuits
If the second polysilicon film is polycide, it is difficult to form the thin gate insulating film 65.

In addition, in the memory cell of the three-layer polysilicon structure of proposal example (2), two TPT transistors are placed on the first layer of polysilicon film, which is used as the gate electrode of the conventional N-channel MOS transistor, with an insulating film 77 interposed therebetween. A second layer of polysilicon film to be used as each gate electrode is formed, and a third layer of polysilicon film to be used as the source region and drain region of each of the two TPTs is formed on top of it with a thin gate insulating film 78 interposed therebetween. Forms a film.

In such a structure, since the ratio of the gate length/gate width of the TPT can be made sufficiently large, it is easy to realize a structure that reduces the off-state current of the TPT.
In order to increase the speed of memory peripheral circuits, it is easy to polycide the first layer of polysilicon film and form a second layer of polysilicon film thereon with an insulating film 77 interposed therebetween. The number of contact holes between layers increases, and the margin in the contact process decreases.

(Problems to be Solved by the Invention) As mentioned above, when TPT is used as a P-channel MOS transistor for a high-resistance load element of a static memory cell, the TPT is used as the gate electrode of the driving N-channel MOS transistor. Conventional SR with a structure in which the polysilicon film in the third layer also serves as the TPT gate electrode.
AM cells cannot have a sufficiently large TPT gate length/gate width ratio, so it is difficult to reduce the off-state current of the TFT. When the polysilicon film is made into polycide, there is a problem in that it is difficult to form the thin gate insulating film.

Further, the conventional SRAM cell having a three-layer polysilicon structure has a problem in that the number of contact holes between layers within the cell increases, and the margin for the contact process decreases. .

The present invention has been made to solve the above-mentioned problems, and its purpose is to improve the gate length/gate width ratio of the TPT when the TPT is used as a P-channel MOS transistor for a high resistance load element of a static memory cell. It is easy to realize a sufficiently large TPT off-state current, and in order to increase the speed of memory peripheral circuits, the first layer of conductive film is made of polycide and gate insulating film is used. To provide a static semiconductor memory device in which it is easy to form a second conductive film through the film, the number of contact holes between layers within a cell is reduced, and the margin in the contact process is increased. be.

Structure of the Invention] (Means for Solving the Problems) The present invention provides a first P-channel MOS transistor for a high-resistance load element made of a thin film transistor, and a first N-channel MOS transistor for driving. and a second inverter consisting of a second P-channel MOS transistor for a high resistance load element made of a thin film transistor and a second N-channel MOS transistor for driving are cross-connected to form a flip-flop, An N-channel MOS for a transfer gate is connected between two complementary data storage nodes of this flip-flop and a complementary pair of bit lines of the memory cell array.
In a static semiconductor memory device having an array of static memory cells in which a transistor is connected and each gate of the transfer gate transistor is connected to a word line of a memory cell array, the N-channel M
A second conductive film is formed on the first conductive film, which is used as the gate electrode of each OS transistor, with an insulating film interposed therebetween, and a third conductive film is formed on top of this through a thin gate insulating film. A conductive film is formed on the second conductive film, and the source region, channel region, and drain region of the first P-channel MO9 transistor and the second conductive film are formed on the second conductive film.
A gate electrode of a P-channel MOS transistor is formed in the third conductive film, and a source region, a channel region, and a drain region of the second P-channel MOS transistor and a gate electrode of the first P-channel MOS transistor are formed in the third conductive film. It is characterized by the formation of

(Function) Since a pair of P-channel MOS transistors are formed complementary to each other by the second-layer conductive film and the third-layer conductive film, the pattern layout is not only easy, but also the TP
The gate length/gate width ratio of the T can be made sufficiently large, and it is easy to reduce the off-state current of the TPT. Further, even when the first layer conductive film is polycide in order to increase the speed of the memory peripheral circuit, it is easy to form the second layer conductive film thereon with an insulating layer interposed therebetween.

Moreover, as contacts, the drain region of the first P channel MOS transistor formed in the second layer conductive film and the second P channel MOS transistor formed in the third layer conductive film are used as contacts.
It is only necessary to connect the drain regions of the channel MOS transistors to the drain regions of the corresponding driving N-channel MOS transistors via polysilicon wiring, which greatly reduces the number of contact holes between the inner cell layers and improves the contact process. margin increases, and the difficulty in microfabrication and contact hole formation is greatly reduced.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a main part of a planar pattern of one static memory cell in an SRAM memory cell array in which static memory cells are arranged in a two-dimensional grid. In order to clearly display the planar pattern of this memory cell, (a) the first layer of polysilicon film and substrate, (b) the second layer of polysilicon film, and (C) the third layer of polysilicon. and (d) the fourth layer polysilicon film, and the corresponding figures are shown in FIGS. 2(a) to (d).
It is shown in In this case, in FIG. 2(a), the first layer polysilicon film is shown as a solid line and the diffusion region of the substrate is shown as a dotted line, and in FIG. 2(b), the second layer polysilicon film is shown as a solid line and The first layer of polysilicon film is shown by a dotted line, and in FIG. 2(C), the third layer of polysilicon film is shown by a solid line. The polysilicon film of the s2 layer is shown by a dotted line, and in FIG. 2(d), the polysilicon film of the fourth layer is shown by a solid line, and the polysilicon film of the third layer is shown by a dotted line. FIG. 3 shows a cross-sectional structure taken along line A-A in FIG. 1.

That is, the circuit configuration of the memory cell is similar to the circuit configuration shown in FIG. 5, and includes a first P-channel MOS transistor P1 for a high-resistance load element made of TPT and a first N-channel MOS for driving. A first inverter consisting of a transistor N1 and a second inverter consisting of a second P-channel MOS transistor P2 for a high resistance load element made of TPT and a second N-channel MOS transistor N2 for driving are crossed. A flip-flop is formed by connecting two complementary data storage nodes (N-channel MOS transistor N
An N-channel MOS transistor T1 for a first transfer gate and a second transfer gate are connected between the drains (Drains 1 and N2) D and D and a complementary pair of bit lines (BLSBL) of the memory cell array. An N-channel MOS transistor T2 is connected thereto, and each gate of these transfer gate transistors T1 and T2 is connected to a word line WL of the memory cell array.

Next, the structure of the above memory cell will be explained. 1° is a P-type silicon substrate, 11 is an element isolation region selectively formed on the substrate surface, and DNl and SNI are N◆-type impurity diffusion regions formed on the substrate surface in the element region. Drain and source regions of N1, D
N2 and SN2 are N formed on the substrate surface in the element region.
The drain region and source region of the second driving transistor N2, DTI and S, which are made of a native impurity diffusion region.
TI is the drain region and source region of the first transfer gate transistor T1, which is composed of N small impurity diffusion regions formed on the substrate surface of the element region, and DT2 and ST2 are N◆ type impurity regions formed on the substrate surface of the element region. These are the drain region and source region of the second transfer gate transistor T2 made of a diffusion region.

Here, the drain region DT1 of the first transfer gate transistor T1 and the drain region DNI of the first driving transistor N1 are formed in series, and are in contact with the drain region DT1 of the first transfer gate transistor T1. A part of the first polysilicon wiring 12 (the contact portion is indicated by 12a) formed on the substrate serves as the gate electrode GN2 of the second driving transistor N2.

Further, the drain region DT2 of the second transfer gate transistor T2 and the drain region DN2 of the second driving transistor N2 are connected by a second polysilicon wiring 13 formed on the substrate (the contact portion is connected to the contact portion 13a and 1
3b), and a part of this second polysilicon wiring 13 serves as the gate electrode GNI of the first driving transistor N1. 14 is a thin gate insulating film (for example, SiO2) on the substrate, WL is a word line formed on this gate insulating film 14, a part of which is the gate electrode GT of the first transfer gate transistor T1.
This serves as the gate electrode GT2 of the first and second transfer gate transistors T2. This word line WL and the first
The polysilicon wiring 12 and the second polysilicon wiring 13 are formed of a first layer polysilicon film.

Furthermore, a second layer of polysilicon film formed on the first layer of polysilicon film with an insulating film 15 interposed therebetween allows the first layer of polysilicon film to be
The source region (V
cc wiring) SPI, a channel region CPI, and a drain region DPI are formed, and a gate electrode GP2 of a second P-channel MOS transistor P2 is formed so as to be continuous with the drain region DPI. The drain region DPI of the first P-channel MOS transistor P1 is in contact with the first polysilicon wiring 12 (the contact portion is indicated by 12b).

A third layer of polysilicon film formed on the second layer of polysilicon film via a thin gate insulating film (for example, 5iO2) 16 forms a source region (V cc wiring) of the second P-channel MOS transistor P2. SF3, a channel region CP2, and a drain region DP2 are formed, and a first P
A gate electrode GPI of channel MOS transistor P1 is formed. The drain region DP2 of the second P-channel MOS transistor P2 is in contact with the second polysilicon wiring 13 (the contact portion is indicated by 13c).

A fourth layer of polysilicon film formed on the third layer of polysilicon film with an insulating film 18 in between makes contact with the source region SNI of the driving transistor N1 (the contact portion is indicated by 19a) at Vss. The arrangement 119 is formed, and the first transfer gate transistor T1
The third polysilicon wiring 20 (the contact portion is shown as 20a) contacts the source region STI of the second transfer gate transistor T2 and the source region S of the second transfer gate transistor T2.
A fourth polysilicon wiring 21 (the contact portion is indicated by 21a) is formed to contact T2.

Note that the Vss wiring 19 is also in contact with the source region SN2 of the driving transistor N2 (the contact portion is not shown). BL is one bit line made of a first layer of aluminum wiring formed on the Vss wiring 19 via an insulating film 22, and is connected to the fourth polysilicon wiring 21 through a contact portion 21b.

Further, 20b is a contact portion between the other bit line BL made of the first layer aluminum wiring and the third polysilicon wiring 20. A second layer of aluminum wiring 24 is formed on the first layer of aluminum wiring with an insulating film 23 interposed therebetween.

In the structure of the memory cell as described above, there is a gate-dedicated layer in which the gate electrodes of each of a pair of P-channel MOS transistors are formed, as in the conventional proposal example
There is no dedicated source/drain layer in which the source and drain regions of the pair of P-channel MOS transistors are formed, and the pair of P-channel MOS transistors are complementarily formed by the second layer polysilicon film and the third layer polysilicon film.
Transistors Pi and P2 are formed.

Therefore, pattern layout becomes easier (,
The gate length/gate width ratio of the TPT can be made sufficiently large, and it is easy to reduce the off-state current of the TPT. Furthermore, even if the first layer of polysilicon film is polycide in order to speed up the memory peripheral circuit, it is not easy to form a second layer of polysilicon film on top of it with the insulating film 15 interposed therebetween. be. Moreover, as contacts, the drain region DPI of the first P channel MOS transistor P1 formed in the second layer polysilicon film and the second P channel MOS transistor formed in the third layer polysilicon film are used as contacts. It is only necessary to connect the drain region DP2 of P2 to the first polysilicon wiring 12 and the second polysilicon wiring 13 correspondingly, and the first P-channel MOS transistor P1 required in the conventional proposal example drain region DPI of and gate electrode GP2 of second P-channel MOS transistor P2.
and the drain region DP2 of the second P-channel MOS transistor P2 and the first P-channel MO
Contact with the gate electrode GPI of the S transistor P1 (two contacts per one memory cell) can be omitted.

As a result, compared to the three-layer polysilicon structure of conventional example (■), the number of contact holes between layers within the cell is significantly reduced, the margin for the contact process is increased, and the difficulty of microfabrication and contact hole formation is greatly reduced. Decrease.

Note that in the structure of the above embodiment, the conductive film in which the source region, channel region, and drain region of the first P-channel MOS transistor are formed and the conductive film in which the gate electrode of the second P-channel MOS transistor is formed are separated. The conductive film in which the source region, channel region, and drain region of the second P-channel MOS transistor are formed is the same layer, and the conductive film in which the gate electrode of the first P-channel MOS transistor is formed is the same. However, the present invention is limited to the above-mentioned embodiments, and includes a conductive film in which the N region is formed and a conductive film in which the source region, channel region, and drain region of the second P-channel MOS transistor are formed. is formed as a separate layer, or a conductive film in which the gate electrode of the first P-channel MOS transistor is formed and the second P-channel MOS transistor
Even in a structure in which the conductive film on which the gate electrode of the S transistor is formed is formed as a separate layer, at least some of the effects of the above embodiments can basically be obtained.

[Effects of the Invention] As described above, according to the present invention, when using a TPT as a P-channel MOS transistor for a high resistance load element of a static memory cell, the ratio of gate length/gate width of the TPT can be made sufficiently large. It is easy to reduce the off-state current of the TPT, and in order to increase the speed of memory peripheral circuits, the first conductive film is made of polycide and the second conductive film is formed through a gate insulating film. It is possible to realize a static semiconductor memory device in which it is easy to form conductive films in multiple layers, and the number of contact holes between layers within a cell is reduced, thereby increasing the margin for the contact process.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a main part of a planar pattern of an SRAM cell according to an embodiment of the present invention, and FIGS.
In order to easily display the planar pattern of the memory cell shown in the figure, it is divided into four layers and each planar pattern is shown.
The figure is a sectional view taken along line A-A in Figure 1, Figures 4 and 5 are circuit diagrams showing a conventional SRAM cell, and Figure 6 is a circuit diagram showing a conventional SRAM cell.
Figure 7 and Figure 7 respectively show an SRAM using a conventional TPT as a P-channel MOS transistor for a high resistance element.
It is a sectional view showing a cell. Pl...first PMOS transistor, P2...second PMOS transistor, N1...first driving transistor, N2...second driving transistor, T
1... First transfer gate transistor, T2...
Second transfer gate transistor, DNI, SNI...
- Drain region and source region of first driving transistor, DN2, SN2...drain region and source region of second driving transistor, GNl...first
gate electrode of the driving transistor (part of the second polysilicon wiring), DTl, ST1... drain region and source region of the first transfer gate transistor, D
T2, ST2...Drain region and source region of the second transfer gate transistor, GN2...Gate electrode of the second driving transistor (part of the first polysilicon wiring), WL...Word line (the gate electrode of the first transfer gate transistor and the gate electrode of the second transfer gate transistor), SPl...the source region of the first P-channel MOS transistor (Vcc wiring), DPI...the Drain region of the first P-channel MOS transistor, CPl...first P-channel MOS
Channel region of transistor, CF2...gate electrode of second P-channel MOS transistor, SF3...
The source region of the second P-channel MOS transistor (V
cc wiring) DP2...2nd P channel MOS
Drain region of transistor, CF2...Channel region of second P-channel MOS transistor, GPI...
- Gate electrode of the first P-channel MOS transistor,
BL, BL... Bit line pair, 10... P-type silicon substrate, 11... Element isolation region, 12... First polysilicon wiring, 12a... Contact of first polysilicon wiring Part, 12b...Contact part of the drain region of the first P-channel MOS transistor, 13...
Second polysilicon wiring, 13a, i3b...Contact part of second polysilicon wiring, 13c...Contact part of drain region of second P-channel MOS transistor, 14...Gate insulating film, 15 ...insulating film,
16... Gate insulating film, 18... Insulating film, 19...
・VSS wiring, 19a...Contact portion between the Vss wiring and the source region of the first driving transistor, 2o...
・Third polysilicon wiring, 20a... Contact portion between the other bit line and the third polysilicon wiring, 21.
...Fourth polysilicon wiring, 21g...Contact portion between the fourth polysilicon wiring and the source region of the 7th second transfer gate transistor, 21b...One bit line and the fourth polysilicon Contact part with wiring, 22.
... Insulating film, 23... Insulating film.

Claims (4)

[Claims] (1) A first P-channel MOS transistor for a high resistance load element consisting of a thin film transistor and a first P-channel MOS transistor for driving.
a first inverter consisting of an N-channel MOS transistor, and a second inverter consisting of a second P-channel MOS transistor for a high resistance load element made of a thin film transistor and a second N-channel MOS transistor for driving. The cross-connections form a flip-flop, and N-channel MOS transistors for transfer gates are connected between two complementary data storage nodes of the flip-flop and a complementary pair of bit lines of the memory cell array, respectively. In a static semiconductor memory device having an array of static memory cells in which each gate of the transfer gate transistor is connected to a word line of a memory cell array, source and drain regions of the first P-channel MOS transistor are formed. and a conductive film on which the gate electrode of the second P-channel MOS transistor is formed are formed as the same layer, and the second P-channel MOS transistor
A static semiconductor memory characterized in that a conductive film in which a source region and a drain region of an OS transistor are formed and a conductive film in which a gate electrode of the first P-channel MOS transistor is formed are formed as the same layer. Device. (2) A second layer of polysilicon film is formed on the first layer of polysilicon film, which is used as the gate electrode of each of the N-channel MOS transistors, with an insulating film interposed therebetween, and a thin gate is formed on this layer. A third layer of polysilicon film is formed with an insulating film interposed therebetween, and a source region, a channel region, a drain region of the first P-channel MOS transistor, and a second P-channel MOS transistor are formed on the second layer of polysilicon film. A gate electrode of a MOS transistor is formed, and a source region, a channel region, and a drain region of the second P-channel MOS transistor and a gate electrode of the first P-channel MOS transistor are formed in the third layer polysilicon film. 2. The static semiconductor memory device according to claim 1, wherein: (3) A first P-channel MOS transistor for a high resistance load element consisting of a thin film transistor and a first P-channel MOS transistor for driving.
a first inverter consisting of an N-channel MOS transistor, and a second inverter consisting of a second P-channel MOS transistor for a high resistance load element made of a thin film transistor and a second N-channel MOS transistor for driving. The cross-connections form a flip-flop, and N-channel MOS transistors for transfer gates are connected between two complementary data storage nodes of the flip-flop and a complementary pair of bit lines of the memory cell array, respectively. In a semiconductor memory device having an array of static memory cells in which each gate of the transfer gate transistor is connected to a word line of a memory cell array, the source region, channel region, and drain region of the first P-channel MOS transistor are The formed conductive film and the source region of the second P-channel MOS transistor
A static semiconductor memory device characterized in that a conductive film in which a channel region and a drain region are formed is formed as a separate layer. (4) A first P-channel MOS transistor for a high resistance load element consisting of a thin film transistor and a first P-channel MOS transistor for driving.
a first inverter consisting of an N-channel MOS transistor, and a second inverter consisting of a second P-channel MOS transistor for a high resistance load element made of a thin film transistor and a second N-channel MOS transistor for driving. The cross-connections form a flip-flop, and N-channel MOS transistors for transfer gates are connected between two complementary data storage nodes of the flip-flop and a complementary pair of bit lines of the memory cell array, respectively. In a semiconductor memory device having an array of static memory cells in which each gate of the transfer gate transistor is connected to a word line of a memory cell array, a conductive film on which a gate electrode of the first P-channel MOS transistor is formed; A static semiconductor memory device characterized in that a conductive film on which a gate electrode of the second P-channel MOS transistor is formed is formed as a separate layer.