JPS63303575A - Generation circuit for reference signal of field - Google Patents

Abstract

PURPOSE:To eliminate influence due to a noise by outputting an equalizing pulse detection signal when the integral value of a synchronizing pulse is approximately a value corresponding to the width of an equalizing pulse, and outputting the reference signal of a field based on the spacing of the equalizing pulse detection signal. CONSTITUTION:In a pulse width detecting means consisting of an integrator 2, a window comparator 3, a threshold setter 4 and a timing generator 5, when it integrates a synchronizing signal, and the integral value is approximately the value corresponding to the width of the equalizing pulse, it outputs the equalizing pulse detection signal. In a pulse spacing detecting means consisting of a pulse spacing detector 6 and an output pulse generator 7, when the spacing of the equalizing pulse detection signal is approximately equal to the spacing of the equalizing pulse, it outputs the reference signal of the field.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field reference signal format circuit suitable for use in, for example, a 1-inch helical VTR for broadcasting using Type C format.

[Summary of the invention]

In a VTR using a type C formant, the present invention integrates each separated synchronization signal, outputs an equalization pulse detection signal when the integrated value approximately corresponds to the width of an equalization pulse, and outputs an equalization pulse detection signal. By outputting the field reference signal when the interval between the output equalization pulse detection signals is approximately equal to the equalization pulse interval, the field reference signal is formed without being affected by any noise. This is how it was done.

[Conventional technology]

In normal video equipment, a vertical synchronization signal is detected from a composite video signal, and in particular, 1.
Among 5-head recording VTRs, 1-head recording VTRs (not recording the vertical synchronization signal part) are permitted.
This type of VTR needs to detect an equalization pulse having a width approximately half that of the horizontal synchronization signal as a vertical synchronization signal, and use it as the vertical synchronization signal (field reference signal).

Conventionally, multiple monostable multivibrators have been used to detect the width of the equalized pulse (for example, in Japanese Patent Application Laid-Open No. 56-506).
In principle, a monostable multivibrator is used to set the timing width, and whether or not the equalization pulse is an equalization pulse is determined based on whether there is a rising or falling edge of the equalization pulse. ing.

For example, as shown in FIG. 4, when a pulse as shown in FIG. 4A is supplied to the first monostable multivibrator, the pulse shown in FIG. A pulse as shown in B is generated, and in synchronization with the rising edge of this pulse, the fourth monostable multivibrator is
If a pulse as shown in Figure C is generated and the pulse shown in Figure 4A rises within this pulse width, that pulse is called an equalization pulse and a layer image.

[Problem that the invention seeks to solve]

By the way, in the case of the above-mentioned method, it is easily affected by noise, and there is a risk that the noise may be mistakenly detected as an equalization pulse.For example, as shown in FIG. 5A, two noises are The first monostable multivibrator generates a pulse as shown in Figure 5B in synchronization with the falling edge of the first noise when riding on the composite synchronization signal at an interval equalized pulse width of . In synchronization with the rising edge of the pulse, the second monostable multivibrator generates a pulse as shown in Fig. 5C, and within this pulse width there is the rise of the second noise shown in Fig. 5A. This will be mistakenly detected as an equalization pulse.

As long as detection is performed by focusing only on the edge of the target pulse, as in this method, such problems are unavoidable, and in order to avoid them, a protection circuit of a certain size is required. It ends up.

This invention has been made in view of the above, and provides a field reference signal forming circuit that can detect equalization pulses and substantially output field reference signals with a simple circuit configuration without being affected by equivalent noise. It provides:

[Means for solving problems]

The field reference signal forming circuit according to the present invention includes a sync signal separation circuit that separates sync signals, and integrates each sync signal separated by the sync signal separation circuit, and the integrated value is approximately the width of an equalized pulse. A pulse width detection means (2 to 5) outputs an equalized pulse detection signal when the pulse width detection means has a corresponding value, and an interval between the equalized pulse detection signal outputted from this pulse width detection means is equal to the interval between the equalized pulses. The pulse interval detection means (6, 7) outputs the reference signal of the fields when the fields are substantially equal.

[Effect]

The pulse width detecting means (2 to 5) integrate the synchronously separated synchronizing signals, and when the integrated value approximately corresponds to the width of the equalized pulse, that is, the first and second threshold levels Thz and Th2 are detected. An equalized pulse detection signal is output when the value is between .

The pulse interval detection means (6, 7) outputs a field reference signal when the interval between the equalized pulse detection signals is approximately equal to the interval between equalized pulses.

Thereby, a reference signal of a desired field can be formed without being affected by noise.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail based on FIGS. 1 to 3.

FIG. 1 shows the configuration of this embodiment, and in the figure,
(11 is an input terminal to which a composite sync signal separated from a video signal is supplied in a sync signal separation circuit (not shown), and each sync pulse included in the composite sync signal from this input terminal (1), The vertical synchronization pulse, horizontal synchronization pulse and equalization pulse are fed to an integrator (2) where they are sequentially integrated.

The integral value integrated by the integrator (2) is supplied to the window comparator (3), where the threshold setter (4) is supplied to the window comparator (3).
) are compared with the first and second threshold levels given in ). The first and second threshold 7L/F levels are set in relation to the horizontal synchronization pulse and the equalization pulse. For example, the first threshold level is greater than the integral value of the equalization pulse and greater than the integral value of the horizontal synchronization pulse. The second threshold level is set to a value greater than O and less than the integral value of the equalization pulse.

Therefore, only the integral value that is smaller than the first threshold level and larger than the second threshold level is imaged as corresponding to the width of the equalization pulse, and is used as the equalization pulse detection signal to output the composite synchronization signal from the input terminal (1). It is output in synchronization with a timing signal from a timing generator (5) responsive to the signal. In other words, (2) to (5) function as pulse width detection means for detecting the width of the equalized pulse.

The equalized pulse detection signal outputted from the window comparator (3) is supplied to a pulse interval detector (6), where it is determined whether the interval of the equalized pulse detection signal is equal to the interval of equalized pulses, If equal, output pulse generator (7)
A field reference signal is outputted to the output terminal (8). In other words, (6) and (7) function as pulse interval detection means for detecting the interval between equalization pulses. Note that once the field reference signal is output, the output pulse generator (7) prevents its input so that the pulse interval detector (6) does not operate again until the next vertical blanking period comes. .

Figure 2 shows an example of the specific circuit configuration of Figure 1.
Input terminal (1) is connected to integrator (2) via buffer (9)
is connected to the input side of the inverter (2a), and the output side of the inverter (2a) is connected to the positive power supply terminal 10B through the resistor (2b), and the inverter (2d) is connected through the resistor (2C). ) is connected to the input side of the

Also, the input side of the inverter (2d) is a capacitor (2e).
grounded via. The output side of the inverter (2d) is grounded to the positive power supply terminal 10B via a resistor (2f) and connected to the input side of the inverter (2h) via a resistor (2g). Further, the input side of the inverter (2h) is grounded via a capacitor (21). Inverter (2
The input side of h) is connected to the positive power supply terminal 10B via a resistor (2j) and grounded via a capacitor (2k). (2a) to (2g), (21) are delay elements for adjusting the timing of comparison in the window comparator (3), and 2h, 23.2
Configure an integrating circuit.

The output side of the integrator (2) is connected to the inverting input terminal of the comparator (3a) of the window comparator (3) and to the non-inverting input terminal of the comparator (3b). The threshold setter (4) consists of resistors (4a), (4b) and (4c) connected in series between the positive power supply terminal 10B and ground.
), the connection point of resistors (4a) and (4b) is connected to the inverting input terminal of comparator (3a), and the connection point of resistors (4b)
) and (4c) are connected to the non-inverting input terminal of the comparator (3b). The connection point between resistors (4a) and (4b) sets a first threshold level Ths, and the connection point between resistors (4b) and (4c) sets a second threshold level Th2. The voltage value integrated for the horizontal synchronization pulse is α, and the voltage value integrated for the equalization pulse is β.
Then, the first threshold level Thz is β
1<α, and the second threshold level Th2 is set to 0, Th2<β.

Each output side of the comparators (3a) and (3b) is connected to one input terminal of the NAND circuit (3c) and (3d), respectively, and each output terminal of the NAND circuit (3C) and (3d) is connected to a NOR circuit (
3e). Furthermore, the timing generator (5) consists of a capacitor (5a), a buffer (5b), and a resistor (5c), one end of the capacitor (5a) is connected to the output side of the buffer (9), and the other end is connected to the output side of the buffer (9). 5
b) is connected to the input side of the buffer (5c) and grounded via the resistor (5c), and the output side of the buffer (5b) is connected to the NAND circuit (
3C) and (3d).

The output side of the window comparator (3) is connected to one input end of the NAND circuit (6a) of the pulse interval detector (6), and the output side of the NAND circuit (6a) is connected to one end of the monostable multivibrator (6b). Connected to the input terminal. The IN stable multivibrator (6b) has a capacitor C1 and a resistor R1 as a time constant that determines the pulse width. The output terminal Q of the monostable multivibrator (6b) is connected to the other input terminal of the next stage monostable multivibrator (6c). One input terminal of the monostable multivibrator (6c) is connected to the positive power supply terminal. The monostable multi-vibration plug (6c) has a capacitor C2 and a resistor R2 as time constants that determine the pulse width.

The output terminal Q of the monostable multivibrator (6c) is connected to the other input terminal of the monostable multivibrator (6b), and the other input terminal of the monostable multivibrator (7a) of the output pulse generator (7) and It is connected to one input terminal of the monostable multivibrator (7b).

One input terminal of the monostable multivibrator (7a) is connected to the positive power terminal B. The monostable multi-bibreak (7a) has a capacitor C3 and a resistor R3 as a time constant that determines the pulse width. The inverted output terminal Q of the monostable multivibrator (7a) is a NAND circuit (6a)
is connected to the other input terminal of the The other input terminal of the monostable multivibrator (7b) is connected to the output terminal of the NAND circuit (6a). Monostable multi-bi break (7b
) has a capacitor C4 and a resistor R4 as a time constant that determines the pulse width. Monostable multivibrator (7
The output terminal Q of b) is connected to the output terminal (8).

Next, the operation of the circuit shown in FIG. 2 will be explained with reference to the signal waveforms shown in FIG.

As is well known, the composite synchronizing signal S1 as shown in FIG. In the vertical blanking period (158), six pulses are inserted in a period of 3H at a period of 0.5H (H: horizontal scanning period) from the end of the video, and a vertical synchronizing pulse (3H
), a period of 3H is inserted again in the same cycle.

When the composite synchronization signal S1 is supplied to the integrator (2), each pulse is integrated in sequence, and an output signal S2 as shown in FIG. 3B is obtained at the output side of the integrated integrator (2). This signal S2 is supplied to the non-inverting input terminal of the comparator (3a) and to the inverting input terminal of the comparator (3b).

The comparator (3a) generates a negative output when the level of the signal S2 is lower than the first threshold level Tht, and generates a positive output when the level is higher than the first threshold level Tht. Further, the comparator (3b) detects that the level of the signal s2 is equal to the second threshold level Th2.
When it is smaller, a positive output is generated; when it is larger, a negative output is generated. The respective outputs of comparators (3a) and (3b) are supplied to NAND circuits (3c) and (3d).

Further, the composite synchronization signal S1 is supplied to the timing generator (5) and differentiated, and a pulse signal S3 as shown in FIG. Get on the side.

This signal S3 is supplied to NAND circuits (3c) and (3d), where it is logically processed with the output signals from comparators (3a) and (3b), further logically processed by a NOR circuit (3e), and then processed by a window comparator (3e). ), an output signal s4 as shown in the third diagram is obtained. That is, the first and second
Only the signal s2 between the threshold level Thx and 1゛h2 is taken out as the output signal s4. This essentially indicates the rising edge of the equalization pulse in the composite synchronization signal si.

Up to this point, we have completed the detection of a pulse signal with the width of the equalization pulse, and next we confirm that this pulse signal is a pulse train with the interval of the equalization pulse. For this purpose, monostable multivibrators (6b) and (6c) are used here to measure the pulse interval. Note that since the above-mentioned noise hardly occurs at this point, there is almost no false detection even if a monostable multivibrator is used.

Now, the signal S4 is supplied to the monostable multivibrator (6b) via the NAND circuit (6a). The i-stable multivibrator (6b) produces an output signal S5 as shown in FIG. 3E, which rises synchronously with the first pulse of the signal S4, continues for a time determined by the time constant of the capacitor C1 and the resistor R1, and then falls. Occur. This output signal S6 is supplied to the next stage monostable multivibrator (6c), and the monostable multivibrator (6c) rises in synchronization with the fall of the output signal S6, and is determined by the time constant of capacitor C2 and resistor R2. An output signal (wind pulse) Ss as shown in FIG. 3F that lasts for a certain period of time and falls is generated.

This wind pulse S@ is converted into a monostable multivibrator (
7b) and during the period of the wind pulse S6 the signal S
If the next pulse after 4 is present, this pulse is imaged with the second equalization pulse and the monostable multivibrator (7b)
An output signal S7 as shown in FIG. 3G is generated on the output side of the field as a field reference signal.

Further, the wind pulse S6 is supplied to the monostable multivibrator (6b) and (7a), and an output signal S8 as shown in FIG. 3H is obtained at the output side of the monostable multivibrator (7a). This output signal S8 is a NAND circuit (
6a) and close its gate. In other words, a pulse with a sufficiently long low level period like the output signal S8 is output, and once the 8 field reference signals are output, the monostable multi-by-break (6b) is repeated twice until the next vertical blanking period. , block the input to the window comparator (3) so that (6c) does not work.

〔Effect of the invention〕

As described above, according to the present invention, each separated synchronization signal is integrated, and when the integrated value is a value corresponding to approximately the width of the equalization pulse, an equalization pulse detection signal is output, etc. Since the field reference signal is output when the interval of the equalization pulse detection signal is approximately equal to the equalization Hals interval, the equalization pulse can be detected without being affected by equalization noise, and the field can be substantially Since a reference signal can be formed and a protection circuit unlike the conventional one is not required, the circuit configuration is also simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit configuration diagram showing an example of the specific circuit shown in FIG. 1, and FIG. 3 is a signal waveform diagram for explaining the operation of FIG. , FIG. 4, and FIG. 5 are diagrams for explaining a conventional example. (2) is an integrator, (3) is a wind cosciparator, (4
) is a threshold setter, (5) is a timing generator, (6) is a pulse interval detector, and (7) is an output pulse generator.

Claims (1)

[Claims] A synchronization signal separation circuit that separates synchronization signals; and a synchronization signal separation circuit that integrates each of the synchronization signals separated by the synchronization signal separation circuit, and when the integrated value is a value approximately corresponding to the width of an equalization pulse. pulse width detection means for outputting an equalized pulse detection signal at a time; and outputting a field reference signal when an interval between the equalized pulse detection signals outputted from the pulse width detection means is substantially equal to an interval between the equalization pulses. 1. A field reference signal forming circuit comprising: pulse interval detection means for detecting a pulse interval.