JPS63302551A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a TFT, which may be thermally treated at a high tempera ture in order to maintain performance thereof and channel length of which is not constrained by the channel length of a transistor on the single crystal substrate side, by forming a polycrystalline Si substrate in the TFT onto the film of a gate and forming the substrate to the same plane shape as the gate film. CONSTITUTION:A MOS transistor shaped to a single crystal Si substrate 1 and a thin-film transistor (TFT) using a gate electrode 5 consisting of polycrystalline Si for the MOS transistor as a common gate and being formed by a polycrystalline Si substrate 7 deposited onto the MOS transistor are pro vided. In a semiconductor device having such laminated structure, the polycrystalline Si substrate 7 in said TFT shaped onto said common gate 5 and formed to the same plane shape as the gate 5 with the exception of a contact section 12 for the gate 5, contact holes 11, 11a shaped near both ends on the polycrystalline Si substrate 7 and formed to an insulator layer 10 deposited onto the polycrystalline Si substrate 7, and source/drain regions 9, 9a in the TFT shaped at the lower positions of the contact holes 11, 11a are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] This invention relates to a stacked structure MOS transistor, that is, an ST
The present invention relates to MOS devices, and particularly relates to an MO5 semiconductor device consisting of a polycrystalline silicon thin film transistor (hereinafter referred to as TPT) stacked on a single crystal silicon transistor.

[Prior Art] As the degree of integration of LSI increases, power consumption within the chip increases. For this reason, the importance of OMO5 (complementary MOS) technology, which has the lowest power consumption, is becoming more and more important.

So-called three-dimensional LSIs, in which polycrystalline silicon transistors (hereinafter referred to as polycrystalline 5ITr) are arranged by depositing polycrystalline silicon on the insulating film of conventional MOS transistors, are CMOS static RAMs and dynamic LSIs with new structures. It is reaching the stage of practical use as RAM.

As a recent example, a three-dimensional LS of “polycrystalline 81 Tr”
Application to I-memory”: Texas Instru
mentsInc, ;Nikkei Electronics, 1
0.7. There is a technique disclosed in p.255 (1985).

Figure 3 shows the stacked CMO shown in this document.
FIG. 2 is an explanatory cross-sectional view of an S-structure semiconductor device.

Unlike conventional bulk CMOS cells (cells in which all transistors are fabricated in a single-crystal silicon substrate), static RA
When used as M, a PMOS transistor as a load overlaps an NMOS transistor, and has a stacked CMOS structure having a common gate electrode.

In the figure, 1 is an 8MO3 single-crystal St p-substrate, 2 and 2a are NMOS type source/drain regions, and 3 is an NMOS
In the gate oxide film (S10□) on the MOS side, 4 is a closed-type channel stopper, and 5 is a gate electrode made of an r-type first layer polycrystalline Sl film. 6 is a field oxide film for element isolation formed of SlO□. The components 1 to 5 above form a normal NMOS transistor.

After forming the above NMOS transistor, 900 to 100
A high temperature oxidation process at 0° C. is performed to form a surface oxide film of the gate electrode 5, thereby forming a second layer gate oxide film 3a. After 2, a polycrystalline Sl film 7, which will serve as a substrate for a thin film transistor (hereinafter referred to as TFF), is deposited on the entire surface, and an n-type channel 8 for PMOS is formed on the gate electrode 5, and an impurity ( By diffusing boron B, etc.) to form source/drain regions 9 and 9a of p-soil walls, a TPT having a PMOS structure with the gate electrode 5 as a common gate is formed.

2, a stacked CMO 8 is formed as a three-dimensional LSI combined with the lower NMOS transistor,
At present, it is reaching the stage where static RAM devices and the like are constructed and put into practical use.

In this case, it has conventionally been generally believed that transistors using polycrystalline Sl as a substrate are not suitable for application to VLSI-class memories as described above.

The reason for this is that due to the influence of grain boundaries, only those with high threshold voltage, low carrier mobility, and high leakage current could be produced.

As a countermeasure to this, some improvements have been made by recrystallizing using new process technologies such as irradiation with laser light or electron beams, and by hydrogenation treatment using a thin polycrystalline St film (about 30 nm). It's here. Even so, at present, characteristics superior to those of single-crystal S1 transistors have not been obtained, but depending on the intended use, it may be sufficient for applications such as static RAM, and there is a reasonable possibility that it will be put into practical use. It's getting bigger.

[Problems to be Solved by the Invention] The polycrystalline S1 transistor in the three-dimensional LSI described above has the following problems due to its structure and process. That is, (1) When forming a gate oxide film, it is necessary to obtain a high-quality film, and for this purpose, a high-temperature gate oxidation process using high-temperature heat treatment at 900 to 1000° C. or higher is necessary.

(2) Therefore, by forming this high-temperature gate oxide film, the source/drain diffusion region of the transistor on the single crystal 81 substrate, that is, the junction or junction, becomes deep, and the MOS
It becomes difficult to set conditions for optimizing transistor characteristics.

(3) As in the above device, when the substrates made of single crystal S1 and polycrystalline Sl have orthogonal patterns, even if the self-alignment method is adopted, the channel length of TPT is I was restricted by the length and decided,
If necessary, for example, to control the punch-through of the TFT, it would be impossible to independently lengthen the length, which would mean degrading the performance of the single-crystal transistor.

This invention was made to solve the above problems, and after the formation of a high temperature gate oxide film, single crystal S
We decided to form source/drain regions of I Tr and polycrystalline St Tr, and heat treatment to maintain TFT performance can be performed at high temperatures without any performance problems, and the TPT channel length is on the single crystal substrate side. The present invention provides a structure and manufacturing method of a semiconductor device that can obtain a TPT that is not restricted by the channel length of a transistor.

[Means for Solving the Problems] A semiconductor device according to the present invention includes depositing TPT made of polycrystalline St on a MOS transistor formed on a single crystal 81 substrate, using a gate made of polycrystalline St as a common gate. In the semiconductor device with the stacked structure formed by the above method, the TPT polycrystalline 81 substrate is provided on the gate film and is formed in the same planar shape as the gate film.
A contact hole is provided in the insulating film near both ends of the substrate, and the polycrystalline 8 below the contact hole is
It is possible to form TPT source/drain regions on one substrate.

Further, in the method for manufacturing a semiconductor device constituting the second aspect of the present invention, before forming the source/drain regions of the MoS transistor on the single crystal Si substrate, the single crystal 81
On the substrate, a first layer of gate oxide film, a first layer of polycrystalline S1 film forming the gate, a second layer of gate oxide film formed by high temperature oxidation, and a source/drain for TPT forming the substrate of the polycrystalline S1 transistor. is formed, a second layer of polycrystalline S1 film and an insulating film are sequentially laminated, and then the first layer described above is formed.
using the gate film of the second layer as a common gate, and the second layer of polycrystalline S1 film as a substrate of a polycrystalline S1 Mo8 transistor;
This substrate is formed on a common gate, and is formed in the same planar shape except for the contact portion of this gate,
After that, after forming the source/drain for the MOSTr formed on the single crystal silicon substrate, an insulating film is deposited, and then the source/drain contact positions near both ends of the polycrystalline 81 substrate and the single crystal Contact holes are formed in the insulating film at source/drain contact positions of the Si substrate and at common gate contact positions.

[Function] In this invention, first, a field oxide film for element isolation (formed by the LOCO3 method) and a first layer gate oxide film on the single crystal 81 substrate side are formed on a single crystal St substrate by oxidation treatment. Later, the first layer of polycrystalline St that forms the gate electrode
A second film is deposited on top of that by high-temperature gate oxidation.
Since a layered gate oxide film is formed, this gate oxide film can be replaced with a high quality oxide film.

On this second gate oxide film, a second
After forming a thin film of polycrystalline Sl with the source/drain regions of the TPT layer, the common gate region and the gate contact region are processed into the same shape, and then the source/drain of the Sl single crystal transistor is formed. In particular, the junction depth of the source/drain region of the single crystal 81 is configured with a desired dimension. Further, with this configuration and process, the channel length of the polycrystalline Si (thin film 91) transistor can be set without being restricted by the channel length of the transistor on the single crystal St side.

As described above, with this configuration and manufacturing method, it is easy to configure a three-dimensional IC using high-quality 0MO5 TPT.

[Embodiment] FIG. 1 is an explanatory diagram of the configuration of a semiconductor device equipped with a TPT showing an embodiment of the present invention, in which (a) is a top view of the main part, and (b)
) is a cross-sectional explanatory diagram. 1 is a p-type substrate of single crystal S1, 3
6 is a first layer gate oxide film, and 6 is a field oxide film for element isolation by LOGOS. Single crystal 8 as above
1 With the substrate 1 pre-processed, the upper surface TPT is formed. Reference numeral 5 denotes a gate electrode made of 81 first-layer polycrystalline layers deposited on the first-layer gate oxide film 3. This gate electrode 5 is doped with highly concentrated impurities and has a low electrical resistance. A type of polycrystalline St is formed.

In this embodiment, a normal NMOS transistor is constructed with the above structure, and 13 and 13a shown in FIG. 1(a) are the source/drain regions of this NMOS, and the first
Although they are not shown in Figure (b) because they are arranged above and below in the direction perpendicular to the paper, Ll shown in Figure (b) indicates the channel width of this NMOS, and therefore, as shown in Figure (a). L2 shown in is the channel length of NMOS.

TPT is formed on the surface of this NMOS transistor, and 3a is a second layer gate oxide film formed on the gate electrode 5, which is oxidized at a high temperature of 900 to 11θ0°C to a thickness of approximately 500 nm. It is formed. 7 is a TPT substrate formed of a second polycrystalline S1 layer. This T
Of the PT substrate 7, 8 is an n-type channel region, 9 and 9
a is a v-type source/drain region. The gate electrode 5 (shared) source/drain regions 9 and 9a constitute a TPT PMOS transistor having the channel region 8 as a channel. This PMO3 and the single crystal S
1 has a common gate 5 with the NMOS transistor formed in
A CMOS is formed through this.

After depositing an insulating film 10 made of an oxide film (SiO7, etc.) on the entire surface of the cell part of this CMOS transistor by CVD, contact holes 11 are formed for the source/drain regions 9 and 9a of the TPT, and a Ha% oxide film 71! +5 conductive hole 12 and single crystal 91 source on substrate 1/
Contact holes 14 and 14a for drains 13 and 13a are formed. Wiring for each electrode is then taken out through the five contact holes.

The structure of the 0MO8 transistor in which TPTs are laminated according to the present invention is characterized in that the TPTs are formed by self-alignment using a TPT substrate.

Next, FIGS. 2(a) to (d) are top views of the main parts and corresponding sectional views of the main parts (a') to (d'),
A method of manufacturing the semiconductor device shown in the embodiment of FIG. 1 will be explained. In the figure, numerals 1 to 14 are the same parts as used in the explanation of FIG.

(2) In FIGS. 2(a) and 2(a'), first, the p-type substrate 1 of single crystal S1 is subjected to preliminary processing by a normal process. That is, after forming a field oxide film 6 for element isolation by LOCOS on the p-substrate 1, oxygen 02
A first layer of gate oxide film 3 is formed to a thickness of about 300 nm by oxidation at 1000° C. in an atmosphere.

Next, polycrystalline St is deposited thereon and a gate film forming the d+ type gate electrode 5 is formed by impurity diffusion.

Furthermore, after performing Dry 0 and high temperature oxidation treatment at 1000° C. again to form a second layer gate oxide film 3a,
After depositing polycrystalline S1 on this by CVD to form a TPT substrate film, a layer is formed by ion implantation in the TPT source/drain region, and an oxide film (SiO□) is formed.
IO is formed by CVD. By the high-temperature heat treatment used in the above process, a high-quality oxide film with good insulation properties can be obtained, especially for the gate oxide film 3a.

After performing the above preliminary processing, a photoresist 15 matching the pattern dimensions of the TPT substrate 7 is applied.

2. Next, as shown in FIGS. 2(b) and 2(b'), the gate oxide film 3 is removed using the photoresist film 15.
After forming patterns of the oxide film 10 and the TFT substrate 7 by dry etching (RIE), the resist film 15 is removed. After this operation, the photoresist film 15 for setting the first gate pattern is formed as shown in the figure.
Apply a.

■ FIGS. 2(c) and 2(c') show the photoresist film 15a and the insulating film 1 on which the TFT region is formed.
This figure shows the state in which the pattern of the gate electrode 5 was formed by dry etching using 0 and then the photoresist film 15a was removed. Through the above operations, the formation of each element region of the TPT and single crystal MOS transistor with the gate electrode 5 as a common gate is completed and the state is reached.

(2) Next, the source/drain for the single crystal MOS transistor is formed. That is, ion implantation is performed using the common gate 5 as a mask.

In this case, the insulating film 10 is used as a mask for ion implantation to prevent impurities from entering the TPT substrate 7 due to ion implantation. In this way, the above (C), (C”)
After forming the single crystal 81 Tr source/drain 13.
To form an n+ region for 13a, As was ion-implanted, and 9
After annealing at around 50℃, the entire surface is oxidized again (
After depositing the SIO2) film 16 by CVD, (d)
, using etching means as shown in (d'), 5
Form contact holes. That is, the symbols 11 and lLa shown in the figure are the source/drain regions 9.9a of the TFT, the symbol 12 is the gate electrode 5, and the symbols 14 and 14a are the source/drain regions 13 of the single crystal St substrate 1.
．． 13a (see FIG. 1(a)).

As described above, since the TFT side constitutes a PMO3 transistor and the single crystal Si side constitutes an NMOS transistor, the first
A so-called stacked STCMOS is formed in which the CMOS structure shown in the figure is integrated by internal connection, that is, the gate electrode 5 is used as a common gate.

As described above with reference to the embodiments, the structure of the semiconductor device according to the present invention is a stacked CMOS including self-aligned TPT using a TPT substrate pattern. Then, before forming the source/drain regions of the single crystal St substrate, TPT
The heat treatment for improving the performance and yield of TPT by forming the substrate has a feature in the manufacturing method that there is no problem at all even if high temperature treatment is performed.

It goes without saying that the present invention is not limited to the above-described embodiments, and that various changes can be made without departing from the spirit of the invention.

[Effects of the Invention] As explained above, in this invention, the TFT substrate is arranged on a common gate, has the same planar shape as the gate except for the contact portion of the gate, and is made of a single crystal by using the TPT substrate and the common gate as a mask. By developing a structure in which the source/drain regions of SIT are formed and a manufacturing method for the same,
The effects listed below can be obtained.

(1) Thermal annealing and high-temperature gate treatment of the polycrystalline Si layer, which are performed to improve TPT performance and yield, can now be performed regardless of the junction depth of single-crystalline silicon transistors, improving product performance and yield. is possible.

(2) Since the channel length of the TPT is created in the channel width direction of the 'II crystal Sl transistor, the channel length of the TFT can be set to be long regardless of the channel length of the single crystal transistor.

[Brief explanation of the drawing]

FIG. 1 is a sectional view and a top explanatory view of a main part of a semiconductor device showing an embodiment of the present invention, FIG. FIG. 3 is an explanatory cross-sectional view showing an example of a conventional semiconductor device having a stacked CMOS structure. In the figure, 1 is a single crystal SIp substrate, 2 and 2a are source/drain regions, 3 and 3a are gate oxide films, 4 is a closed channel stopper, 5 is a gate electrode, 6 is a field oxide film, and 7 is a second layer polycrystalline Si film, 8 is an r-type channel, 9
．． 9a is a source/drain region of a polycrystalline SI Tr;
IO is an insulator film, 11. lla is contact hole,
12 is a contact hole, 13° 13a is a single crystal SI
In the source/drain region of the Tr, 14° 14a is a contact hole, 15.15a is a photoresist film, and 1B is an insulating film. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

[Claims] (1) A polycrystalline silicon substrate consisting of a MOS transistor formed on a single crystal silicon substrate, a gate electrode made of polycrystalline silicon of this MOS transistor as a common gate, and a polycrystalline silicon layer deposited on this common gate. In a semiconductor device having a laminated structure consisting of a thin film transistor to be formed, the polycrystalline thin film transistor of the thin film transistor is provided on the common gate and is formed in the same planar shape as the gate except for a contact portion of the gate. A silicon substrate, a contact hole formed near both ends of the polycrystalline silicon substrate and provided in an insulating layer deposited on the polycrystalline silicon substrate, and the thin film transistor formed below the contact hole. A semiconductor device comprising a source/drain region. (2) A MOS transistor formed on a single crystal silicon substrate, a gate electrode made of polycrystalline silicon of this MOS transistor as a common gate, and a polycrystalline silicon substrate made of a polycrystalline silicon layer deposited on this common gate. In the method of manufacturing a semiconductor device having a stacked structure including a thin film transistor to be formed, before forming a source/drain region of the single crystal silicon MOS transistor, a first layer is formed on the single crystal silicon substrate.
a first layer of polycrystalline silicon film constituting the gate, a second layer of gate oxide film formed by high-temperature oxidation, and a second layer on which the source/drain for the thin film transistor forming the substrate of the polycrystalline silicon transistor is formed. After forming two layers of polycrystalline silicon film and insulating film in sequence,
The first layer of polycrystalline silicon film is used as the common gate, and the polycrystalline silicon substrate of the second layer of polycrystalline silicon film is formed on the common gate and the contact portion of this gate. After that, after forming the source/drain of the MOS transistor formed on the single crystal silicon substrate, an insulating film is deposited on the second polycrystalline silicon substrate near both ends. A method of manufacturing a semiconductor device, comprising forming contact holes in the insulating film at source/drain contact positions, source/drain contact positions of the single crystal silicon substrate, and common gate contact positions.