JPS63300568A - Formation of schottky electrode - Google Patents
Formation of schottky electrodeInfo
- Publication number
- JPS63300568A JPS63300568A JP13722887A JP13722887A JPS63300568A JP S63300568 A JPS63300568 A JP S63300568A JP 13722887 A JP13722887 A JP 13722887A JP 13722887 A JP13722887 A JP 13722887A JP S63300568 A JPS63300568 A JP S63300568A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- exposed
- covered
- schottky electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 7
- 238000007493 shaping process Methods 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 8
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 3
- 239000004020 conductor Substances 0.000 abstract description 2
- 230000008018 melting Effects 0.000 abstract description 2
- 238000002844 melting Methods 0.000 abstract description 2
- 229910000510 noble metal Inorganic materials 0.000 abstract description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 2
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 1
- 230000005669 field effect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ショットキー電極の形成方法に関し、特に電
界効果トランジスタのショットキーゲートの形成方法に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming a Schottky electrode, and particularly to a method for forming a Schottky gate of a field effect transistor.
従来のこの種の技術を第3図(a)〜(d)を参照して
説明する。A conventional technique of this type will be explained with reference to FIGS. 3(a) to 3(d).
まず第3図(a)に示すように、GaAsからなる半導
体基板21の表面にW−3tからなる耐熱性の導電膜2
2を形成する。その後、第3図(b)に示すように酸化
シリコンからなる絶縁膜23を堆積し、ホトレジスト膜
24により表面を平坦にする0次いで、絶縁膜23とホ
トレジスト膜24のエツチングレートが等しい条件で全
面を徐々にエツチングする。第3図(c)に示すように
導電膜22の表面が露出した所でエッチラグを終了し表
面にAuからなる低抵抗金属膜25を被着する。次に、
第3図(d)に示すように、低抵抗金属膜25を所定形
状に整形加工し、低抵抗のショットキー電極を形成して
いた。First, as shown in FIG. 3(a), a heat-resistant conductive film 2 made of W-3t is coated on the surface of a semiconductor substrate 21 made of GaAs.
form 2. Thereafter, as shown in FIG. 3(b), an insulating film 23 made of silicon oxide is deposited, and the surface is flattened with a photoresist film 24.Then, the entire surface is etched under the condition that the etching rates of the insulating film 23 and the photoresist film 24 are equal. gradually etching. As shown in FIG. 3(c), the etch lag is terminated when the surface of the conductive film 22 is exposed, and a low resistance metal film 25 made of Au is deposited on the surface. next,
As shown in FIG. 3(d), the low resistance metal film 25 was shaped into a predetermined shape to form a low resistance Schottky electrode.
上述した従来のショットキー電極の形成方法では、耐熱
性の導電膜の表面を露出させる際のエツチングにおいて
、エツチングの終了時点を決定する事が困難であり、エ
ツチング量が足ない場合は、耐熱性の導電膜と低抵抗金
属膜が接触しないし、エツチング量が多すぎる場合は、
低抵抗金属膜の被着と整形加工がうまくいかず、特性の
均一なショットキー電極が得られないという欠点がある
。In the conventional Schottky electrode formation method described above, it is difficult to determine the end point of etching when exposing the surface of a heat-resistant conductive film. If the conductive film and low-resistance metal film do not contact each other and the amount of etching is too large,
The drawback is that the deposition and shaping of the low-resistance metal film are not successful, making it impossible to obtain a Schottky electrode with uniform characteristics.
本発明のショットキー電極の形成方法は、半導体基板表
面にショットキー接合をなす導電膜と第1の絶縁膜を形
成して所定形状に整形する工程と、第2の絶縁膜を全面
に堆積させて前記導電膜及び第1の絶縁膜を埋込む工程
と、表面が平坦なレジスト膜を被着する工程と、エツチ
ング技術により前記第1の絶縁膜表面を露出させたのち
前記第1の絶縁膜を選択的に除去して前記導電膜表面を
露出させる工程と、前記導電膜と接触する金属膜を被着
する工程とを含むというものである。The method for forming a Schottky electrode of the present invention includes the steps of forming a conductive film and a first insulating film forming a Schottky junction on the surface of a semiconductor substrate and shaping them into a predetermined shape, and depositing a second insulating film on the entire surface. a step of embedding the conductive film and the first insulating film, a step of depositing a resist film with a flat surface, and a step of exposing the surface of the first insulating film by etching, and then removing the first insulating film. The method includes a step of selectively removing the conductive film to expose the surface of the conductive film, and a step of depositing a metal film in contact with the conductive film.
〔実施例〕
次に、本発明の実施例について図面を参照して説明する
。[Example] Next, an example of the present invention will be described with reference to the drawings.
第1図(a)〜(d)は本発明の第1の実施例を説明す
るための工程順に配置した半導体チップの断面図である
。FIGS. 1(a) to 1(d) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining a first embodiment of the present invention.
まず、第1図(a)に示すように、GaAsからなる半
導体基板11の表面に、GaAsとショットキー接合を
なす高融点導電材料であるタングステンシリサイドから
なる導電膜12を厚さ400nm被着する。次に、厚さ
300nmの酸化シリコン膜からなる第1の絶縁膜13
を被着し所定形状に整形する。First, as shown in FIG. 1(a), a conductive film 12 made of tungsten silicide, which is a high melting point conductive material that forms a Schottky junction with GaAs, is deposited to a thickness of 400 nm on the surface of a semiconductor substrate 11 made of GaAs. . Next, a first insulating film 13 made of a silicon oxide film with a thickness of 300 nm is formed.
is applied and shaped into a predetermined shape.
電界効果トランジスタ製造上必要な高温熱処理後、第1
図(b)に示すように、窒化シリコンからなる第2の絶
縁膜13を導電膜12.第1の絶縁膜13の合計厚さと
同程度被着し、ホトレジスト膜15により表面を平坦に
する。次いで窒化シリコン膜(14)とホトレジスト膜
15のエツチングレートが同じドライエツチング条件で
全面を徐々にエツチングし第1図(c)に示すように第
1の絶縁膜13の表面が露出してから導電膜12の表面
が露出するまでの間にエツチングを終了する。その後希
釈フッ酸により、エツチングすると、窒化シリコン膜(
14)はほとんどエツチングされず、酸化シリコン膜(
13)のみが除去され、”vV−3i膜(12)の表面
が露出する。次にAuなどの貴金属からなる低抵抗金属
膜16を第1図(d)のように導電膜12に接触させて
被着し、整形加工し低抵抗ゲート(ショットキー電極)
を形成する。After the high-temperature heat treatment necessary for manufacturing field effect transistors, the first
As shown in Figure (b), a second insulating film 13 made of silicon nitride is applied to a conductive film 12. It is deposited to the same extent as the total thickness of the first insulating film 13, and the surface is made flat by the photoresist film 15. Next, the entire surface is gradually etched under dry etching conditions in which the etching rate of the silicon nitride film (14) and the photoresist film 15 are the same, and after the surface of the first insulating film 13 is exposed as shown in FIG. Etching is completed before the surface of film 12 is exposed. The silicon nitride film (
14) is hardly etched, and the silicon oxide film (
13) is removed, and the surface of the vV-3i film (12) is exposed.Next, a low resistance metal film 16 made of a noble metal such as Au is brought into contact with the conductive film 12 as shown in FIG. 1(d). A low-resistance gate (Schottky electrode) is formed by applying and shaping the
form.
第2の絶縁膜のエツチングは、第1の絶縁膜の表面が露
出してから導電膜12の表面が露出するまでの任意の闇
で終了させれば、導電膜12.金属膜16からなるショ
ットキー電極の加工上何の問題も生じない。Etching of the second insulating film can be completed at any time between when the surface of the first insulating film is exposed and when the surface of the conductive film 12 is exposed. No problems arise in processing the Schottky electrode made of the metal film 16.
第2図(a)〜(c)は本発明の第2の実施例を説明す
るための工程順に配置した半導体チップの断面図である
。FIGS. 2(a) to 2(c) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining a second embodiment of the present invention.
第1図(a)、(b)を用いて説明した工程の次に、第
2図(a)に示すように窒化シリコン膜(14)の凸部
の表面が露出するまでエツチングする。次に、第2図(
b)に示すように、ホトレジスト膜15をマスクに窒化
シリコン膜をエツチングして酸化シリコン膜13の表面
が露出して導電膜12の表面が露出するまでの間にエツ
チングを終了する。その後希釈フッ酸で残った酸化シリ
コ膜(13)のみをエツチングし導電膜12の表面を露
出させ、第2図(b)に示すようにAu等の低抵抗金属
膜16を第2図(c)のように成膜し、低抵抗ゲート電
極を形成する。この実施例では、低抵抗金属膜と半導体
基板間の容量が軽減でき、ショットキーゲート型電界効
果トランジスタの特性が改善できるという利点がある。Next to the steps explained using FIGS. 1(a) and 1(b), etching is performed until the surface of the convex portion of the silicon nitride film (14) is exposed as shown in FIG. 2(a). Next, see Figure 2 (
As shown in b), the silicon nitride film is etched using the photoresist film 15 as a mask, and the etching is completed before the surface of the silicon oxide film 13 is exposed and the surface of the conductive film 12 is exposed. Thereafter, only the remaining silicon oxide film (13) is etched with diluted hydrofluoric acid to expose the surface of the conductive film 12, and a low resistance metal film 16 such as Au is etched as shown in FIG. 2(c). ) to form a low resistance gate electrode. This embodiment has the advantage that the capacitance between the low resistance metal film and the semiconductor substrate can be reduced and the characteristics of the Schottky gate field effect transistor can be improved.
以上説明したように本発明は、まず耐熱性の導電膜上に
第1の絶縁膜のあるものを形成し、その上に第2の絶縁
膜を形成することにより、第2の絶縁膜のエツチングの
終了時点を耐熱性の導電膜上の第1の絶縁膜の表面が露
出してから耐熱性の導電膜の表面が露出するまでの間で
任意に選べるので、形状の整ったショットキー電極を確
実に形成でき、ショットキーダイオード、ショットキー
ゲート型電界効果トランジスタ等の半導体装置を再現性
よく製造できる効果がある。As explained above, in the present invention, a first insulating film is first formed on a heat-resistant conductive film, and a second insulating film is formed on top of the first insulating film. The end point of the process can be arbitrarily selected between the time when the surface of the first insulating film on the heat-resistant conductive film is exposed and the time when the surface of the heat-resistant conductive film is exposed, making it possible to form a well-shaped Schottky electrode. It can be formed reliably and is effective in manufacturing semiconductor devices such as Schottky diodes and Schottky gate field effect transistors with good reproducibility.
第1図(a)〜(d)、第2図(a)〜(c)及び第3
図(a)〜(d)はそれぞれ本発明の第1の実施例、第
2の実施例及び従来例を説明するための工程順に配置し
た半導体チップの断面図である。
11.21・・・半導体基板、12.22・・・導電膜
、13・・・第1の絶縁膜、14.24・・・ホトレジ
スト膜、15・・・ホトレジスト膜、16・・・金属膜
、23・・・絶縁膜、25・・・低抵抗金属膜。
Ml 図
兜2Z
第37Figures 1 (a) to (d), Figures 2 (a) to (c), and Figure 3.
Figures (a) to (d) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining a first embodiment, a second embodiment, and a conventional example of the present invention, respectively. 11.21... Semiconductor substrate, 12.22... Conductive film, 13... First insulating film, 14.24... Photoresist film, 15... Photoresist film, 16... Metal film , 23... Insulating film, 25... Low resistance metal film. Ml Illustration helmet 2Z No. 37
Claims (1)
の絶縁膜を形成して所定形状に整形する工程と、第2の
絶縁膜を全面に堆積させて前記導電膜及び第1の絶縁膜
を埋込む工程と、表面が平坦なレジスト膜を被着する工
程と、エッチング技術により前記第1の絶縁膜表面を露
出させたのち前記第1の絶縁膜を選択的に除去して前記
導電膜表面を露出させる工程と、前記導電膜と接触する
金属膜を被着する工程とを含むことを特徴とするショッ
トキー電極の形成方法。A conductive film forming a Schottky junction on the surface of a semiconductor substrate and a first
a step of forming an insulating film and shaping it into a predetermined shape, a step of depositing a second insulating film over the entire surface and embedding the conductive film and the first insulating film, and depositing a resist film with a flat surface. exposing the surface of the first insulating film using an etching technique and then selectively removing the first insulating film to expose the surface of the conductive film; and a metal film in contact with the conductive film. A method for forming a Schottky electrode, the method comprising: depositing a Schottky electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13722887A JPS63300568A (en) | 1987-05-29 | 1987-05-29 | Formation of schottky electrode |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13722887A JPS63300568A (en) | 1987-05-29 | 1987-05-29 | Formation of schottky electrode |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63300568A true JPS63300568A (en) | 1988-12-07 |
Family
ID=15193775
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13722887A Pending JPS63300568A (en) | 1987-05-29 | 1987-05-29 | Formation of schottky electrode |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63300568A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02244642A (en) * | 1989-03-16 | 1990-09-28 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
-
1987
- 1987-05-29 JP JP13722887A patent/JPS63300568A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02244642A (en) * | 1989-03-16 | 1990-09-28 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
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