JPS6329953A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a stepped section in the surface, and to form a structure, in which the disconnection and defective short circuits of a wiring with a change into multilayers of the wiring are difficult to be generated, by connecting a wiring layer in a semiconductor substrate bulk by a diffusion layer shaped by diffusing a semiconductor having the same conduction type as the wiring layer and turning the wiring into multilayers. CONSTITUTION:A first diffusion wiring layer 12 having a conductivity type reverse to at least one layer or more of an electrically isolated semiconductor substrate 11 and a second diffusion wiring layer 14 electrically isolated from the first diffusion wiring layer 12 and having the conductivity type reverse to the semiconductor substrate 11 in a surface region in the semiconductor substrate 11 are formed into one conductivity type semiconductor substrate bulk. Predetermined sections in the first and second diffusion wiring layers 12, 14 are connected by a diffusion layer 17 buried between the layers 12, 14 and shaped by diffusing a semiconductor having the conductivity type reverse to the semiconductor substarte 11. Accordingly, since both diffusion wiring layers 12, 14 are connected by the diffusion layer 17, a stepped section in the surface of the second diffusion wiring layer 14 can be reduced, thus preventing the generation of the disconnections and defective short circuits of wirings with a change into multilayers of the wirings.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to a multilayer arrangement of semiconductor integrated circuits. ;! Magazuke ni III
It is something that

2. Description of the Related Art Conventionally, in order to achieve higher integration and higher density of semiconductor integrated circuits, it has been well known that the wiring area of an integrated circuit has a multilayer structure.

FIG. 3 is a sectional view showing an example of a conventional multilayer wiring WJ structure of a semiconductor device. In FIG. 3, 1 is a silicon substrate, and a diffusion wiring layer 2 is formed on the surface area of this silicon substrate 1, and this diffusion arrangement! ;1 layer 2 upper 2 upper 1 approximately 8 layers 3
First metal distribution through! ! Two layers 4 are formed, this first
A second metal interconnection layer 5! is formed on the metal interconnection layer 4 through the second insulating layer 5! A wiring layer 4.6 is connected to the wiring layers 2, 4 through contact holes 3a, 5a formed in the insulating layers 3, 5. 7 is a third insulating layer that protects the second metal wiring layer 6.

Problems to be Solved by the Invention However, in the conventional multilayer wiring structure, as the number of metal wiring layers increases to two or three layers, the metal wiring layer 4
The negative step 4a becomes large on the surface above the contact hole 3a, and there is a problem in that wiring breaks and short circuits are likely to occur.

The present invention solves the above-mentioned problems, and even when the wiring layers of a semiconductor integrated circuit are multi-layered, the wiring is only 5. It is an object of the present invention to provide a semiconductor device having a multilayer wiring structure in which no level difference occurs on the surface of the layers.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a bulk semiconductor substrate of one conductivity type, at least one layer of which is electrically isolated from the semiconductor substrate and a first layer of the opposite conductivity type. a diffusion wiring layer, and a second diffusion wiring layer of a conductivity type opposite to that of the semiconductor substrate, which is electrically isolated from the first diffusion wiring layer in a surface region of the semiconductor substrate.
The first and second diffusion layers 15i! Predetermined portions of the layers are connected by a diffusion layer formed by diffusion of a semiconductor of a conductivity type opposite to that of the semiconductor substrate buried therebetween.

Function: With the above structure, wiring layers in the bulk of a semiconductor substrate that are electrically separated are connected by a diffusion layer formed by diffusion of a semiconductor of the same conductivity type. Compared to a structure in which wiring layers are stacked on a substrate, the @ structure is less likely to cause disconnections or short circuits due to multi-layered wiring, due to the smaller level difference on the surface.

Example Hereinafter, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 1(a) is a plan view of a semiconductor device which is an embodiment of the present invention, and FIG. 1(b) is a sectional view taken along line AA' in FIG.

In FIG. 1, reference numeral 11 denotes a p-type silicon substrate, and an n-type first diffusion wiring layer 12 is formed on the surface region of this p-type silicon substrate 1. An epitaxial layer 13 is formed. Also,
An n-type second diffusion wiring layer 14 is formed in the surface region of the epitaxial layer 13, and this second diffusion wiring layer 14 and the first diffusion wiring layer 14 are connected to each other.
The predetermined portion of the diffusion wiring layer 12 is a region filled in a first contact hole 15 provided to reach the first diffusion wiring layer 12 through the second diffusion wiring layer 14 and the epitaxial layer 13. In addition, phosphorus-doped polysilicon 16
They are connected by an n-type diffusion layer 17 formed by diffusion from the substrate. Reference numeral 18 denotes an aluminum wiring layer, which is insulated from the second diffusion wiring layer 14 by a first silicon oxide layer 19 and is connected through a second contact hole 20 provided in a predetermined portion of the first silicon oxide layer 19. and is connected to the second diffusion wiring layer 14. 21 is aluminum layout I!
! ;! A second silicon oxide layer that protects layer 18.

Next, the manufacturing process of the semiconductor device of the present invention will be explained.

FIG. 2 is a sectional view showing an embodiment of the manufacturing process of the 1J semiconductor device shown in FIG. First, as shown in FIG. 2(a), a p-type silicon substrate 1 with an impurity concentration of 1×10×α
1 at a predetermined portion of the surface of
A first n-type diffusion wiring layer 12 is formed using a well-known selective diffusion technique, and then a p-type []-hypertaxial layer 13 with an impurity concentration of 1×10” ci is formed to a thickness of 7 μm.
A first contact hole 15 is formed in a predetermined portion of the epitaxial layer 13 above the first diffusion layer 12 by RIE (reactive ion etching) technique.

Next, as shown in FIG. 2(b), the inside of the first contact hole 15 is doped with phosphorus at a concentration of about 5 x
Polysilicon 16 of 10" cm ' is filled by a known vapor phase growth method, and the polysilicon other than the first contact hole 15 is removed by an edge-back method and flattened. Next, phosphorus contained in polysilicon 16 is removed by heating. An n-type diffusion layer 17 is formed in the epitaxial layer 13 by diffusion.

Next, as shown in FIG. 2(C), the epitaxial layer 1
A second n-type diffusion interconnection layer 14 with an inactive concentration of about 1×10″cxr−’ is formed in a region excluding the n-type diffusion layer 17 on the surface of 3 by a known selective diffusion technique, and further A first silicon oxide film 19 is formed as an insulating layer by a known vapor phase growth method, and then a second contact hole 20 is formed in a predetermined portion of the silicon oxide film 19 by a known photoetching technique.

Next, as shown in FIG. 2(d), an aluminum film of about 1 μm is deposited by a known vacuum evaporation method, and an aluminum PiJ layer 18 is formed by photoetching to cover the second contact hole 20. Next, a second silicon oxide WA 21 is formed by a known vapor phase growth method to protect the aluminum wiring layer 18, and the semiconductor device shown in FIG. 1 is obtained.

Although only the multilayer wiring structure has been described in this embodiment, it goes without saying that the multilayer wiring M4 structure of the present invention can be used to connect semiconductor elements such as MOS transistors and bipolar transistors.

Further, although this embodiment shows an example using one diffusion wiring layer in the bulk of the semiconductor substrate, higher integration can be achieved by using two or more layers.

In this way, since both the diffusion layers 12 and 14 are connected by the diffusion layer 17, the level difference on the surface of the second diffusion layer 4!2 layer 14 can be reduced.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, according to the present invention, a diffusion layer having a conductivity type opposite to that of the semiconductor substrate in an electrically isolated bulk of the semiconductor substrate is connected by a diffusion layer having a conductivity type opposite to that of the semiconductor substrate. Therefore, compared to the conventional structure in which wiring layers are stacked on a semiconductor substrate, it is possible to reduce the level difference on the surface, and it is less likely to cause disconnections or short circuits that occur due to multilayer wiring, making it possible to improve semiconductor integrated circuits. This can greatly contribute to improving the reliability of multilayer wiring structures.

In addition, by combining the conventional multilayer F structure and the 4III structure of the present invention, the multilayer wiring of semiconductor*a circuits can be dramatically improved, leading to higher integration and higher density of semiconductor integrated circuits. It is possible to make a significant contribution to

[Brief explanation of the drawing]

FIG. 1(a) is a plan view of a semiconductor device showing an embodiment of the present invention, FIG. 1(b) is a sectional view taken along line AA' in FIG. 1(a),
FIGS. 2(a) to 2(d) are cross-sectional views illustrating the manufacturing process of the same semiconductor device, and FIG. 3 is a cross-sectional view showing a conventional multilayer wiring 411I structure. DESCRIPTION OF SYMBOLS 11... P-type silicon substrate, 12... First diffusion distribution KJ layer, 13... Epitaxial layer, 14... Second
diffusion distribution, Pi1 layer, 16...polysilicon layer, 17
... Diffusion layer agent Yoshihiro Moriki Figure 1'4---N2y+t@edo$4 21---pi
,,7a>m ft) Gutu>4t6-i Marunoshidakun Figure 3

Claims (1)

[Claims] 1. In a semiconductor substrate bulk of one conductivity type, at least one electrically isolated first diffusion wiring layer of an opposite conductivity type to the semiconductor substrate, and the first diffusion wiring layer in a surface region of the semiconductor substrate; a second diffusion wiring layer of a conductivity type opposite to the semiconductor substrate, which is electrically isolated from the wiring layer;
and a semiconductor device in which a predetermined portion of the second diffusion wiring layer is connected by a diffusion layer formed by diffusion of a semiconductor of a conductivity type opposite to that of the semiconductor substrate buried therebetween.