JPS63296360A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63296360A JPS63296360A JP13262887A JP13262887A JPS63296360A JP S63296360 A JPS63296360 A JP S63296360A JP 13262887 A JP13262887 A JP 13262887A JP 13262887 A JP13262887 A JP 13262887A JP S63296360 A JPS63296360 A JP S63296360A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor device
- molding
- surface part
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000011347 resin Substances 0.000 claims abstract description 28
- 229920005989 resin Polymers 0.000 claims abstract description 28
- 238000007789 sealing Methods 0.000 claims abstract description 13
- 238000000465 moulding Methods 0.000 abstract description 15
- 230000002950 deficient Effects 0.000 abstract description 5
- 238000004140 cleaning Methods 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000004907 flux Effects 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 5
- 238000005476 soldering Methods 0.000 description 3
- 239000002904 solvent Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 235000008375 Decussocarpus nagi Nutrition 0.000 description 1
- 244000309456 Decussocarpus nagi Species 0.000 description 1
- 102000003816 Interleukin-13 Human genes 0.000 description 1
- 108090000176 Interleukin-13 Proteins 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は樹脂封止した半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a resin-sealed semiconductor device.
本発明はアウターリードがJ形に曲げられ−た、かつ、
樹脂封止部の下面部の端部周辺に、下面部より引込んだ
第2の平面部を有する事を特徴とする半導体装置に関す
る。In the present invention, the outer lead is bent into a J shape, and
The present invention relates to a semiconductor device characterized by having a second plane part recessed from the lower surface part around the end of the lower surface part of the resin sealing part.
従来のJ形に曲げられたアウターリードを有する半導体
装置は特開昭58−27354号公報、に示す如き形状
をしていた。すなわち第2図、第3図において、樹脂封
止部lの下面部2に複数個のアウターリード3に対応し
複数個の凸部4及び凹部5が設けられていた。アウター
リード3は樹脂封止部lの各側面部6に埋め込まれ、J
型に曲げられ他端は凸部4をとびこえ凹部5の中に入っ
ている如き構造であった。この様な、多数の凸部4、凹
部5を有する形状の樹脂封止する場合、樹脂屑等により
成形率゛良が生じやすく、不良率が高くなりやすい傾向
があった。その゛様子を第4図で説明する。A conventional semiconductor device having an outer lead bent into a J shape has a shape as shown in Japanese Unexamined Patent Publication No. 58-27354. That is, in FIGS. 2 and 3, a plurality of convex portions 4 and a plurality of concave portions 5 were provided on the lower surface portion 2 of the resin sealing portion l, corresponding to the plurality of outer leads 3. The outer lead 3 is embedded in each side surface 6 of the resin sealing part l, and
It was bent into a shape, and the other end went over the convex part 4 and entered the concave part 5. When resin-sealing a shape having a large number of convex portions 4 and concave portions 5 as described above, the molding rate tends to deteriorate due to resin debris and the like, and the defective rate tends to increase. The situation will be explained with reference to FIG.
第4図において10は上型で製品形状となる上キャビテ
ィー11を有する。12は下型で、−製品形状となる下
キャビティー13を有する。下キャビティー13には製
品の凹部5及び凸部4となる突起14及び窪15を有す
る、樹脂はランナー1Gからゲート17を通って上下キ
ャビティーIL13に注入される。18はリードフレー
ムである。In FIG. 4, reference numeral 10 denotes an upper mold having an upper cavity 11 that forms the product shape. 12 is a lower mold, which has a lower cavity 13 which becomes a product shape. The lower cavity 13 has protrusions 14 and depressions 15 that will become the recesses 5 and protrusions 4 of the product. Resin is injected from the runner 1G through the gate 17 into the upper and lower cavities IL13. 18 is a lead frame.
樹脂成形する場合、上型10、下型12の境界部分のス
キマを、ゼロにする事は困難で5μ程度の微小なスキマ
が出来る事は周知の事実である。In the case of resin molding, it is a well-known fact that it is difficult to eliminate the gap at the boundary between the upper mold 10 and the lower mold 12, and that a minute gap of about 5 μm is created.
このため、成形樹脂がこのスキマに入り込み硬化、上型
lO1下型12を開き製品を取り出した後、前述した、
スキマに入り込んだ薄い(5μm程度)樹脂が一部は製
品に付着し、上型10、下型12から除去され、一部は
上型10下型12に付着又は落下して取り残される。こ
の除去のため成形後、エアー又はブラシ等で、上型10
、下型12内に取り残されている薄い樹脂を除去してい
る。For this reason, the molding resin enters this gap and hardens, and after opening the upper mold lO1 and lower mold 12 and taking out the product, the above-mentioned
A portion of the thin (about 5 μm) resin that has entered the gap adheres to the product and is removed from the upper mold 10 and lower mold 12, and a portion adheres to or falls to the upper mold 10 and lower mold 12 and is left behind. To remove this, after molding, use air or a brush to remove the upper mold 10.
, the thin resin left behind in the lower mold 12 is removed.
このとき上型10、下型12の主として上、下キャビテ
ィー11及び13内に凹凸があると、突部14のつけ根
、窪の底に薄い硬化した樹脂19が残りやすく、次回樹
脂注入時、硬化した樹脂、19が製品の中に混入される
事になり品質上問題が発生しやすい事も周知の事実であ
る。At this time, if there are irregularities mainly in the upper and lower cavities 11 and 13 of the upper mold 10 and the lower mold 12, a thin hardened resin 19 tends to remain at the base of the protrusion 14 and the bottom of the depression, and the next time the resin is injected, It is also a well-known fact that the cured resin 19 is mixed into the product, which tends to cause quality problems.
以上の観点より従来の方法はアウターリード3に対応し
て多数の微細な凹凸があり、硬化した樹脂の除去は困難
であった。From the above point of view, in the conventional method, there were many fine irregularities corresponding to the outer leads 3, and it was difficult to remove the cured resin.
又、本発明にかかわる製品のプリン)i板への組立状態
は第5図に示す如く、ハンダ20により、基板21上に
ハンダ付される。Further, as shown in FIG. 5, the product according to the present invention is assembled onto a substrate 21 by soldering 20 onto a substrate 21. As shown in FIG.
ハンダ付時、固着部の活性化のため、フラックスを用い
、ハンダ付後、樹脂封止部1等に付着したフラックスを
溶剤により除去する事が行われる。During soldering, flux is used to activate the fixed portion, and after soldering, the flux adhering to the resin sealing portion 1 and the like is removed using a solvent.
従来の方法によれば、樹脂封止部1に凹凸が多く、その
中にもフラックスが入り込むため、溶剤での洗浄がしに
くく、残った場合、フラックスの特性上、アウターリー
ド3を錆させる恐れがあった。According to the conventional method, the resin sealing part 1 has many irregularities, and the flux gets into it, making it difficult to clean with a solvent, and if it remains, there is a risk that the outer lead 3 will rust due to the characteristics of flux. was there.
さらに、アウターリード3に対応して凸部4及び凹部5
が設けられ、さらにアウターリード3の先端は凹部5の
中に入っている構造のため、従来の半導体装置は最初の
樹脂封止部lの設計で、設置できるアウターリード3の
本数が決まってしまい、樹脂封止部1を成形するための
金型に対し、ただ一つの種類のものしか出来ない事にな
る。Further, a convex portion 4 and a concave portion 5 are provided corresponding to the outer lead 3.
is provided, and the tips of the outer leads 3 are placed inside the recess 5, so in conventional semiconductor devices, the number of outer leads 3 that can be installed is determined by the design of the initial resin sealing part l. Therefore, only one type of mold can be used to mold the resin sealing part 1.
以上の様に従来の方法によれば、樹脂成形特金型の多数
の凹凸に、薄い硬化した樹脂が、エアー等のふきつけで
も除去されにくく、製品の不良率を高めていた、又樹脂
封止部に微細な凹凸が多数あるため、プリント基板への
組立時、フラックス除去がしにくいという欠点を持って
いた。As described above, according to the conventional method, the thin hardened resin is difficult to remove even by blowing with air due to the many irregularities of the resin molding special mold, increasing the defective rate of the product. Since there are many fine irregularities on the surface, it has the disadvantage that it is difficult to remove flux when assembling it onto a printed circuit board.
しかるに本発明は従来の問題点を解決しようとするもの
で、その目的は
(1)、樹脂成形時の不良率を低下させる。However, the present invention is intended to solve the conventional problems, and its purpose (1) is to reduce the defective rate during resin molding.
(2)、プリント基板組立時、フラックス洗浄をしやす
(し、品質を向上させる。(2) Easier flux cleaning when assembling printed circuit boards (and improves quality).
(3)、1つの樹脂封止部成形用金型で複数の種類の半
導体装置を供給する事にある。(3) A plurality of types of semiconductor devices can be supplied using one resin molding mold.
本発明は、樹脂封止部の下面部の端部周辺に、下面部よ
り引込んだ第2の平面部を設けた事を特徴とする半導体
装置である。The present invention is a semiconductor device characterized in that a second plane part recessed from the lower surface part is provided around the end of the lower surface part of the resin sealing part.
本発明の一実施例を第1図、第6図について説明する。 An embodiment of the present invention will be described with reference to FIGS. 1 and 6. FIG.
30はグイバット、31は半導体素子で、グイバット3
0に固着されている。32は金属製のインナーリード、
33はアウターリードでインナーリード32と一体で形
成されている。34は直径30μm前後の細線で、イン
ナーリード32と半導体素子31の図示しない電極とを
電気的に導通させている。35はアウターリード33の
先端部、36は略正方形の樹脂封止部、37は樹脂封止
部36の下面部38より引き込み、略正方形の樹脂封止
部36の下面部38の4辺全周に配置された第2の平面
部、39はアウターリード33の配列間隔を示す。30 is Guibat, 31 is a semiconductor element, Guibat 3
It is fixed at 0. 32 is a metal inner lead,
Reference numeral 33 denotes an outer lead which is formed integrally with the inner lead 32. Reference numeral 34 denotes a thin wire having a diameter of about 30 μm, which electrically connects the inner lead 32 and an unillustrated electrode of the semiconductor element 31. 35 is the tip of the outer lead 33, 36 is a substantially square resin-sealed portion, and 37 is drawn in from the lower surface 38 of the resin-sealed portion 36, all around the four sides of the lower surface 38 of the approximately square resin-sealed portion 36. A second plane portion 39 located at 39 indicates the arrangement interval of the outer leads 33.
以上の構成によれば、第2の平面37は従来例で示した
凹凸が無く構成されているため、樹脂成形用金型に凹凸
が少(なるため成形不良が少く、なる事は前述した通り
である。スプリント基板への組立時、洗浄が行いやすい
事も明らかである。According to the above configuration, since the second plane 37 is configured without the unevenness shown in the conventional example, the resin molding mold has fewer unevenness (therefore, there are fewer molding defects, as described above). It is also clear that cleaning is easy when assembled onto a splint board.
さらに、第2の平面37は凹凸が無く形成されているた
め、配列間隔5は制限を受けないため、技術的に可能な
範囲で、アウターリード33の本数を選択出来る。−例
としてアウターリード33の本数は樹脂封止部36の外
形寸法が縦横とも29゜3m/mの場合、配列間隔39
が1 、27+++n+の場合84本1.27/2+m
の場合160本配置出来、成形用金型が一種類でも複数
のタイプの半導体装置が得られる。Furthermore, since the second plane 37 is formed without any unevenness, the arrangement interval 5 is not limited, so the number of outer leads 33 can be selected within a technically possible range. - As an example, if the external dimensions of the resin sealing part 36 are 29°3m/m in length and width, the number of outer leads 33 is arranged at an arrangement interval of 39°.
If is 1, 27+++n+ then 84 lines 1.27/2+m
In this case, 160 pieces can be arranged, and multiple types of semiconductor devices can be obtained even with one type of molding die.
本発明の実施例においては、第2の平面37は4辺とも
完全に平面の場合について説明したが、第7図の如く略
正方形の頂点付近に突起40を設は位置決め等の目的で
用いる事も可能である。この突起40の高さは下面部3
8と同一であってもよく、下面部38より低くても、高
くてもよいものである。In the embodiment of the present invention, the case where the second plane 37 is completely flat on all four sides has been explained, but the protrusion 40 may be provided near the apex of a substantially square shape as shown in FIG. is also possible. The height of this protrusion 40 is
8, and may be lower or higher than the lower surface portion 38.
第1図は本発明の一実施例を示す断面図第2図は従来の
方法を示す側面図
第3図は従来の方法を示す下平面間
第4図は樹脂成形を示す断面図
第5図はプリント基板への組立を示す断面図第6図は本
発明の一実施例を示す下平面間第7図は他の実施例を示
す上平面図
30・・・グイバット
31・・・半導体素子
32・・・インナーリード
33・・・アウターリード
35・・・アウターリードの先端部
36・・・樹脂封止部
37・・・樹脂封止部の第2の平面部
38・・・樹脂封止部の下面部
以 上
出願人 セイコーエプソン株式会社
棺3図
笥 6凪Fig. 1 is a sectional view showing an embodiment of the present invention Fig. 2 is a side view showing a conventional method Fig. 3 is a lower plane showing a conventional method Fig. 4 is a sectional view showing resin molding 6 is a bottom plan view showing one embodiment of the present invention; FIG. 7 is a top plan view showing another embodiment 30...Guibat 31...Semiconductor element 32 . . . Inner lead 33 . Applicant: Seiko Epson Co., Ltd. Coffin 3: 6 Nagi
Claims (2)
した後、前記リードフレームのアウターリードをJ形に
曲げた半導体装置において、前記樹脂封止部の下面部の
端部周囲に、下面部より引込んだ第2の平面部を有する
事を特徴とする半導体装置。(1) In a semiconductor device in which the outer leads of the lead frame are bent into a J shape after a semiconductor element is mounted on a lead frame and resin-sealed, a lower surface portion is placed around the end of the lower surface portion of the resin-sealed portion. A semiconductor device characterized by having a second flat portion that is more retracted.
を有する特許請求の範囲第1項記載の半導体装置におい
て、前記第2の平面部は、前記正方形又は長方形の各辺
の頂点付近に突起部を有する事を特徴とする半導体装置
。(2) In the semiconductor device according to claim 1, which has a resin sealing portion having a square or rectangular planar shape, the second planar portion protrudes near the apex of each side of the square or rectangle. A semiconductor device characterized by having a part.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13262887A JPS63296360A (en) | 1987-05-28 | 1987-05-28 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13262887A JPS63296360A (en) | 1987-05-28 | 1987-05-28 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63296360A true JPS63296360A (en) | 1988-12-02 |
Family
ID=15085769
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13262887A Pending JPS63296360A (en) | 1987-05-28 | 1987-05-28 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63296360A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5475259A (en) * | 1991-10-17 | 1995-12-12 | Fujitsu Limited | Semiconductor device and carrier for carrying semiconductor device |
-
1987
- 1987-05-28 JP JP13262887A patent/JPS63296360A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5475259A (en) * | 1991-10-17 | 1995-12-12 | Fujitsu Limited | Semiconductor device and carrier for carrying semiconductor device |
US5637923A (en) * | 1991-10-17 | 1997-06-10 | Fujitsu Limited | Semiconductor device, carrier for carrying semiconductor device |
US5666064A (en) * | 1991-10-17 | 1997-09-09 | Fujitsu Limited | Semiconductor device, carrier for carrying semiconductor device, and method of testing and producing semiconductor device |
US5736428A (en) * | 1991-10-17 | 1998-04-07 | Fujitsu Limited | Process for manufacturing a semiconductor device having a stepped encapsulated package |
US5750421A (en) * | 1991-10-17 | 1998-05-12 | Fujitsu Limited | Semiconductor device, carrier for carrying semiconductor device, and method of testing and producing semiconductor device |
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