JPS61269338A - Resin-sealed semiconductor device and molding die used for manufacture thereof - Google Patents

Resin-sealed semiconductor device and molding die used for manufacture thereof

Info

Publication number
JPS61269338A
JPS61269338A JP60110357A JP11035785A JPS61269338A JP S61269338 A JPS61269338 A JP S61269338A JP 60110357 A JP60110357 A JP 60110357A JP 11035785 A JP11035785 A JP 11035785A JP S61269338 A JPS61269338 A JP S61269338A
Authority
JP
Japan
Prior art keywords
package
resin
mold
semiconductor device
sealed semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60110357A
Other languages
Japanese (ja)
Inventor
Hideki Tanaka
英樹 田中
Akira Suzuki
明 鈴木
Koji Koizumi
浩二 小泉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60110357A priority Critical patent/JPS61269338A/en
Publication of JPS61269338A publication Critical patent/JPS61269338A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/182Disposition
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Moulds For Moulding Plastics Or The Like (AREA)
  • Casting Or Compression Moulding Of Plastics Or The Like (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To improve the mold release characteristics of a package to a molding die by forming a predetermined taper to the side surface of a projecting section in the surface of the package. CONSTITUTION:In a package 1 shaped through resin mold, a pellet 4 is fitted to a tab 3 by a bonding material such as a conductive resin. The pellet 4 is connected electrically to the inner end section of a lead 2 through a gold wire. The lead 2 is bent inward along a projecting section 6, which is bent downward near the side end of the package 1 and shaped around the back of the package 1, and a nose section thereof is inserted into a recessed section 7 formed to the back of the package 1. A groove 20 is shaped between the projecting sections 6. Tapered angle theta is formed to the side surfaces of each projecting section 6. The tapered angle theta is set in order to improve the mold release characteristics of the package 1 to a molding die. It is desirable that the tapered angle theta is large from the viewpoint of the mold release characteristics of the package 1 to the molding die.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は、樹脂封止型半導体装置およびその製造技術に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a resin-sealed semiconductor device and a manufacturing technique thereof.

〔背景技術〕[Background technology]

樹脂封止型半導体装置は、通常モールド金型を用いた樹
脂モールド法によって、そのパッケージが形成される。
A package of a resin-sealed semiconductor device is usually formed by a resin molding method using a molding die.

すなわち、リードフレームへのベレット取付工程および
ワイヤボンディング工程が終了した後、該リードフレー
ムが、共に凹部を有する金型の上型と下型の間に挟持さ
れ、その状態で樹脂注入ゲートよりエポキシ樹脂等の樹
脂がモールド型によっで形成されるキャビティ内に注入
され、注入された樹脂が所定時間硬化された後に金型か
ら取り外ずされる。
That is, after the bellet mounting process and wire bonding process to the lead frame are completed, the lead frame is held between the upper and lower molds, both of which have recesses, and in this state, epoxy resin is injected from the resin injection gate. A resin such as the above is injected into a cavity formed by a mold, and after the injected resin is cured for a predetermined period of time, it is removed from the mold.

樹脂の注入硬化によって形成されたパッケージをモール
ド金型から外すために、押圧ピン、いわゆるエジェクト
ビンがモールド金型に設けられ、エジェクトピンによっ
てパッケージに押圧力が加えられることによって、パッ
ケージがモールド金型から外される。すなわち、パンケ
ージが離型される。
In order to remove the package formed by injecting and hardening the resin from the mold, a press pin, or so-called eject bin, is provided in the mold.By applying a pressing force to the package with the eject pin, the package is released from the mold. removed from That is, the pan cage is released from the mold.

ここで、樹脂封止半導体装置において、それに使用され
る樹脂は、半導体装置の信鎖性を高めるために、リード
フレームに対し大きい接着力を示す性質を持つことが必
要とされる。樹脂にこのような性質が必要とされること
に応じて、注入硬化によって形成されたパッケージをモ
ールド金型との離型性は、必ずしも良くない。
Here, in a resin-sealed semiconductor device, the resin used therein is required to have a property that exhibits a large adhesive force to the lead frame in order to improve the reliability of the semiconductor device. Since the resin is required to have such properties, the releasability of the package formed by injection curing from the molding die is not necessarily good.

離型性が悪いと、離型時にエジェクトビンによって、望
ましくない大きさの外力がパッケージに加えられるよう
になる。
If the mold release properties are poor, an undesirable amount of external force will be applied to the package by the eject bin during demolding.

離型性の問題は;いわゆるプラスチックリーデツドチッ
プキャリア型(以下、PLCCとも称する)半導体装置
のように、得るべきパッケージの表面が平坦でなく、凹
凸を持つようにされているときに特に大きくなる。
The problem of mold releasability becomes particularly large when the surface of the package to be obtained is not flat but has irregularities, such as in the case of so-called plastic leaded chip carrier type (hereinafter also referred to as PLCC) semiconductor devices. .

樹脂封止型半導体装置は、またそのパッケージ表面が梨
地面のような粗面とされる場合がある。
In some cases, the package surface of a resin-sealed semiconductor device has a rough surface such as a matte finish.

これは、凹部内面、すなわちモールド後のパンケージ表
面に接触する面が梨地仕上げされているモールド金型を
使用することにより製造できるものである。
This can be manufactured by using a molding die in which the inner surface of the recess, that is, the surface that contacts the surface of the pan cage after molding, has a matte finish.

このようなパッケージ表面の梨地面化は、主に製品を識
別するために種類やロフト番号等をパッケージ表面に印
刷する、いわゆるマーキングを良好にさせるために行わ
れる。ここでマーキングにおいて、その印刷性はパッケ
ージ表面の梨地が微細であると悪くなる。その結果とし
てマーキング不良が生じ易くなる。他方、梨地面の粗さ
を粗くすると、モールド金型とパッケージとの離型性が
悪くなる。
This matte finish on the surface of the package is mainly performed to improve so-called marking, which is printing of the type, loft number, etc. on the surface of the package to identify the product. Here, in marking, the printability becomes worse if the surface of the package has a fine satin finish. As a result, marking defects are likely to occur. On the other hand, if the roughness of the satin surface is made rougher, the releasability between the mold and the package becomes worse.

なお、樹脂封止型半導体装置については、1980年1
月15日、株式会社工業調査会発行、日本マイクロエレ
クトロニクス協会線rrc化実装技術JP149〜P1
50に説明されている。
Regarding resin-sealed semiconductor devices, the 1980 January
Published by Kogyo Kenkyukai Co., Ltd., March 15th, Japan Microelectronics Association line RRC mounting technology JP149-P1
50.

〔発明の目的〕[Purpose of the invention]

本発明の1つの目的は、モールド型に対する離型性の優
れた樹脂封止半導体装置を提供することにある。
One object of the present invention is to provide a resin-sealed semiconductor device with excellent releasability from a mold.

本発明の他の目的は、マーキングの印刷性が優れている
とともに、モールド工程における離型性が優れた樹脂封
止型半導体装置を提供することにある。
Another object of the present invention is to provide a resin-sealed semiconductor device that has excellent marking printability and excellent mold releasability in a molding process.

本発明の他の目的は、前記半導体装置の製造に適したモ
ールド金型を提供することにある。
Another object of the present invention is to provide a mold suitable for manufacturing the semiconductor device.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。
A brief overview of typical inventions disclosed in this application is as follows.

すなわち、パッケージ表面における突起部の側面に所定
のテーパが設けられることにより、モールド型に対する
パッケージの離型性の向上が達成されるものである。
That is, by providing a predetermined taper on the side surface of the protrusion on the package surface, the releasability of the package from the mold can be improved.

〔実施例1〕 第1図(alは本発明による一実施例である、いわゆる
プラスチックリーデツドチップキャリア(PLCC)型
半導体装置の一部の断面図であり、第1開山)は前記半
導体装置の部分側面図である。
[Example 1] FIG. 1 (al is a cross-sectional view of a part of a so-called plastic leaded chip carrier (PLCC) type semiconductor device, which is an example of the present invention, and the first opening) shows the structure of the semiconductor device. FIG.

また、第2図は本実施例の半導体装置の概略斜視図であ
る。
Moreover, FIG. 2 is a schematic perspective view of the semiconductor device of this example.

第2図に示す如(、本実施例の半導体装置は、そのパッ
ケージlの四囲に多数のり一部2が埋設されており、該
リードの先端はパッケージ裏面に折り曲げられている。
As shown in FIG. 2, in the semiconductor device of this embodiment, a number of lead portions 2 are embedded around the four sides of a package 1, and the tips of the leads are bent on the back surface of the package.

さらに詳しく説明すれば、第1図(alに拡大して示す
如く、樹脂モールドにより形成されたパッケージ1内に
おいて、タブ3にペレット5が導電性樹脂あるいは金−
シリコン共晶からなるような結合材(図示せず、)によ
って取り付けられており、1亥ベレツト4は、それにお
けるポンディングパッド電極(図示しない)がリード2
の内端部と金ワイヤ5を介して電気的に接続されている
。そして、前記リード2のパッケージ外の部分(以下、
外部リードともいう。)はパッケージ1の側端近傍で下
方に折り曲げられ、さらに該パンケージ1の裏面周囲に
形成されている突出部6に沿って内側に折り曲げられ、
その先端部がパンケージ1の裏面に形成された凹部7に
挿入されてなる。
More specifically, as shown enlarged in FIG.
The bead 4 is attached by a bonding material (not shown), such as silicon eutectic, and the bonding pad electrode (not shown) thereon is attached to the lead 2.
The gold wire 5 is electrically connected to the inner end of the gold wire 5. Then, the portion of the lead 2 outside the package (hereinafter referred to as
Also called external lead. ) is bent downward near the side edge of the package 1, and further bent inward along the protrusion 6 formed around the back surface of the pan cage 1,
The tip end thereof is inserted into a recess 7 formed on the back surface of the pan cage 1.

前記突出部6はプリント基板への実装時等におけるリー
ド2の変形を防止する機能を有する。
The protrusion 6 has a function of preventing deformation of the lead 2 during mounting on a printed circuit board.

突出部6は連続した1個から成るのではなく、第1開山
)から明らかなように、各リードに1対1に対応される
。それ故に、突出部6の相互間に溝20が存在する。
The protrusions 6 do not consist of one continuous piece, but correspond to each lead on a one-to-one basis, as is clear from the first opening. Therefore, there are grooves 20 between the protrusions 6.

溝20は、たとえば次のような理由によって設けられる
The groove 20 is provided for the following reasons, for example.

すなわち、PLCCはそのリードの下端2aがプリント
基板のような配線基板(図示しない)の配線に、半田か
ら成るようなろう材によって電気的機械的に結合される
。PLCCの実装工程において、半田付けのために用い
られたフラックスのようなリードおよび配線を侵す恐れ
のある・不所望な反応物は、電子装置の信頼性を充分に
向上させる必要のある場合、洗浄され、除去される。溝
20が形成されていない場合、すなわち、複数のリード
に対し連続的な突出部が設けられている場合、その突出
部によって囲まれているパッケージの底面部分への洗浄
液の囲り込みは、掻く制限される。
That is, the lower ends 2a of the leads of the PLCC are electrically and mechanically coupled to the wiring of a wiring board (not shown) such as a printed circuit board using a brazing material such as solder. During the PLCC mounting process, undesirable reactants that may attack leads and wiring, such as flux used for soldering, must be cleaned if necessary to sufficiently improve the reliability of the electronic device. and removed. If the groove 20 is not formed, that is, if a continuous protrusion is provided for a plurality of leads, the cleaning liquid will not be trapped in the bottom part of the package surrounded by the protrusion. limited.

これに応じて不所望な反応物をリード2、ろう材層およ
び配線基板の配線層などの表面から充分に除去できなく
なる。上述のように溝2oが設けられている場合、パッ
ケージlの底面と配線基板との間の空間における洗浄液
の交換は、充分に良好になる。その結果、かかる空間部
分における不所望な反応物も充分に除去することができ
るようになる。
Accordingly, undesirable reactants cannot be sufficiently removed from the surfaces of the leads 2, the brazing material layer, the wiring layer of the wiring board, and the like. When the groove 2o is provided as described above, exchange of the cleaning liquid in the space between the bottom surface of the package l and the wiring board becomes sufficiently efficient. As a result, undesirable reactants in such spaces can also be sufficiently removed.

この実施例に従うと、第1開山)から明らかなように、
各突出部6の側面にテーパ角θが付けられる。このテー
パ角θは、後で第4図によって説明するモールド型8a
に対するパッケージ1の離型性を良くするために設定さ
れる。突出部6のリード2と直接的に対応される部分の
幅は、リード2に対する良好なガイドとさせるために、
リード2の幅と実質的に等しいか、もしくは第1開山)
に示されたようにリード2のそれよりも若干大きくされ
る。
According to this example, as is clear from the first opening),
A taper angle θ is attached to the side surface of each protrusion 6. This taper angle θ is determined by the mold type 8a, which will be explained later with reference to FIG.
It is set in order to improve the releasability of the package 1 against the mold. The width of the portion of the protrusion 6 that directly corresponds to the lead 2 is set such that it provides a good guide for the lead 2.
substantially equal to the width of lead 2 or the first opening)
As shown in Figure 2, it is made slightly larger than that of lead 2.

テーパ角θは、モールド型に対するパッケージ1の離型
性の点から、大きいことが望ましい0反面、テーパ角θ
は、溝20の断面積の減少を防ぐという点から、小さい
ことが望ましい、これらの点からテーパ角θは、3度な
いし20度、特に望ましくは15度にされることが望ま
しい。
The taper angle θ is desirably large from the viewpoint of releasability of the package 1 from the mold.
is desirably small in order to prevent the cross-sectional area of the groove 20 from decreasing. From these points of view, it is desirable that the taper angle θ is between 3 degrees and 20 degrees, particularly preferably 15 degrees.

第4図は、本実施例の半導体装置の製造に適用される本
発明による他の一実施例である金型を、そのモールド工
程の態様を含めて示す断面図である。
FIG. 4 is a sectional view showing a mold according to another embodiment of the present invention applied to manufacturing the semiconductor device of this embodiment, including aspects of the molding process.

前記金型8は、上金型8aおよび下金型8bで構成され
るものであり、それぞれに丁度対応する場所に凹部すな
わちキャビティが形成され、かつ下金型の凹部底面周囲
には半導体装置の突起部7に対応する凹部9が形成され
ている。この上金型8aと下金型8bの間に、ペレフト
の取り付けおよびワイヤボンディングが完了したリード
フレームを同図に示す如く挟持し、ゲートlOよりエポ
キシ樹脂を流入させ、上金型8aの凹部と下金型8bの
凹部とで形成されるキャビティ11内に該樹脂を充たす
ことにより、パッケージ形成が行われる。
The mold 8 is composed of an upper mold 8a and a lower mold 8b, and a recess, that is, a cavity, is formed at a location exactly corresponding to each mold, and a semiconductor device is formed around the bottom of the recess of the lower mold. A recess 9 corresponding to the protrusion 7 is formed. As shown in the figure, the lead frame with the pellet attached and the wire bonding completed is held between the upper mold 8a and the lower mold 8b, and the epoxy resin is flowed into the recess of the upper mold 8a through the gate IO. A package is formed by filling the resin into the cavity 11 formed by the recess of the lower mold 8b.

前記キャビティ11内に樹脂を充たし、所定時間経過し
た後、すなわち樹脂を硬化させた後、図示しないエジェ
クトピンの利用によって金型8からパッケージの取り外
しを行い、次いでフレームからリードの切断、外部リー
ドの折曲成形を行うことにより、本実施例の半導体装置
が完成される。
The cavity 11 is filled with resin, and after a predetermined period of time has elapsed, that is, after the resin has hardened, the package is removed from the mold 8 using an eject pin (not shown), and then the leads are cut from the frame and the external leads are removed. By performing bending, the semiconductor device of this example is completed.

樹脂はそれが硬化されると、その体積が若干減少される
。第2図に示されたように、複数のリードに対し複数の
突出部が形成される場合、パッケージ1を構成する樹脂
の全体的な収縮によって、突出部6の側面6a、もしく
は6b(第1開山))と、モールド型8b(第4図)と
の間に、比較的大きい応力が加わるようになる硬化収縮
によってもたらされる応力は、パッケージ1の中心から
離れれば、それに応じて増加される。側面6aもしくは
6bに加わる応力は、突出部6に対する剪断応力とみな
される。この応力は、また、パッケージ1の離型の際、
突出部6とモールド型8bとの相互の摩擦力を増加させ
る。突出部6の側面6a。
The resin is slightly reduced in volume when it is cured. As shown in FIG. 2, when a plurality of protrusions are formed for a plurality of leads, overall shrinkage of the resin constituting the package 1 causes side surfaces 6a or 6b of the protrusion 6 (the first The stress caused by the curing shrinkage, which results in a relatively large stress being applied between the opening (1)) and the mold 8b (FIG. 4), increases accordingly as the distance from the center of the package 1 increases. The stress applied to the side surface 6a or 6b is considered to be a shear stress on the protrusion 6. This stress also occurs when the package 1 is released from the mold.
The mutual frictional force between the protrusion 6 and the mold 8b is increased. Side surface 6a of protrusion 6.

6bに実質的にテーパ角θが与えられていない場合、上
記摩擦力は充分に大きくなり、離型を困難にさせる。
When the taper angle θ is not substantially given to 6b, the above-mentioned frictional force becomes sufficiently large, making release from the mold difficult.

この実施例に従うと、突出部6の側面6a、6bにテー
パ角θが与えられているので、樹脂が硬化収縮された際
に突出部6に加わる応力は、2つの方向、すなわちパッ
ケージ1の平面と実質的に同じ方向の横方向と、パッケ
ージ1の平面に対し実質的に垂直にされた方向とに分割
される。その結果として、樹脂の硬化収縮に伴って、パ
ッケージ1をモールド型8bから離型させるための応力
が生ずる。
According to this embodiment, since the taper angle θ is given to the side surfaces 6a and 6b of the protrusion 6, the stress applied to the protrusion 6 when the resin is cured and shrunk can be applied in two directions, that is, on the plane of the package 1. and a direction substantially perpendicular to the plane of the package 1. As a result, as the resin hardens and shrinks, stress is generated to release the package 1 from the mold 8b.

本実施例の半導体装置は、第1図fatおよび(blの
リード2の埋設面より上の上側パッケージ部分1aの表
面が、前記埋設面より下の下側パッケージ部分1bの表
面より粗(形成されている。第3図fa)および(b)
はその様子を拡大して示すものであり、同図fa)は第
1図1a)におけるA部を、同図中)は同じくB部を示
すものである。
In the semiconductor device of this embodiment, the surface of the upper package portion 1a above the buried surface of the leads 2 in FIG. Figure 3 fa) and (b)
1 shows the state in an enlarged manner, and fa) in the same figure shows part A in FIG. 1a), and part B in the same figure shows part B.

第4図の金型8は、製造される前記半導体装置のパッケ
ージ表面に対応して、上金型8aの凹部表面は粗い粗面
をもって形成され、下金型8bのそれは前記上型8aよ
り細かい粗面をもって形成されている。これら凹部表面
は、たとえば上金型8aが約13μmの表面粗さとされ
、下金型8bが6〜8μmの表面粗さとされる。
In the mold 8 of FIG. 4, the concave surface of the upper mold 8a is formed to have a rough surface, and that of the lower mold 8b is finer than that of the upper mold 8a, corresponding to the surface of the package of the semiconductor device to be manufactured. It is formed with a rough surface. For example, the surfaces of these recesses are made to have a surface roughness of about 13 μm in the upper mold 8a and 6 to 8 μm in the lower mold 8b.

第5図は、前記表面状態を拡大して示すもので、同図f
atは第4図におけるA部、同図中)は同じくB部を示
すものである。
FIG. 5 shows an enlarged view of the surface condition.
"at" indicates section A in FIG. 4, and "at" indicates section B in the same figure.

なお、モールド型3a、3bの主要部は、たとえば超硬
合金のような素材から構成され、放電加工技術のような
加工技術によって形成される。
The main parts of the molds 3a and 3b are made of a material such as cemented carbide, and are formed by a machining technique such as electrical discharge machining.

各モールド型の凹部表面は、放電加工の際に粗面となる
。粗面の程度、すなわち粗さは、放電加工の際の加工条
件によって決定される。各モールド型は、それと注入さ
れる樹脂中に混入されている酸化シリコン粉末を主成分
とするような比較的硬度の大きいフィラーとの相互に生
ずる摩擦によって、反復使用されるに従って摩耗される
。モールド型の凹部表面には、図示しないけれども、硬
質クロムメッキ層のような比較的薄い厚さの被覆層が形
成される。被覆層の表面は、下地材料と実質的に同じ粗
面となる。摩耗が進行した場合、たとえば古い被覆層が
除去され、再び新しい被覆層が形成される。従って、被
覆層はモールド型における一種の再生層を構成する。
The concave surface of each mold becomes rough during electrical discharge machining. The degree of roughness, that is, the roughness, is determined by the machining conditions during electrical discharge machining. Each mold is worn out as it is repeatedly used due to mutual friction between it and a filler having a relatively high hardness, such as a filler mainly composed of silicon oxide powder, which is mixed into the injected resin. Although not shown, a relatively thin coating layer such as a hard chrome plating layer is formed on the surface of the recessed portion of the mold. The surface of the covering layer has substantially the same roughness as the underlying material. If the wear progresses, for example, the old coating layer is removed and a new coating layer is formed again. Therefore, the covering layer constitutes a kind of reproduction layer in the mold.

ここで、一般に金型表面を粗い粗面で形成すると、該金
型からパッケージを取り外す工程における離型性が悪く
なり、そのためパッケージ欠は等の外観不良が発生し易
いという問題がある。特に、本実施例2の半導体装置の
如く、パンケージ裏面に突起部7を有するものは特に問
題が大きい。
Generally, if the surface of the mold is formed with a rough surface, the releasability in the step of removing the package from the mold will be poor, and therefore there is a problem in that external defects such as package chipping are likely to occur. In particular, a semiconductor device having a protrusion 7 on the back surface of a pan cage, such as the semiconductor device of Example 2, has a particularly serious problem.

一方、金型表面を細かい粗面で形成すると離型性は向上
するが、製造される半導体装置のパッケージ表面に付す
るマーキングの印刷性が低下するためマーキング不良を
引き起こす。
On the other hand, if the surface of the mold is formed with a finely rough surface, the mold releasability will be improved, but the printability of the marking applied to the package surface of the manufactured semiconductor device will be lowered, resulting in marking defects.

第5図のようにされた金型8を用いることにより、上側
パッケージ部分1aの表面を粗く形成することができる
ので、該上側パッケージ部分の表面に印刷性の高いマー
キングが達成され、その上、下金型とパッケージとの離
型性を向上させることができるので、作業性向上および
不良発生の防止を達成できる。特に、本実施例の如く構
造が複雑な下側パッケージ部分1bからなる半導体装置
については極めて有効である。
By using the mold 8 as shown in FIG. 5, the surface of the upper package part 1a can be formed to be rough, so that marking with high printability can be achieved on the surface of the upper package part, and furthermore, Since the releasability between the lower mold and the package can be improved, workability can be improved and defects can be prevented. Particularly, this embodiment is extremely effective for a semiconductor device including a lower package portion 1b having a complicated structure as in this embodiment.

〔効果〕〔effect〕

(1)、突出部のような段差を生ずる部分の側面にテー
パを与えたので、過大な応力が段差部に加わっていない
樹脂封止半導体装置を得ることができ、その結果として
パッケージ欠は等の外観不良の発生のない半導体装置を
得ることができる。
(1) Since the side surface of the part where a step occurs, such as a protrusion, is tapered, it is possible to obtain a resin-sealed semiconductor device in which no excessive stress is applied to the step, and as a result, package chipping is reduced. A semiconductor device without appearance defects can be obtained.

(2)、上金型の凹部内面の少なくとも一部が粗い粗面
で、かつ下金型の凹部内面が細かい粗面で仕上げられた
金型を用いて樹脂封止型半導体装置を製造することによ
り、モールド工程において少なくとも下金型については
離型性を向上させることができるので、パッケージ欠は
等の外観不良の発生を防止できる。
(2) Manufacturing a resin-sealed semiconductor device using a mold in which at least a part of the inner surface of the recess of the upper mold is finished with a rough surface, and the inner surface of the recess of the lower mold is finished with a fine rough surface. As a result, it is possible to improve the mold releasability of at least the lower mold in the molding process, thereby preventing appearance defects such as package chipping.

(3)、前記(2)により、半導体装置の歩留り向上を
達成できる。
(3) According to (2) above, it is possible to improve the yield of semiconductor devices.

(4)、前記(2)の金型を用いることにより、上側パ
ッケージ部分表面の少なくとも一部が粗い粗面からなる
半導体装置を製造できるので、該粗い粗面に印刷性の良
いマーキングが可能である。
(4) By using the mold described in (2) above, it is possible to manufacture a semiconductor device in which at least a part of the surface of the upper package portion has a rough surface, so that it is possible to mark the rough surface with good printability. be.

(5)、前記(3)および(4)により、信頼性の高い
マーキングが付された半導体装置を安価に提供できる。
(5) According to (3) and (4) above, a semiconductor device with highly reliable markings can be provided at low cost.

(6)、前記+11に記載した金型をPLCC型半導体
装置に適用することにより、該半導体装置はパッケージ
裏面が複雑であるため特に有効である。
(6) Applying the mold described in +11 above to a PLCC type semiconductor device is particularly effective since the semiconductor device has a complicated back surface of the package.

(7)、細かい粗面を持つモールド型と、注入される樹
脂に混入されているフィラーとの摩擦が、その細かい粗
面によって小さくなるので、長寿命のモールド型を得る
ことができる。
(7) Since the friction between the mold having a finely roughened surface and the filler mixed in the injected resin is reduced by the finely roughened surface, a mold with a long life can be obtained.

(8)、多(の段差部を持つことによって複雑な形状に
され、その結果高価となるモールドが、上記(ηによっ
て長寿命にされるので、実質的に安価なモールド型を得
る゛ことができる。
(8) A mold that is made to have a complicated shape and is therefore expensive due to the presence of multiple step portions can be made to have a long life due to the above (η), so it is possible to obtain a mold that is substantially cheaper. can.

以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。
Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.

たとえば、上側パンケージ部分の表面全体が粗い梨地面
で形成されている半導体装置について説明したが、これ
に限るものでなく、上側パッケージ部分の表面の一部、
すなわちマーキング部のみを粗くしたものであってもよ
い。
For example, although a semiconductor device has been described in which the entire surface of the upper package portion is formed of a rough matte surface, the present invention is not limited to this; a portion of the surface of the upper package portion,
In other words, only the marking portion may be made rough.

同様に前記半導体装置の製造に適用される金型について
も、上金型の内面全体が粗い梨地で形成されているもの
に限るものでな(、その一部のみが粗いものであっても
よいことはいうまでもない。
Similarly, the mold used for manufacturing the semiconductor device is not limited to one in which the entire inner surface of the upper mold is formed of a rough satin finish (although only a part of the inner surface may be rough). Needless to say.

上金型、下金型は、単に得るべきパッケージの上面、下
面(もしくは裏面)と対応されているにすぎないもので
あり、封止装置において上下のいずれに位置されても良
い、金型は金属以外でも良い。
The upper mold and the lower mold merely correspond to the upper surface and lower surface (or back surface) of the package to be obtained, and the molds may be located either above or below in the sealing device. It can be made of materials other than metal.

〔利用分野〕[Application field]

以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である、いわゆるPLCC
型半導体装置に適用した場合について説明したが、それ
に限定されるものではなく、たとえば、樹脂封止型半導
体装置であれば、いわゆるDIP型等の種々の形式の半
導体装置に適用して有効な技術である。
The above explanation will mainly focus on the field of application made by the present inventor, which is the so-called PLCC.
Although the description has been made regarding the case where the application is applied to a semiconductor device of the type semiconductor device, the present invention is not limited thereto. It is.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図talは、本発明による一実施例である半導体装
置を示す部分断面図、 第1図(b)は、前記半導体装置の部分側面図、第2図
は、前記半導体装置の概略を示す斜視図、第3図ia+
は、上側パンケージ部分の表面部を示す拡大断面図、 第3図(blは、下側パッケージ部分の表面部を示す拡
大断面図、 第4図は、本発明による他の一実施例である金型を示す
部分断面図、 第5図(alは、上金型の凹部表面部を示す拡大断面図
、 第5図(blは、下金型の凹部表面部を示す拡大断面図
である。 ■・・・パッケージ、1a・・・上側パッケージ部分、
1b・・・下側パッケージ部分、2・・・リード、3・
・・タブ、4・・・ペレット、5・・・ワイヤ、6・・
・突起部、7・・・凹部、8・・・金型、8a・・・上
金型、8b・・・下金型、9・・・凹部、10・・・ゲ
ート、11・・・キャビティ。 第  1  図 (b) 第  3  図
FIG. 1 is a partial sectional view showing a semiconductor device according to an embodiment of the present invention, FIG. 1B is a partial side view of the semiconductor device, and FIG. 2 is a schematic diagram of the semiconductor device. Perspective view, Figure 3 ia+
3 is an enlarged sectional view showing the surface part of the upper pancage part, FIG. 4 is an enlarged sectional view showing the surface part of the lower package part, and FIG. A partial sectional view showing the mold, Figure 5 (al is an enlarged sectional view showing the surface of the recess of the upper mold, and Figure 5 (bl is an enlarged sectional view showing the surface of the recess of the lower mold). ...Package, 1a...Upper package part,
1b...lower package part, 2...lead, 3.
...Tab, 4...Pellet, 5...Wire, 6...
・Protrusion, 7... Recess, 8... Mold, 8a... Upper mold, 8b... Lower mold, 9... Recess, 10... Gate, 11... Cavity . Figure 1 (b) Figure 3

Claims (1)

【特許請求の範囲】 1、複数のリード線材によって構成される平面に対して
の一方の側に位置するパッケージ表面に、上記平面の延
長方向に対し異なる方向にされた側面を持つ段差部が形
成されてなる樹脂封止半導体装置であって、上記側面に
テーパが与えられてなることを特徴とする樹脂封止半導
体装置。 2、上記段差部は、プラスチックリーデッドチップキャ
リア型パッケージにおける各リード線材に対応された凸
部から成ることを特徴とする特許請求の範囲第1項記載
の樹脂封止半導体装置。 3、上記平面に対する他方の側に位置するパッケージ表
面にマーキング部が形成され、少なくとも上記マーキン
グ部が粗面にされてなることを特徴とする特許請求の範
囲第2項記載の樹脂封止半導体装置。 4、上記平面に対する上記他方の側に位置するパッケー
ジ表面が粗い粗面にされ、上記一方の側に位置するパッ
ケージ表面が細かい粗面にされて成ることを特徴とする
特許請求の範囲第3項記載の樹脂封止半導体装置。 5、上記パッケージが樹脂モールド法によって形成され
てなり、上記パッケージ表面の粗面がモールド型によっ
て決定されて成ることを特徴とする特許請求の範囲第3
項または第4項記載の樹脂封止半導体装置。 6、パッケージ表面が粗面にされている樹脂封止型半導
体装置であって、リード線材によって構成される平面に
対する一方の側におけるパッケージ表面のうち少なくと
もマーキング部が粗い粗面で形成され、上記平面に対す
る他方の側におけるパッケージ表面が細かい粗面で形成
されてなる樹脂半導体装置。 7、パッケージ裏面にリード変形防止用の凸部が形成さ
れているプラスチックリーデッドチップキャリア型パッ
ケージからなることを特徴とする特許請求の範囲第6項
記載の半導体装置。 8、樹脂封止型半導体装置製造用のモールド金型であっ
て、上金型の凹部内面の少なくとも一部が粗い梨地で形
成され、下金型の内面が細かい梨地で形成されてなるモ
ールド金型。 9、下金型の凹部底面周囲に凹部が形成されていること
を特徴とする特許請求の範囲第7項記載のモールド金型
[Claims] 1. On the surface of the package located on one side of a plane formed by a plurality of lead wires, a stepped portion is formed with a side surface facing in a different direction with respect to the direction of extension of the plane. 1. A resin-sealed semiconductor device characterized in that the side surface is tapered. 2. The resin-sealed semiconductor device according to claim 1, wherein the stepped portion is comprised of a convex portion corresponding to each lead wire in a plastic leaded chip carrier type package. 3. The resin-sealed semiconductor device according to claim 2, wherein a marking portion is formed on the surface of the package located on the other side with respect to the plane, and at least the marking portion has a roughened surface. . 4. Claim 3, characterized in that the package surface located on the other side with respect to the plane is made into a rough surface, and the package surface located on the one side is made into a finely roughened surface. The resin-sealed semiconductor device described above. 5. Claim 3, wherein the package is formed by a resin molding method, and the rough surface of the package is determined by the mold type.
The resin-sealed semiconductor device according to item 1 or 4. 6. A resin-sealed semiconductor device with a roughened package surface, wherein at least a marking portion of the package surface on one side of the plane formed by the lead wire is formed with a rough surface, and the flat surface A resin semiconductor device in which a package surface on the other side is formed with a finely roughened surface. 7. The semiconductor device according to claim 6, which is comprised of a plastic leaded chip carrier type package in which a convex portion for preventing lead deformation is formed on the back surface of the package. 8. A mold for manufacturing resin-sealed semiconductor devices, in which at least a part of the inner surface of the recess of the upper mold is formed with a rough satin finish, and the inner surface of the lower mold is formed with a fine satin finish. Type. 9. The mold according to claim 7, wherein a recess is formed around the bottom surface of the recess of the lower mold.
JP60110357A 1985-05-24 1985-05-24 Resin-sealed semiconductor device and molding die used for manufacture thereof Pending JPS61269338A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60110357A JPS61269338A (en) 1985-05-24 1985-05-24 Resin-sealed semiconductor device and molding die used for manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60110357A JPS61269338A (en) 1985-05-24 1985-05-24 Resin-sealed semiconductor device and molding die used for manufacture thereof

Publications (1)

Publication Number Publication Date
JPS61269338A true JPS61269338A (en) 1986-11-28

Family

ID=14533724

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60110357A Pending JPS61269338A (en) 1985-05-24 1985-05-24 Resin-sealed semiconductor device and molding die used for manufacture thereof

Country Status (1)

Country Link
JP (1) JPS61269338A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0221728U (en) * 1988-07-28 1990-02-14
US6146919A (en) * 1997-07-09 2000-11-14 Micron Technology, Inc. Package stack via bottom leaded plastic (BLP) packaging
WO2013047606A1 (en) * 2011-09-30 2013-04-04 株式会社カネカ Molded resin body for surface-mounted light-emitting device, manufacturing method thereof, and surface-mounted light-emitting device
EP2136414B1 (en) * 2007-03-26 2015-12-23 Nichia Corporation Side-view light emitting device
JP2018059925A (en) * 2016-09-28 2018-04-12 旭化成エレクトロニクス株式会社 Magnetic sensor

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0221728U (en) * 1988-07-28 1990-02-14
US6537051B2 (en) 1997-07-09 2003-03-25 Micron Technology, Inc. Encapsulation mold with a castellated inner surface
US6166328A (en) * 1997-07-09 2000-12-26 Micron Technology, Inc. Package stack via bottom leaded plastic (BLP) packaging
US6188021B1 (en) 1997-07-09 2001-02-13 Micron Technology, Inc. Package stack via bottom leaded plastic (BLP) packaging
US6213747B1 (en) * 1997-07-09 2001-04-10 Micron Technology, Inc. Package stack via bottom leaded plastic (BLP) packaging
US6265660B1 (en) 1997-07-09 2001-07-24 Micron Technology, Inc. Package stack via bottom leaded plastic (BLP) packaging
US6146919A (en) * 1997-07-09 2000-11-14 Micron Technology, Inc. Package stack via bottom leaded plastic (BLP) packaging
US6899534B2 (en) 1997-07-09 2005-05-31 Micron Technology, Inc. Mold assembly for a package stack via bottom-leaded plastic (blp) packaging
US7094046B2 (en) 1997-07-09 2006-08-22 Micron Technology, Inc. Mold assembly for a package stack via bottom-leaded plastic (BLP) packaging
EP2136414B1 (en) * 2007-03-26 2015-12-23 Nichia Corporation Side-view light emitting device
WO2013047606A1 (en) * 2011-09-30 2013-04-04 株式会社カネカ Molded resin body for surface-mounted light-emitting device, manufacturing method thereof, and surface-mounted light-emitting device
JPWO2013047606A1 (en) * 2011-09-30 2015-03-26 株式会社カネカ RESIN MOLDED BODY FOR SURFACE MOUNT LIGHT EMITTING DEVICE, ITS MANUFACTURING METHOD, AND SURFACE MOUNTED LIGHT EMITTING DEVICE
US9793456B2 (en) 2011-09-30 2017-10-17 Kaneka Corporation Molded resin body for surface-mounted light-emitting device, manufacturing method thereof, and surface-mounted light-emitting device
JP2018059925A (en) * 2016-09-28 2018-04-12 旭化成エレクトロニクス株式会社 Magnetic sensor

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