JPS6329408B2 - - Google Patents

Info

Publication number
JPS6329408B2
JPS6329408B2 JP15677679A JP15677679A JPS6329408B2 JP S6329408 B2 JPS6329408 B2 JP S6329408B2 JP 15677679 A JP15677679 A JP 15677679A JP 15677679 A JP15677679 A JP 15677679A JP S6329408 B2 JPS6329408 B2 JP S6329408B2
Authority
JP
Japan
Prior art keywords
electrode film
electrode
metal foil
cathode electrode
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP15677679A
Other languages
Japanese (ja)
Other versions
JPS5680140A (en
Inventor
Hitoshi Oonuki
Hiroshi Soeno
Keiichi Morita
Noboru Baba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15677679A priority Critical patent/JPS5680140A/en
Publication of JPS5680140A publication Critical patent/JPS5680140A/en
Publication of JPS6329408B2 publication Critical patent/JPS6329408B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01027Cobalt [Co]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0133Ternary Alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor

Description

【発明の詳細な説明】 本発明は半導体装置に係り、特に圧接型半導体
装置の電極構造に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to an electrode structure of a pressure contact type semiconductor device.

例えばトランジスタ、ゲートターンオフ型ある
いは電界効果型サイリスタのような3端子半導体
装置においては、半導体基体の一主表面に異なる
2種の半導体領域(一方の主電極領域および制御
電極領域)が露出しこれらの半導体領域に個別に
電極膜(一方の主電極および制御電極)が形成さ
れるのが一般的である。そして、一方の主電極領
域の各部を均一かつ効果的に制御するために、平
面的にみて一方の主電極領域は例えば多数の長方
形等に細分割され、制御電極領域がそれら一方の
主電極領域をとり囲むように形成される場合が多
い。更に、一方の主電極面を制御電極面よりも高
くして、これら多数の一方の主電極面に同時に接
するように一方の主電極板を加圧接触させること
により一方の主電極を形成することが、特に電力
用半導体装置において行なわれている。
For example, in a three-terminal semiconductor device such as a transistor, gate turn-off type, or field effect thyristor, two different types of semiconductor regions (one main electrode region and one control electrode region) are exposed on one main surface of a semiconductor substrate. Generally, electrode films (one main electrode and one control electrode) are formed individually in the semiconductor region. In order to uniformly and effectively control each part of one of the main electrode regions, one of the main electrode regions is subdivided into a large number of rectangles when viewed in plan, and the control electrode region is divided into one of the main electrode regions. It is often formed to surround the Furthermore, one main electrode is formed by making one main electrode surface higher than the control electrode surface and bringing one main electrode plate into pressure contact with these many one main electrode surfaces simultaneously. This is particularly practiced in power semiconductor devices.

このような半導体装置の一例を、ゲートターン
オフサイリスタを例にとつて図面を用いて説明す
る。第1図はこの種ゲートターンオフサイリスタ
の従来構造の一例を示す。図において、Si半導体
基体1はp型エミツタ層14、n型ベース層1
3、p型ベース層12およびn型エミツタ層11
の積層構造を有する。n型エミツタ層11が前述
の一方の主電極領域、p型ベース層12が制御電
極領域にそれぞれ相当し、p型エミツタ層14は
他方の主電極領域である。なお101はSiO2
面保護膜である。
An example of such a semiconductor device will be described with reference to the drawings, taking a gate turn-off thyristor as an example. FIG. 1 shows an example of a conventional structure of this type of gate turn-off thyristor. In the figure, a Si semiconductor substrate 1 includes a p-type emitter layer 14 and an n-type base layer 1.
3. p-type base layer 12 and n-type emitter layer 11
It has a laminated structure. The n-type emitter layer 11 corresponds to one of the aforementioned main electrode regions, the p-type base layer 12 corresponds to the control electrode region, and the p-type emitter layer 14 corresponds to the other main electrode region. Note that 101 is a SiO 2 surface protective film.

また、n型エミツタ層11の表面露出部には一
方の主電極膜111が、p型ベース層12の表面
露出部には制御電極膜121が、p型エミツタ層
14の表面露出部には他方の主電極膜141がそ
れぞれ形成されている。ここで、n型エミツタ層
11とp型ベース層12の電極形成面は各半導体
層の積層方向に段差を有している。すなわちn型
エミツタ層11はp型ベース層12の電極形成面
より突出したメサ頂部に形成されている。そして
n型エミツタ層11の露出部にはカソード電極膜
111が、p型ベース層12にはゲート電極膜1
21がほぼ同じ厚さで形成されている。したがつ
てこれら2つの電極膜もまた、段差を有してい
る。これらの電極膜には例えばAlが使用される。
Further, one main electrode film 111 is placed on the exposed surface part of the n-type emitter layer 11, a control electrode film 121 is placed on the exposed surface part of the p-type base layer 12, and the other main electrode film 121 is placed on the exposed surface part of the p-type emitter layer 14. Main electrode films 141 are formed respectively. Here, the electrode formation surfaces of the n-type emitter layer 11 and the p-type base layer 12 have a step in the stacking direction of each semiconductor layer. That is, the n-type emitter layer 11 is formed at the top of the mesa that protrudes from the electrode formation surface of the p-type base layer 12. A cathode electrode film 111 is provided on the exposed portion of the n-type emitter layer 11, and a gate electrode film 1 is provided on the p-type base layer 12.
21 are formed with approximately the same thickness. Therefore, these two electrode films also have a step difference. For example, Al is used for these electrode films.

p型エミツタ層14の露出した主表面にはアノ
ード電極膜141が形成され、アノード電極膜1
41にはアノード電極板3がろう材(図示せず)
により接着されている。
An anode electrode film 141 is formed on the exposed main surface of the p-type emitter layer 14.
41, the anode electrode plate 3 is a brazing material (not shown)
It is glued by.

多数に分割されたカソード電極膜111上には
カソード電極板2が載置され、良好な接触を図つ
て図中矢印の方向に加圧される。このカソード電
極板2とカソード電極膜111とは、半導体装置
運転時の発熱に伴う熱歪を吸収するためにろう接
されない。カソード電極板およびアノード電極板
には例えばW、Moのように熱膨張係数が半導体
基体の材料であるSiのそれと近いものが使用され
る。
The cathode electrode plate 2 is placed on the cathode electrode film 111 divided into many parts, and is pressed in the direction of the arrow in the figure to ensure good contact. The cathode electrode plate 2 and the cathode electrode film 111 are not soldered to each other in order to absorb thermal strain caused by heat generation during operation of the semiconductor device. For the cathode electrode plate and the anode electrode plate, materials such as W and Mo, whose coefficient of thermal expansion is close to that of Si, which is the material of the semiconductor substrate, are used.

上述したカソード電極板2のカソード電極膜1
11への加圧は両者の電気抵抗を減らすため通常
200Kg/cm2程度加えられる。
Cathode electrode film 1 of the cathode electrode plate 2 described above
Normally, pressure is applied to 11 to reduce the electrical resistance between the two.
Approximately 200Kg/cm2 can be added.

また、図示されていないが、ゲート電極膜12
1の適宜部分にはp型ベース領域12と外部とを
結ぶためのゲートリードが接続される。更にカソ
ード電極板2およびアノード電極板3にはそれぞ
れ例えばCuからなる外部電極板が連なり、外部
電極板間を絶縁筒で結ぶことにより半導体基体を
密封する。ゲートリードは通常上述の絶縁筒ある
いは一方の外部電極板を貫通して外部へ導かれ
る。
Although not shown, the gate electrode film 12
A gate lead for connecting the p-type base region 12 to the outside is connected to an appropriate portion of the p-type base region 1 . Further, external electrode plates made of, for example, Cu are connected to each of the cathode electrode plate 2 and the anode electrode plate 3, and the semiconductor substrate is sealed by connecting the external electrode plates with an insulating cylinder. The gate lead usually passes through the above-mentioned insulating tube or one of the external electrode plates and is guided to the outside.

上述の構造の半導体装置はカソード電極膜から
の集電機構、カソード電極板とカソード電極膜を
加圧接触することによる熱歪の緩和、n型エミツ
タ層の分散化によるターンオフ動作の均整化等の
点で特に電力用装置に適したものである。しかし
なお、次の点で改善すべき問題点が存在する。
The semiconductor device with the above structure has a current collection mechanism from the cathode electrode film, relaxation of thermal strain by bringing the cathode electrode plate and cathode electrode film into pressure contact, and equalization of turn-off operation by dispersing the n-type emitter layer. In this respect, it is particularly suitable for power equipment. However, there are still problems that need to be improved in the following points.

それはカソード電極膜111が加圧下でヒート
サイクルにさらされる点に帰因する。すなわち、
上述の如くこの種半導体装置では通常200Kg/cm2
以上の加圧力が必要である。かつ運転時には半導
体基体の発熱により100〜150℃まで昇温する一
方、休止時には室温に戻る過程が繰り返される。
このような条件のもとではカソード電極膜が極め
て変形しやすいことが明らかとなつた。カソード
電極膜の変形は著しい場合にはその幅が2倍にも
延長されるほどである。その結果、カソード電極
膜がゲート電極膜と接触し半導体装置が動作不能
となる事故が生ずる。第2図はカソード電極の変
形の一態様を示すものであり、図においてカソー
ド電極膜111は加圧下のヒートサイクルによつ
てつぶれ、ゲート電極膜121と接触している。
This is due to the fact that the cathode electrode film 111 is exposed to heat cycles under pressure. That is,
As mentioned above, this type of semiconductor device usually has a weight of 200Kg/cm 2
A pressure greater than that is required. During operation, the temperature rises to 100 to 150°C due to the heat generated by the semiconductor substrate, while the process of returning to room temperature during rest is repeated.
It has become clear that the cathode electrode film is extremely easily deformed under such conditions. In cases where the deformation of the cathode electrode film is significant, its width may be doubled. As a result, an accident occurs in which the cathode electrode film comes into contact with the gate electrode film and the semiconductor device becomes inoperable. FIG. 2 shows one mode of deformation of the cathode electrode, and in the figure, the cathode electrode film 111 is crushed by the heat cycle under pressure and is in contact with the gate electrode film 121.

また、直ちに第2図に示すような短絡事故が生
じないまでも、多数の分散されたカソード電極膜
の一部において若干変形が生じ、そのためにカソ
ード電極膜間で加圧力が不均一となり、その程度
が進んでカソード電極板が傾斜する場合もある。
このような場合には、半導体基体の端部近傍にお
いてベース電極膜とカソード電極板とが接触事故
を起こす。
Furthermore, even if a short circuit accident as shown in Figure 2 does not occur immediately, some deformation may occur in some of the many dispersed cathode electrode films, resulting in uneven pressure between the cathode electrode films. In some cases, the degree of damage may progress and the cathode electrode plate may become tilted.
In such a case, a contact accident occurs between the base electrode film and the cathode electrode plate near the end of the semiconductor substrate.

いずれの接触事故も例えば10000回等の多数回
のヒートサイクルを経て発生し易いものであり、
それだけに従来このような点は見過ごされがちで
あつたのが実情である。
Any type of contact accident is likely to occur after a large number of heat cycles, such as 10,000 times.
The reality is that this point has tended to be overlooked in the past.

なお、同様の問題点はゲートターンオフサイリ
スタに限らず、また電極膜あるいは電極板の材質
によらず存在する。更に、電極板と電極膜間の加
圧力を、両者間の接触抵抗が実用上の範囲内であ
るようにした場合は加圧力によらず上述の問題点
がひきおこされる。
Note that similar problems exist not only in gate turn-off thyristors, but also regardless of the material of the electrode film or electrode plate. Furthermore, if the pressure applied between the electrode plate and the electrode film is such that the contact resistance between the two is within a practical range, the above-mentioned problem will occur regardless of the pressure applied.

本発明の目的は上述した従来構造での問題点を
解決し、加圧下のヒートサイクルが加えられても
電極間の短絡が起らない電極構造を有する半導体
装置を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to solve the problems with the conventional structure described above, and to provide a semiconductor device having an electrode structure in which short circuits between electrodes do not occur even when heat cycles under pressure are applied.

この目的を達成するために本発明の特徴とする
ところは、一方の主表面側に異種の電極膜が互い
にその頂面が段差を持つように配置された半導体
基体と、半導体基体の一方の主表面側の突出した
方の電極膜に加圧接触される電極板と、上述の突
出した方の電極膜と電極板間に介在し、加圧下に
おいて突出した電極膜の頂面端部を包囲する金属
箔とを有する点にある。
In order to achieve this object, the present invention is characterized by a semiconductor substrate in which different types of electrode films are arranged on one main surface side so that the top surfaces thereof have a step difference, and one main surface side of the semiconductor substrate. An electrode plate that is pressed into contact with the protruding electrode film on the surface side, and an electrode plate that is interposed between the protruding electrode film and the electrode plate and surrounds the top end of the protruding electrode film under pressure. The point is that it has a metal foil.

本発明では、上述した金属箔が加圧下で上述の
突出した電極膜の頂面に圧接され電極膜と電極板
間を電気的に接続する。それと同時に電極膜頂面
端部のすぐ外側では加圧のため金属箔がカソード
電極の形状にくぼむように変形し、電極膜の側端
で加圧方向と鋭角をもつて交わる。これは、電極
膜が加圧により変形し薄くなると、下地である硬
い半導体基体の影響で見掛け上の硬さが増加し、
金属箔の硬さを越えると、その後は金属箔が加圧
力で変形するようになるためである。この金属箔
の変形は電極膜頂面の全周にわたり、電極膜の加
圧による変形がある程度以上進行するのを阻止す
る。したがつて、電極膜の変形は実用上問題のな
い程度に制限され、電極間の短絡が防止される。
In the present invention, the metal foil described above is brought into contact with the top surface of the protruding electrode film under pressure to electrically connect the electrode film and the electrode plate. At the same time, just outside the top end of the electrode film, the metal foil is deformed into the shape of the cathode due to pressure, and intersects the direction of pressure at an acute angle at the side edge of the electrode film. This is because when the electrode film deforms and becomes thinner due to pressure, its apparent hardness increases due to the influence of the underlying hard semiconductor substrate.
This is because once the hardness of the metal foil is exceeded, the metal foil begins to deform due to the applied pressure. This deformation of the metal foil extends over the entire circumference of the top surface of the electrode film, and prevents deformation of the electrode film due to pressure from proceeding beyond a certain level. Therefore, deformation of the electrode film is limited to a level that causes no practical problems, and short circuits between the electrodes are prevented.

以下、本発明の実施例を図面を用いて説明す
る。第3図は本発明の一実施例ゲートターンオフ
サイリスタの要部断面を示す。第3図において第
1図と同じ部分は第1図におけると同じ符号で示
す。本実施例ではカソード電極膜111とカソー
ド電極板2との間にFe−Ni−Co合金からなる箔
4が介在されている。箔4はカソード電極膜11
1を全て覆う面積を有している。この箔4は
Fe28%、Ni16%、残部Coの合金を900℃で2時
間加熱した後水冷し、圧延して約30μmの厚さと
した後、歪を除去するために700℃で1時間焼鈍
して得られた。熱膨張係数は4.5×10-6/℃であ
る。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 shows a cross section of a main part of a gate turn-off thyristor according to an embodiment of the present invention. In FIG. 3, the same parts as in FIG. 1 are designated by the same reference numerals as in FIG. In this embodiment, a foil 4 made of a Fe--Ni--Co alloy is interposed between the cathode electrode film 111 and the cathode electrode plate 2. Foil 4 is cathode electrode film 11
It has an area that completely covers 1. This foil 4
An alloy of 28% Fe, 16% Ni, and the balance Co was heated at 900℃ for 2 hours, cooled with water, rolled to a thickness of about 30μm, and annealed at 700℃ for 1 hour to remove strain. . The coefficient of thermal expansion is 4.5×10 -6 /°C.

また、半導体基体の直径は30mmであり、その一
方主表面側に幅約200μm、長さ約6mmのn型エ
ミツタ層11が26本ずつ2列にわたつて形成され
ている。カソード電極膜111およびゲート電極
膜121はAlからなり、厚さは約10μmである。
カソード電極板はWからなり、200Kg/cm2で金属
箔4を介しカソード電極膜に圧接されている。ま
た、カソード電極膜111とゲート電極膜121
のそれぞれの頂面の段差は約20μmである。
The diameter of the semiconductor substrate is 30 mm, and two rows of 26 n-type emitter layers 11 each having a width of about 200 μm and a length of about 6 mm are formed on the main surface side. The cathode electrode film 111 and the gate electrode film 121 are made of Al and have a thickness of about 10 μm.
The cathode electrode plate is made of W and is pressed to the cathode electrode film through a metal foil 4 at a pressure of 200 kg/cm 2 . In addition, the cathode electrode film 111 and the gate electrode film 121
The height difference between the top surfaces of each is approximately 20 μm.

このような半導体装置に30℃と120℃間のヒー
トサイクルを10000回施した。その結果、カソー
ド電極膜111は第4図に示すようにわずかに変
形はしているものの、金属箔4によつてその変形
が阻止されていることが明らかとなつた。一方、
第1図に示す従来例に同様のヒートサイクル試験
を施したところ、カソード電極膜は著しくつぶれ
ており、一部のカソード電極膜は第2図に示すよ
うにゲート電極膜と接触していた。このように、
本実施例によれば圧接型構造の半導体装置におけ
る電極膜のつぶれを防止することに効果がある。
Such a semiconductor device was subjected to heat cycles between 30°C and 120°C 10,000 times. As a result, it became clear that although the cathode electrode film 111 was slightly deformed as shown in FIG. 4, the deformation was prevented by the metal foil 4. on the other hand,
When the conventional example shown in FIG. 1 was subjected to a similar heat cycle test, the cathode electrode film was significantly crushed, and some of the cathode electrode film was in contact with the gate electrode film as shown in FIG. 2. in this way,
This embodiment is effective in preventing collapse of the electrode film in a semiconductor device of pressure contact type structure.

本実施例と同等の効果は金属箔としてFe−Ni
合金を用いた場合でも達成される。一例を示せ
ば、Fe35%、Ni65%の合金に上述のFe−Ni−Co
合金の場合と同様の処理を施して得られた厚さ約
30μmの箔を用いた場合でもFe−Ni−Co合金箔
と同等の成績が得られた。
The same effect as this example can be obtained using Fe-Ni as the metal foil.
This can also be achieved using alloys. To give an example, the above-mentioned Fe-Ni-Co is added to an alloy of 35% Fe and 65% Ni.
The thickness obtained by applying the same treatment as in the case of alloys is approx.
Even when a 30 μm foil was used, the same results as Fe-Ni-Co alloy foil were obtained.

なお、上述の実施例において、半導体装置使用
時にカソード電極膜と接している部分以外の金属
箔がたれ下り、ゲート電極膜と接触する問題は全
然生じなかつた。これは、金属箔として比較的硬
度の大きい金属を用いたため、またカソード電極
膜と接している部分以外では金属箔に何らの加圧
力が加わらないためと考えられる。
In the above embodiment, there was no problem that the metal foil other than the portion in contact with the cathode electrode film drooped down and came into contact with the gate electrode film during use of the semiconductor device. This is considered to be because a metal with relatively high hardness was used as the metal foil, and also because no pressing force was applied to the metal foil in areas other than those in contact with the cathode electrode film.

上述の実施例のように、金属箔としてFe−Ni
−CoまたはFe−Ni合金等組成、処理法によつて
その熱膨張係数を変化し得るものを用いるときは
その熱膨張係数を半導体およびカソード電極板の
それにできるだけ近づけることがこれらの間での
ステイツキング現象を防止する上で好ましい。ま
た、これらの合金は容易に100μm以下の箔に形
成できかつ安価なので好ましい。なお、Fe−Ni
−Co合金の場合、Niが27.5〜31wt%、Coが15〜
20wt%の範囲からずれると、またFe−Ni合金の
場合、Niが30〜42wt%の範囲からずれると熱膨
張係数が大きくなり、カソード電極板との間でス
テイツキング現象を起こし易くなるので好ましく
ない。
As in the above embodiment, Fe-Ni is used as the metal foil.
When using a material whose thermal expansion coefficient can be changed depending on the composition and processing method, such as -Co or Fe-Ni alloy, it is important to make the thermal expansion coefficient as close as possible to that of the semiconductor and cathode electrode plate. This is preferable in terms of preventing the king phenomenon. Further, these alloys are preferred because they can be easily formed into foils of 100 μm or less and are inexpensive. In addition, Fe−Ni
−For Co alloy, Ni is 27.5~31wt% and Co is 15~
If Ni deviates from the range of 20 wt%, or in the case of Fe-Ni alloys, if Ni deviates from the range of 30 to 42 wt%, the coefficient of thermal expansion will increase and the staking phenomenon with the cathode electrode plate is likely to occur, so this is preferable. do not have.

また、金属箔としてAl、Ag等を用いることも
検討したが、Alは高温(約80℃以上)で著しく
軟化してゲート電極板と接触する危険があり、
Agは熱膨張係数がカソード電極板より著しく大
きいのでカソード電極板との間でステイツキング
現象を生じ好しくないことが明らかとなつた。
We also considered using Al, Ag, etc. as the metal foil, but Al softens significantly at high temperatures (approximately 80°C or higher) and risks coming into contact with the gate electrode plate.
It has become clear that since Ag has a significantly larger coefficient of thermal expansion than the cathode electrode plate, it causes a staking phenomenon with the cathode electrode plate, which is undesirable.

以上、本発明をゲートターンオフサイリスタの
実施例について説明したが、本発明はこれに限ら
れず広く適用できるものである。
Although the present invention has been described above with reference to an embodiment of a gate turn-off thyristor, the present invention is not limited to this and can be widely applied.

まず半導体装置としてはトランジスタ、高周波
サイリスタ、電界効果型サイリスタ等にも応用で
きるし、それらの半導体基体内部の構造によらず
適用できる。例えば第5図に示すように、半導体
基体としては段差がなく、電極膜の方に段差があ
るものであつてもよい。また、加圧下のヒートサ
イクルによる電極膜のつぶれは電極膜としてAl
以外の金属、例えばAl−Cu合金、Cr、Ti、Ni、
Mo等を用いた場合でも、またこれらの金属を適
宜積層させた場合でも、程度の差はあれ、生ずる
ものである。したがつて、本発明は電極膜の種類
によらず有効である。
First, the present invention can be applied to semiconductor devices such as transistors, high-frequency thyristors, and field-effect thyristors, regardless of the internal structure of their semiconductor substrates. For example, as shown in FIG. 5, the semiconductor substrate may have no level difference, but the electrode film may have a level difference. In addition, the collapse of the electrode film due to heat cycles under pressure is caused by the fact that the electrode film is made of aluminum.
Other metals, such as Al-Cu alloy, Cr, Ti, Ni,
Even if Mo or the like is used, or if these metals are appropriately laminated, this problem occurs to varying degrees. Therefore, the present invention is effective regardless of the type of electrode film.

金属箔としては、加圧によつて突出した電極膜
の頂面端部を包囲するものであればその厚さは問
わない。すなわち、加圧時に加圧力の方向と金属
箔とが上述の突出した電極膜(例えば第3図のカ
ソード電極膜111)の頂面端部において鋭角で
交わるような条件が大切なのであり、この条件を
満たす限り、金属箔の厚さあるいは突出した電極
膜の形状(断面、平面とも)には無関係なのであ
る。
The thickness of the metal foil does not matter as long as it surrounds the top end of the electrode film that protrudes under pressure. In other words, it is important that the direction of the pressurizing force and the metal foil intersect at an acute angle at the top edge of the protruding electrode film (for example, the cathode electrode film 111 in FIG. 3) mentioned above during pressurization. As long as this is satisfied, it is irrelevant to the thickness of the metal foil or the shape (both cross-section and plane) of the protruding electrode film.

金属箔の硬度は、突出した電極膜の硬度よりも
高いことが本発明の効果を強調する上で望まし
い。
In order to emphasize the effects of the present invention, it is desirable that the hardness of the metal foil be higher than the hardness of the protruding electrode film.

また、金属箔は上述の要求を満たす限り複数枚
を重ねて用いてもよい。あるいは、当接すべき電
極膜群の全てを一枚の箔で覆わずに、複数枚に分
割した箔を用いることもできる。
Furthermore, a plurality of metal foils may be stacked and used as long as the above-mentioned requirements are met. Alternatively, instead of covering the entire group of electrode films to be brought into contact with a single sheet of foil, it is also possible to use foils divided into a plurality of sheets.

以上の諸点を考慮すれば、本発明に適用される
金属箔の材料としては実施例のものに限られず広
い範囲から選択することが可能である。
Taking the above points into consideration, the material of the metal foil applied to the present invention is not limited to those of the embodiments, but can be selected from a wide range.

また、電極板(第3図に符号2で示される)と
しては通常この種半導体装置に用いられる全ての
ものが使用可能であることは言うまでもない。
It goes without saying that all the electrode plates (indicated by reference numeral 2 in FIG. 3) that are normally used in semiconductor devices of this type can be used.

以上詳細に説明したように、本発明によれば、
圧接型構造の半導体装置において、電極間の短絡
を防止することに効果がある。
As explained in detail above, according to the present invention,
This is effective in preventing short circuits between electrodes in a semiconductor device having a pressure contact type structure.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一従来例ゲートターンオフサ
イリスタの平面図aおよびその−′断面要図
b、第2図は第1図bに示す従来例に加圧下ヒー
トサイクル試験を施した後の要部断面図、第3図
は本発明の一実施例ゲートターンオフサイリスタ
の断面図、第4図は第3図の要部拡大断面図、第
5図は本発明の他の実施例を示す図である。 1……半導体基体、2……カソード電極板、3
……アノード電極板、4……金属箔。
Figure 1 shows a plan view (a) and a schematic cross-sectional view (b) of a conventional gate turn-off thyristor according to the present invention, and Figure 2 shows the view of the conventional example shown in Figure 1 (b) after being subjected to a heat cycle test under pressure. 3 is a sectional view of a gate turn-off thyristor according to an embodiment of the present invention, FIG. 4 is an enlarged sectional view of the main part of FIG. 3, and FIG. 5 is a diagram showing another embodiment of the present invention. be. 1... Semiconductor substrate, 2... Cathode electrode plate, 3
...Anode electrode plate, 4...Metal foil.

Claims (1)

【特許請求の範囲】 1 一対の主表面間に所定のpn接合を有する半
導体基体と、半導体基体の一方の主表面上に形成
された複数の第1の電極膜と、半導体基体の一方
の主表面上に第1の電極膜と絶縁されかつ第1の
電極膜の頂面よりも低く形成された第2の電極膜
と、複数の上記第1の電極膜上に跨がつて配置さ
れ上記第1の電極膜より高硬度を有し、上記半導
体基体と略等しい熱膨張係数を有する100μm以
下の厚さを持つ金属箔と、上記金属箔上に載置さ
れ金属箔を介して上記第1の電極膜に加圧接触さ
れる電極板とを有し、加圧下において、上記第1
の電極膜は加圧力で変形し、厚さを減じて見掛け
上の硬さが上記金属箔の硬さ以上となり、上記金
属箔は上記第1の電極膜の頂面端部外側で該加圧
力の方向と鋭角をもつて交わるように僅かに湾曲
していることを特徴とする半導体装置。 2 特許請求の範囲第1項において、上記金属箔
はFe−Ni−Co、又はFe−Ni合金からなることを
特徴とする半導体装置。
[Claims] 1. A semiconductor substrate having a predetermined pn junction between a pair of main surfaces, a plurality of first electrode films formed on one main surface of the semiconductor substrate, and one main surface of the semiconductor substrate. a second electrode film formed on the surface to be insulated from the first electrode film and lower than the top surface of the first electrode film; and a second electrode film disposed astride the plurality of first electrode films. A metal foil having a thickness of 100 μm or less, which has higher hardness than the first electrode film and has a coefficient of thermal expansion substantially equal to that of the semiconductor substrate; and an electrode plate that is brought into pressure contact with the electrode film, and under pressure, the first
The electrode film is deformed by the applied pressure, its thickness is reduced, and the apparent hardness becomes greater than the hardness of the metal foil, and the metal foil is deformed by the applied pressure at the outside of the top end of the first electrode film. A semiconductor device characterized by being slightly curved so as to intersect at an acute angle with the direction of. 2. The semiconductor device according to claim 1, wherein the metal foil is made of Fe-Ni-Co or Fe-Ni alloy.
JP15677679A 1979-12-05 1979-12-05 Semiconductor device Granted JPS5680140A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15677679A JPS5680140A (en) 1979-12-05 1979-12-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15677679A JPS5680140A (en) 1979-12-05 1979-12-05 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5680140A JPS5680140A (en) 1981-07-01
JPS6329408B2 true JPS6329408B2 (en) 1988-06-14

Family

ID=15635057

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15677679A Granted JPS5680140A (en) 1979-12-05 1979-12-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5680140A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6459824A (en) * 1987-08-31 1989-03-07 Hitachi Ltd Pressure-contact type semiconductor device

Also Published As

Publication number Publication date
JPS5680140A (en) 1981-07-01

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