JPH08222732A - Insulated-gate semiconductor device - Google Patents

Abstract

PURPOSE: To eliminate the possibility that the characteristics of a semiconductor element are deteriorated and the element is broken even if a local pressure due to an internal buffer is generated. CONSTITUTION: In an insulated-gate semiconductor device assembled by pressing a semiconductor base body 500, which has insulated gate structures formed of an oxide film 20, a polycrystalline silicon layer 21 and an oxide film 22 on the main surface on one side of its main surfaces, via an internal buffer 220, a region having no insulated gate structure is left at a part, which comes into contact with the main surface, of the buffer 200 in the peripheral part of the buffer 200 and a pressing force relaxation region D is made to form of this region. A local pressure due to a bent, which is generated at the end part of the buffer 200 by a difference between the thermal expansion coefficients of the end part, is relaxed by the deformation of an electrode 31 at the region D and the amount of the deformation is limited by an oxide film 100.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate type semiconductor device in which electrical connection to a semiconductor substrate is obtained by pressure contact of electrodes, and more particularly to an insulated gate type semiconductor device suitable for high power. .

[0002]

2. Description of the Related Art A high-voltage power semiconductor device having an insulated gate structure, such as an IGBT (insulated gate bipolar transistor) or an MCT (insulated gate thyristor),
Compared with GTO (gate turn-off thyristor) which has been widely used as a self-extinguishing type semiconductor device for electric power in the past, it has excellent characteristics such as a gate type gate drive system and an operating frequency that is nearly one digit higher. Therefore, the range of application is rapidly expanding to the field to which the high breakdown voltage GTO was applied.

By the way, the insulated gate type semiconductor device, which is currently the mainstream, adopts a module structure in which a semiconductor substrate (semiconductor element) is connected to an external electrode by using wire bonding or solder. There is a problem that reliability is lowered due to breakage of wire bonding due to fatigue, cracking of solder, and the like.

Therefore, instead of such wire bonding or soldering connection, Japanese Patent Laid-Open No. 218643/1993
JP-A-4-290272 and JP-A-4-32247.
As can be seen in each publication of No. 1, a pressure contact type structure has been studied in which a low resistance connection is obtained by pressure contact of an external electrode with a semiconductor element. By adopting this pressure contact type structure, In addition to high reliability, it is possible to reduce thermal resistance due to heat dissipation from both sides of the element.

As described above, the pressure contact type is an effective means for increasing the reliability of the semiconductor device and reducing the thermal resistance, but the external electrode and the semiconductor element made of a material having low electric resistance and thermal resistance such as copper are used. In order to make pressure contact, a strain absorption layer that absorbs strain due to the difference in thermal expansion coefficient between both materials is required,
Therefore, it is customary to provide an internal buffer made of a material having a thermal expansion coefficient relatively close to that of the semiconductor element between the external electrode and the semiconductor element.

FIG. 6 shows an example of a pattern on the emitter side of a conventional large capacity IGBT semiconductor device 500 in which a plurality of active device regions 301 having an insulated gate structure are arranged on a rectangular semiconductor chip (semiconductor substrate). , A gate pad 300 for extracting a gate electrode is formed in the central portion, and a plurality of active element regions 301 having an insulated gate structure are arranged around the gate pad 300, and the gate is formed so as to surround these active element regions 301. Wiring 302 is formed,
Further, a termination region 600 that defines the breakdown voltage of the semiconductor device is formed outside the active element regions 301 so as to surround them.

Next, FIG. 7 shows the semiconductor device 5 shown in FIG.
00 is pressed by an external post electrode 100. In the example of FIG. 7, the coefficient of thermal expansion of silicon (2.9 × 10
^The internal buffer 20 is a member made of molybdenum (Mo) whose coefficient of thermal expansion is relatively close to that of ( ⁶ K) (4.9 × 10 ⁶ K).
0 is arranged, and the surface thereof is further pressed by a post electrode 1000 of copper (Cu). As the material of the internal buffer 200, tungsten (W) can be used instead of molybdenum.

[0008]

The above-mentioned prior art does not take into consideration the local stress concentration generated by the temperature change in the semiconductor device of the pressure contact type structure, and the strong stress appears in the insulated gate structure portion, resulting in the characteristics. There is a problem that there is a possibility that the device may be deteriorated or the device may be broken.

As described with reference to FIG. 7, this is because, in the pressure contact type semiconductor device, materials having different thermal expansion coefficients are laminated and pressed, so that when the temperature rises, the This is because stress is applied to the internal buffer 200 sandwiched between materials having different expansion coefficients, and its shape is deformed.

FIG. 8 shows, by arrows, the state of expansion that appears in each member when the temperature rises. One surface of the internal buffer 200 is made of copper (17.1) having a coefficient of thermal expansion larger than that of molybdenum. Since it is in contact with the post electrode 1000 made of × 10 to ⁶ K), a force pulling outward from the center is generated on the surface of the internal buffer 200 made of molybdenum.

On the other hand, the other surface is in contact with the semiconductor element 500 made of silicon having a coefficient of thermal expansion smaller than that of molybdenum, so that the surface of molybdenum exerts a force to prevent the expansion. Due to the difference in the forces applied to both surfaces, the internal buffer 200 tries to deform into a dish shape, and the end portion of the internal buffer 200 locally strongly presses the semiconductor element 500 at the portion indicated by a circle A. It becomes.

This will be described more specifically with reference to FIG. FIG. 9 shows a case where the semiconductor element 500 is an IGBT, and FIG. 9B is a cross-sectional view of the peripheral portion of the semiconductor element 500, in which the end of the internal buffer 200 is in contact. (a) shows the distribution of the pressing force that appears on the surface of the semiconductor element 500 when each member thermally expands due to the temperature rise. In the semiconductor element 500, the high-concentration p layer 11 is formed on one surface (lower surface in the figure) of the low-concentration n-type base layer 10, and the lower surface on which the high-concentration p layer 11 is exposed is the collector surface. And here, the first main electrode 30
Are formed.

A p-type base layer 12 is formed on the other surface (also the upper surface) of the low-concentration n-type base layer 10, and inside the p-type base layer 12, an n-type emitter layer is formed. Thirteen
Are formed. The upper surface on which the p-type base layer 12 is exposed serves as an emitter surface, and the emitter layer 13 extends from the emitter layer 13 to the next emitter via the gate insulating film 20. A gate electrode 21 made of, for example, polycrystalline silicon is formed up to the layer 13, a second oxide film 22 is formed on the surface thereof to form an insulated gate structure, and the n-type emitter layer 13 is further formed on the surface thereof.
The second main electrode 31 is formed so as to be in contact with.

By the way, in such an element, the insulated gate structure portion is fragile in strength. Then
As described above, the pressure contact type semiconductor device has a structure in which the second main electrode 31 is pressed. Therefore, the second main electrode 31
When the electrode 31 formed on the surface of the insulated gate structure, that is, the surface of the second oxide film 22 is locally pressed as shown by an arrow C, a part of the The stress may increase and the characteristics of the semiconductor element may be deteriorated. For this reason, it is necessary to avoid local pressure on the main electrode formed on the emitter-side surface as much as possible.

By the way, in the pressure contact type structure, as already described with reference to FIG. 8, the internal buffer 200 is deformed due to the temperature rise, and the portion indicated by a circle B in the figure is strongly pressed. As a result, as shown in FIG. 9A, the applied pressure becomes large at the outer peripheral portion of the chip forming the semiconductor element 500, that is, the portion where the end portion of the internal buffer 200 is in contact, and strong stress is applied to the insulated gate structure portion. Take a
There is a possibility that the characteristics may be deteriorated or the element may be destroyed.

An object of the present invention is to provide an insulated gate semiconductor device in which the characteristics of the semiconductor element are not deteriorated or the semiconductor element is destroyed even if local pressure is applied by the internal buffer. There is.

[0017]

SUMMARY OF THE INVENTION In order to achieve the above object, in an insulated gate type semiconductor device in which a semiconductor substrate having an insulated gate structure on one main surface is assembled by pressing through an internal buffer, the periphery of the internal buffer is provided. Part, a region not having the insulated gate structure is left in a portion in contact with the main surface, and this region forms a pressing force relaxation region.

[0018]

[Function] The pressure relieving region concentrates the local pressure exerted by the deformation of the end portion of the internal buffer to limit the amount of deformation, thereby preventing stress from being applied to the insulated gate structure portion. Work to do.

As a result, even if the end portion of the internal buffer is deformed, the stress caused by the deformation is eliminated and the characteristic deterioration can be prevented.

[0020]

The insulated gate semiconductor device according to the present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG.
1 is a first embodiment in which the present invention is applied to an IGBT, and particularly shows an insulated gate structure in the peripheral portion of an IGBT semiconductor element (semiconductor substrate) 500.

In the figure, an IGBT semiconductor device 500 is shown.
Has a high-concentration p layer 11 formed on one surface (lower surface in the figure) of the low-concentration n-type base layer 10, and the lower surface on which the high-concentration p layer 11 is exposed serves as a collector surface. A first main electrode 30 made of aluminum is formed on the.

A p-type base layer 12 is formed on the other surface (also the upper surface) of the low-concentration n-type base layer 10, and an n-type emitter layer 12 is formed inside the p-type base layer 12. Thirteen
Are formed.

The upper surface on which the p-type base layer 12 is exposed serves as an emitter surface, and the emitter layer 13 extends from the emitter layer 13 to the p-type base layer 12 and the n-type base layer 10 via the gate insulating film 20. A gate electrode 21 made of, for example, polycrystalline silicon is formed up to the next emitter layer 13, and a second oxide film 22 is formed on the surface thereof to form an insulated gate structure. Further, on the surface thereof, an n-type emitter layer 13 is formed. A second main electrode 31 made of aluminum is formed so as to be in contact therewith. Although the above-mentioned configuration is the same as that of the conventional example shown in FIG. 9, the structure of the peripheral portion D of the semiconductor element 500 in this example is different from that of the conventional example. That is, in this embodiment, in its peripheral portion D, as shown in the figure, the portion exposed on the surface of the p-type base layer 12 that extends laterally outward is provided with polycrystalline silicon serving as a gate electrode therein. The oxide film 100 which is not formed is formed so that the pressing force relaxing region is formed in the peripheral portion D, which is different from the conventional example in this respect.

Next, the function of the pressing force alleviating region according to this embodiment will be described. In the present invention, in order to mitigate the local concentration of pressure on the insulated gate structure, the portion locally pressurized by the internal buffer is moved to the region where the insulated gate structure is not formed. As a feature, the degree of the pressure concentration relaxing function obtained at this time largely varies depending on the structure of the pressure relaxing region.
Therefore, first, in the embodiment of FIG. 1, the applied pressure relaxation region is formed by two layers of the main electrode 31 which is an elastic material and the oxide film 100 which is an inelastic material. Here, the elastic substance is a substance that undergoes elastic deformation in response to a stress up to a certain degree and is plastically deformed by a stress higher than that, and corresponds to a metal such as aluminum and a non-elastic substance. The term "material" refers to a substance that causes almost no elastic deformation under a certain level of stress, and changes to destruction under a higher level of stress, and corresponds to certain oxides and ceramics. .

FIG. 2 shows the thickness d in the pressing force relaxing region D when the pressing force relaxing region is exerted by the deformation of the internal buffer 200 in the embodiment of FIG. 1, that is, p in the peripheral portion D. From the surface of the type semiconductor layer 12 to the main electrode 3
1 shows the relationship between the amount of change in the thickness up to the surface of No. 1 and the pressure (stress) applied to the insulated gate structure arranged around the pressure relaxation region.

In the applied pressure relaxation region D, when the internal buffer 200 is deformed and pressure is applied, first, the main electrode 3 is pressed.
1 is elastically deformed. Although the amount of elastic deformation varies depending on the applied pressure, when the elastic deformation is repeated, the surface of the main electrode 31 made of aluminum is gradually crushed, and as a result, the thickness D of the pressure relaxation region D gradually decreases. .

Therefore, when the aluminum main electrode 31 in this portion is gradually crushed and deformed due to the concentration of the pressing force, if the oxide film 100 is not provided in this pressing force relaxation region D, the main electrode 31 remains as it is. When it is crushed and becomes thinner than the thickness of the insulated gate structure, the concentrated portion of the pressing force due to the deformation of the internal buffer 200 is also transferred to the insulated gate structure arranged in the periphery (inner side) of the pressing force relaxation region D, As shown in FIG. 2, stress concentrates also on the insulated gate structure adjacent to the pressure relaxation region, which deteriorates the characteristics of the insulated gate structure.

However, in this embodiment, since the oxide film 100 made of an inelastic material is formed in the lower layer of the main electrode 31 made of aluminum which is an elastic material, the pressure relaxation region D is formed.
The thickness d is not less than the thickness of the oxide film 100.

As a result, according to this embodiment, even if the temperature cycle is repeated, the concentrated area of the applied pressure does not move from the pressure relaxation area D to the periphery, and the stress is concentrated on the insulated gate structure, so that the characteristics can be improved. It is possible to surely prevent the risk of deterioration.

That is, according to this embodiment, the gate electrode 21 and the low-concentration n-type base layer 10 are not short-circuited, the threshold voltage is not changed, and the characteristics are not deteriorated, and the temperature cycle is repeated. It is possible to obtain a pressure contact type semiconductor device having no change in characteristics.

Further, in this embodiment, even if the oxide film 100 is destroyed by the pressure and a minute defect is generated on the silicon surface, the p-type which is relatively deeply diffused in the pressure relaxation region D. Since the base layer 12 is formed, the blocking voltage or the like is not adversely affected, and therefore the characteristics are not likely to deteriorate even in this case.

Next, another embodiment of the present invention will be described. FIG. 3 is a second embodiment of the present invention. In this embodiment, the pressure relaxation oxide film 100 in the embodiment of FIG. 1 is formed into a plurality of films, in this case, three films 101 and 102, and This structure is characterized by being formed by 103, and the other structure is the same as that of the first embodiment. Therefore, also in this embodiment, the concentrated area of the pressing force does not move from the pressure relaxation area D to the periphery. It is possible to surely prevent the risk of stress concentration on the insulated gate structure and deterioration of the characteristics.

Moreover, in this embodiment, the membrane 101 is made of p
The oxide film is formed at the same time when the gate oxide film 20 is formed on the surface of the mold base body layer 12, the film 102 is formed of a polycrystalline silicon layer formed at the same time as the gate electrode 21, and the film 103 is a protective oxide film. 22 and an oxide film formed at the same time.

That is, in this embodiment, the gate oxide film 20 and the gate electrode 2 forming the insulated gate structure portion are formed.
1, the protective oxide film 22, the oxide film 101 forming the pressing force relaxation region D, the polycrystalline silicon layer 102, and the protective oxide film 103 are formed of the same material at the same time.

Therefore, since the height and hardness of the gate insulating structure portions A, B, C and the pressure relaxation region C from the semiconductor surface to the surface of the main electrode 31 are substantially equal, the internal buffer 200 having a flat surface. Thus, by simply pressing the surface of the main electrode 31, it is possible to uniformly press the gate insulating structure portion and the pressurizing force relaxing region.

Further, since the gate insulating structure portion and the pressure relieving region can be manufactured at the same time, the number of manufacturing steps can be used as it is without increasing the number of conventional manufacturing steps, thus increasing the cost. Can be suppressed.

Next, FIG. 4 and FIG. 5 show the present invention with a large capacity I.
This is an example when applied to a GBT. First, in Figure 4,
2 shows an emitter side pattern of a large capacity IGBT semiconductor device 500 according to this embodiment, in which a gate pad 300 for taking out a gate electrode is formed in a central portion, and a plurality of active device regions 301 having an insulated gate structure are formed in the periphery thereof. It is arranged.

Next, a gate wiring 302 is formed so as to surround these active element regions 301, and a pressure relieving region 400 is formed so as to surround the entire active element regions 301. A termination region 600 that determines the breakdown voltage of the semiconductor device is formed outside the pressure relaxation region 400. FIG. 5 shows FIG.
Of the cross section taken along line AA of
Is an oxide film for insulating the gate wiring, 601 is a p-type semiconductor layer forming a termination region, 602 is an oxide film, and 604 is an electrode in the termination region.

The feature of the embodiment shown in FIGS. 4 and 5 lies in that the pressurizing area 400 is arranged around the active area so as to surround the gate wiring 302. That is, in this embodiment, the local pressure applied by the end portion of the internal buffer 200 is relaxed by the pressure relief area 400, which is similar to the previously described embodiment of FIG. In this embodiment, the electrode to be provided on the surface of the pressure relaxation oxide film 100 is formed separately from the main electrode 31, and this is used as the third electrode 33. Then, the electrode 33 is brought into contact with the p-type base layer 12p, and the internal buffer 200 is provided via the third electrode 33.
And the p-type base layer 12 are in contact with each other with low resistance.

Therefore, according to this embodiment, when the device is switched off, the n-type base layer 10 below the pressure relaxation oxide film 100 and the termination region 600 is formed.
Since the carriers remaining therein can be quickly discharged to the internal buffer 200 via the third electrode 33, the depletion layer can be rapidly expanded to the termination region 600, and a specified design breakdown voltage can be easily obtained. be able to.

Further, since the discharged carriers do not flow in the vicinity of the n-type emitter layer 13, the latch-up phenomenon of the semiconductor element can be prevented, so that the maximum allowable collector current can be increased and the capacity can be further increased. You can

In the embodiments shown in FIGS. 4 and 5, the pressure relaxation layer is formed of the oxide film 100.
As in the above embodiment, a pressure relaxation layer composed of a plurality of laminated films may be used, and the same effect can be obtained.

In the above embodiments, the case where the present invention is applied to the insulated gate bipolar transistor (IGBT) has been described. However, the present invention is not limited to the IGBT, and the insulated gate type structure is formed on the surface of the semiconductor element. Needless to say, the pressure contact type semiconductor device can be applied to any semiconductor device, for example, a power MOSFET,
Similar effects can be obtained even when applied to a semiconductor device such as an insulated gate thyristor (MCT).

[0044]

According to the present invention, in the pressure type semiconductor device, even if the local pressure is applied by the internal buffer, the characteristics of the semiconductor element may be deteriorated or the semiconductor element may be broken. Since it can be surely eliminated, the thermal resistance and the electrical resistance can be suppressed sufficiently small by increasing the applied pressure, and the improvement of the cooling effect and the reduction of the loss can be easily obtained.

Further, as a result, it is possible to easily provide a pressure type insulated gate semiconductor device with greatly improved reliability.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of an insulated gate semiconductor device according to the present invention.

FIG. 2 is a characteristic diagram illustrating a pressure relaxation characteristic according to an embodiment of the present invention.

FIG. 3 is a sectional view showing a second embodiment of the insulated gate semiconductor device according to the present invention.

FIG. 4 is a plan view showing a third embodiment of the insulated gate semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view showing a third embodiment of an insulated gate semiconductor device according to the present invention.

FIG. 6 is a plan view showing a conventional example of an insulated gate semiconductor device.

FIG. 7 is an explanatory diagram showing a state in which an insulated gate semiconductor element is pressed by an external electrode.

FIG. 8 is an explanatory view showing stress when an insulated gate semiconductor element is pressed by an external electrode.

FIG. 9 is a cross-sectional view showing a conventional example of an insulated gate semiconductor device.

[Explanation of symbols]

 10 Low Concentration n-type Base Layer 11 High Concentration p Layer 12 ... P-type Base Layer 13 n-type Emitter Layer 20 Gate Oxide Film 21 Gate Electrode 22 Oxide Film 30 First Main Electrode 31 Second Main Electrode 33 Third Main electrodes 100, 101, 103 Oxide film 102 Polycrystalline silicon layer (polysilicon) 200 Internal buffer 300 Gate pad 301 Active device region 302 Gate wiring 400 Pressure relaxation region 500 Semiconductor device 600 Termination region 1000 Post electrode

Claims (4)

[Claims] 1. An insulated gate semiconductor device in which a semiconductor substrate having an insulated gate structure on one main surface is assembled by pressing through an internal buffer, and in the peripheral portion of the internal buffer, the main surface is in contact with the main surface. An insulated gate semiconductor device, characterized in that a region not having the above-mentioned insulated gate structure is left in a part thereof, and a pressing force relaxation region is formed by this region. 2. The invention according to claim 1, wherein the pressing force relaxing region is composed of at least two layers, a pressing force relaxing layer made of an elastic material and a pressing force relaxing layer made of an inelastic material. Insulated gate type semiconductor device. 3. The insulated gate type according to claim 1 or 2, wherein the pressing force relaxation region layer is formed simultaneously and at the same time with the formation of the insulated gate structure. Semiconductor device. 4. The insulated gate type according to claim 2, wherein the pressing force relaxing layer made of the elastic material is composed of an electrode independent of a main electrode in contact with the insulated gate structure. Semiconductor device.