JP2756826B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2756826B2 JP2756826B2 JP1129533A JP12953389A JP2756826B2 JP 2756826 B2 JP2756826 B2 JP 2756826B2 JP 1129533 A JP1129533 A JP 1129533A JP 12953389 A JP12953389 A JP 12953389A JP 2756826 B2 JP2756826 B2 JP 2756826B2
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- Prior art keywords
- electrode
- semiconductor device
- layer
- bonding
- bonding pad
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48455—Details of wedge bonds
- H01L2224/48456—Shape
- H01L2224/48458—Shape of the interface with the bonding area
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
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- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Engineering & Computer Science (AREA)
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- Electrodes Of Semiconductors (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の電極構造に係り、特にボンディ
ングパッドを備えた半導体装置の電極構造に関する。Description: TECHNICAL FIELD The present invention relates to an electrode structure of a semiconductor device, and more particularly to an electrode structure of a semiconductor device having a bonding pad.
半導体装置（半導体ペレット）の電極としては、種々
改良された構造のものが知られているが、たとえば熱膨
張差、加工面あるいは経済面等の観点からAlが用いられ
ることが一般的である。As an electrode of a semiconductor device (semiconductor pellet), those having variously improved structures are known. For example, Al is generally used from the viewpoint of a difference in thermal expansion, a processing surface, an economic surface, and the like.
そして、このような半導体装置は、機械的外力から防
止するため、リード状電極を備えた外囲器内へ収納され
るのが通常である。Such a semiconductor device is usually housed in an envelope provided with a lead electrode in order to prevent the semiconductor device from being subjected to a mechanical external force.
したがって、前記リード状電極と半導体装置の電極と
をたとえばワイヤを介して電気的に接続するため、前記
半導体装置の主表面には前記電極を延在させて形成され
たボンディングパッドを備えている。Therefore, in order to electrically connect the lead-shaped electrode and the electrode of the semiconductor device via, for example, a wire, a bonding pad formed by extending the electrode is provided on a main surface of the semiconductor device.
しかし、このような半導体装置は、電極を形成した後
に、アニールと称される熱処理を行なっている。それま
でのスパッタリング、蒸着等の表面処理によってダメー
ジが生ずるので、そのダメージを消失させるためであ
る。However, such a semiconductor device performs a heat treatment called annealing after forming the electrodes. This is because damage is caused by surface treatment such as sputtering and vapor deposition, and the damage is eliminated.
このため、この熱処理時において、電極とオーミック
接触する半導体基板面のシリコンが該電極を構成するAl
内に拡散してしまう現象が生じ、特に前記電極とオーミ
ック接触する半導体層と異なる導電型の半導体との接合
面が浅い場合において該接合面が破壊するということが
ある。Therefore, during this heat treatment, the silicon on the semiconductor substrate surface in ohmic contact with the electrode is
In particular, when the junction surface between the semiconductor layer in ohmic contact with the electrode and a semiconductor of a different conductivity type is shallow, the junction surface may be broken.
したがって、近年にあっては、電極を、特にSiを含ま
せたAlで構成し、これにより半導体基板内のSiを電極側
へ拡散するのをできるだけ阻止せんとした技術が知られ
るようになった。Therefore, in recent years, a technique has been known in which an electrode is made of Al, particularly containing Si, and thereby prevents diffusion of Si in the semiconductor substrate to the electrode side as much as possible. .
しかし、通常にあって電極とこの電極と接続されるボ
ンディングパッドとは同工程で形成されるため、前記ボ
ンディングパッドにおいてもSiを含ませたAlで構成され
たものとなる。However, since the electrodes and the bonding pads connected to the electrodes are usually formed in the same process, the bonding pads are also made of Al containing Si.
この場合、超音波ボンディング法を用いてボンディン
グパッドにワイヤをボンディングする際、該ボンディン
グパッドにSiを含んでいるが故に、そのボンディングが
充分でなくなるという問題点を有する。したがってボン
ディングのパワーを向上させてボンディングを行なって
いたものであるが、半導体装置に大きなストレスがかか
り、これがために半導体装置を破壊するということが往
々にしてあった。In this case, when bonding the wire to the bonding pad using the ultrasonic bonding method, there is a problem that the bonding is not sufficient because the bonding pad contains Si. Therefore, although the bonding is performed by improving the bonding power, a large stress is applied to the semiconductor device, which often destroys the semiconductor device.
本発明は、このような事情に鑑みてなされたものであ
り、Siの電極への拡散を防止できるとともにボンディン
グも障害なく行なうことのできる電極構造を有する半導
体装置及びその製造方法を提供することを目的とするも
のである。The present invention has been made in view of such circumstances, and it is an object of the present invention to provide a semiconductor device having an electrode structure capable of preventing diffusion of Si to an electrode and performing bonding without any trouble, and a method of manufacturing the same. It is the purpose.
このような目的を達成するために本発明は、半導体基
板の主表面に絶縁膜が形成され、該絶縁膜に形成された
透孔により露呈された前記半導体基板面に電極が形成さ
れ、かつ前記電極と電気的に接続されたボンディングパ
ッドを有する半導体装置において、前記電極は少なくと
も前記半導体基板面とオーミック接触する側にてSiAl金
属で形成され、前記ボンディングパッドは少なくともそ
のボンディングされる側にてAlで形成されていることを
基本的な構成とし、前記電極およびボンディングパッド
は半導体基板側からAlSi,Alを順次積層させた二層構造
でかつAlSi層およびAl層は同一パターンとする。In order to achieve such an object, the present invention provides an insulating film formed on a main surface of a semiconductor substrate, an electrode formed on the surface of the semiconductor substrate exposed by a through hole formed in the insulating film, and In a semiconductor device having a bonding pad electrically connected to an electrode, the electrode is formed of SiAl metal on at least a side in ohmic contact with the semiconductor substrate surface, and the bonding pad is formed on at least a side to be bonded of Al. The electrode and the bonding pad have a two-layer structure in which AlSi and Al are sequentially laminated from the semiconductor substrate side, and the AlSi layer and the Al layer have the same pattern.
また、蒸着装置内にAlSi,Alの２つのソースを配置
し、時間的に切り換えてAlSi層、Al層を蒸着により形成
する半導体装置の製造方法とする。Further, a method for manufacturing a semiconductor device in which two sources of AlSi and Al are arranged in a vapor deposition apparatus and an AlSi layer and an Al layer are formed by vapor deposition while changing over time.
このように構成された半導体装置の電極構造は、その
電極が少なくとも半導体基板面とオーミック接触する側
にてSiAl金属で形成されている。このため、電極形成後
にアニールと称される熱処理を施した場合においても半
導体基板内のSiが電極側へ拡散するのを阻止することが
できるようになる。The electrode structure of the semiconductor device thus configured is made of SiAl metal at least on the side where the electrode comes into ohmic contact with the semiconductor substrate surface. For this reason, even when a heat treatment called annealing is performed after the electrode is formed, it is possible to prevent Si in the semiconductor substrate from diffusing toward the electrode.
また前記電極と接続されるボンディングパッドは少な
くともそのボンディングされる面にてAlで形成されてい
る。このため、ワイヤを超音波ボンディング法によりボ
ンディングする場合、そのパワーを大きくすることなく
行なうことができ、半導体素子に大きなストレスをかけ
ることがなくなる。したがってボンディングを何ら支障
なく行なうことができる。A bonding pad connected to the electrode is formed of Al at least on a surface to be bonded. For this reason, when bonding the wires by the ultrasonic bonding method, the bonding can be performed without increasing the power, and a large stress is not applied to the semiconductor element. Therefore, bonding can be performed without any trouble.
第１図は本発明による半導体装置の電極構造の一実施
例を示す構成図である。同図において、半導体基板１が
あり、この半導体基板１の表面にはエピタキシャル成長
層６が形成されている。そしてこのエピタキシャル成長
層６の表面には複数個のMOSトランジスタ20が並設され
ている。この各MOSトランジスタ20の構成は第２図に示
すようになっている。すなわちエピタキシャル成長層６
の表面にはこのエピタキシャル成長層６と異なる導電型
の拡散層９が形成されている。この拡散層９はチャンネ
ル領域を形成するための半導体層となるものである。さ
らにこの拡散層９の表面にはこの拡散層９と異なる導電
型の拡散層10が前記拡散層９の周辺部に沿って環状に形
成されている。この拡散層10はソース層を構成するもの
である。FIG. 1 is a configuration diagram showing one embodiment of an electrode structure of a semiconductor device according to the present invention. In FIG. 1, there is a semiconductor substrate 1, and an epitaxial growth layer 6 is formed on the surface of the semiconductor substrate 1. A plurality of MOS transistors 20 are juxtaposed on the surface of the epitaxial growth layer 6. The configuration of each MOS transistor 20 is as shown in FIG. That is, the epitaxial growth layer 6
A diffusion layer 9 of a conductivity type different from that of the epitaxial growth layer 6 is formed on the surface of the substrate. This diffusion layer 9 is to be a semiconductor layer for forming a channel region. Further, on the surface of the diffusion layer 9, a diffusion layer 10 of a conductivity type different from that of the diffusion layer 9 is formed in an annular shape along the periphery of the diffusion layer 9. This diffusion layer 10 constitutes a source layer.
そして、このような環状をなす前記拡散層10の間にあ
る前記拡散層９およびこの拡散層９の周辺の前記拡散層
10の一部を露呈させた状態にて他の領域にはゲート酸化
膜を構成する酸化膜７が形成されている。さらにこの酸
化膜７を介して前記拡散層10とエピタキシャル成長層６
との間の前記拡散層９の上面にはゲート電極８が形成さ
れこのゲート電極８は周辺に延在されたものとなってい
る。The diffusion layer 9 between the annular diffusion layers 10 and the diffusion layer around the diffusion layer 9.
An oxide film 7 constituting a gate oxide film is formed in another region with a portion of 10 exposed. Further, the diffusion layer 10 and the epitaxial growth layer 6 are interposed via the oxide film 7.
A gate electrode 8 is formed on the upper surface of the diffusion layer 9 between the gate electrode 8 and the gate electrode 8 extending to the periphery.
前記ゲート酸化膜を構成する酸化膜７の上面には前記
ゲート電極を被覆した状態で比較的層厚の大きな絶縁層
11が形成されている。この絶縁層11および前記酸化膜７
によって露呈されている前記拡散層９およびこの拡散層
９の周辺の前記拡散層10の一部にはAlSi電極４が形成さ
れている。このAlSi電極４はたとえばその表面が前記絶
縁膜11の表面と面一になって形成されている。On the upper surface of the oxide film 7 constituting the gate oxide film, an insulating layer having a relatively large thickness while covering the gate electrode is provided.
11 are formed. The insulating layer 11 and the oxide film 7
An AlSi electrode 4 is formed on the diffusion layer 9 exposed by the above and a part of the diffusion layer 10 around the diffusion layer 9. The AlSi electrode 4 is formed, for example, so that its surface is flush with the surface of the insulating film 11.
ここで、Alに対するSiの含有量の程度は、第３図に示
すようになっている。同図は横軸で示した割合の電極を
形成した後、縦軸に示す温度でアニールしたときの、前
記電極の状態を示すものである。電極が固体から固溶体
に変化する場合には半導体基板内のSiが電極内へ拡散す
ることから、この範囲を避けて、アニールの温度の関係
からSiの含有量を定めなければならない。Here, the degree of the content of Si with respect to Al is as shown in FIG. This figure shows the state of the electrodes when the electrodes are formed at the ratio shown on the horizontal axis and then annealed at the temperature shown on the vertical axis. When the electrode changes from a solid to a solid solution, Si in the semiconductor substrate diffuses into the electrode. Therefore, it is necessary to determine the Si content from the relationship of the annealing temperature while avoiding this range.
そして、前記AlSi電極４および絶縁層11の表面にはAl
電極５が形成されている。The surface of the AlSi electrode 4 and the insulating layer 11 has Al
An electrode 5 is formed.
このような構成から前記Al電極５およびこのAl電極５
と電気的に接続されるAlSi電極４はソース電極を構成す
るようになる。また前記エピタキシャル成長層６はドレ
イン層となり、これに接続されるドレイン電極は図示し
ない部分にて形成されている。なお、ゲート電極８への
電圧印加によって拡散層10とエピタキシャル成長層６と
の間の拡散層９の酸化膜（ゲート酸化膜７）界面にはチ
ャンネル層が形成される。With such a configuration, the Al electrode 5 and the Al electrode 5
The AlSi electrode 4 electrically connected to the source electrode constitutes a source electrode. The epitaxial growth layer 6 becomes a drain layer, and a drain electrode connected to the drain layer is formed in a portion not shown. Note that a channel layer is formed at the oxide film (gate oxide film 7) interface of the diffusion layer 9 between the diffusion layer 10 and the epitaxial growth layer 6 by applying a voltage to the gate electrode 8.
そして前記Al電極５は、第１図に示すように、他のMO
Sトランジスタ20のソース電極と共通に形成されたもの
であり、ボンディングパッドを兼ねたものとして構成さ
れている。さらに、このボンディングパッド面には超音
波ボンディイング法によってボンディングされたボンデ
ィングワイヤ12が接続して固着されている。The Al electrode 5 is, as shown in FIG.
It is formed in common with the source electrode of the S transistor 20, and is configured to also serve as a bonding pad. Further, a bonding wire 12 bonded by an ultrasonic bonding method is connected and fixed to the bonding pad surface.
このように構成した半導体装置の電極構造によれば、
拡散層9,10にオーミック接触するAlSi電極４はSiが含有
されたものであることから、アニール時に拡散層9,10側
から前記AlSi電極４へのSiの拡散を阻止することができ
る。また、ボンディングパッドとなるAl電極５はAlそれ
自体の金属からなるため、ボンディングパワーを大きく
することなくボンディングでき、半導体装置の破壊を防
止することができるようになる。According to the electrode structure of the semiconductor device configured as described above,
Since the AlSi electrode 4 in ohmic contact with the diffusion layers 9 and 10 contains Si, it is possible to prevent the diffusion of Si from the diffusion layers 9 and 10 side to the AlSi electrode 4 during annealing. Further, since the Al electrode 5 serving as the bonding pad is made of Al itself, the bonding can be performed without increasing the bonding power, and the semiconductor device can be prevented from being broken.
第４図は、Al超音波ボンディング時のパワーが大きい
と、絶縁膜（半導体装置）が破壊され、逆にボンディン
グパワーが小さいとボンディング不良が生じることを、
従来と本実施例の場合とを比較して示している。このこ
とから明らかなように、本実施例によれば、従来構造に
比べ、Al超音波ボンディング時のパワーを20％程度小さ
くでき、また、Al電極表面が平坦化されているためボン
ディングストレスに依る絶縁破壊も防止できる。FIG. 4 shows that if the power at the time of Al ultrasonic bonding is high, the insulating film (semiconductor device) is destroyed, and if the bonding power is low, bonding failure occurs.
This shows a comparison between the conventional case and the case of the present embodiment. As is clear from this, according to the present embodiment, the power at the time of Al ultrasonic bonding can be reduced by about 20% as compared with the conventional structure, and the Al electrode surface is flattened, which depends on the bonding stress. Dielectric breakdown can also be prevented.
上述した実施例では、半導体装置に組み込まれる半導
体素子上に重畳させて形成したボンディングパッドにつ
いて説明したものであるが、これに限らず前記半導体素
子とは離間されてたとえば半導体装置の周辺部に位置づ
けたボンディングパッドであってもよいことはもちろん
である。また前記半導体素子としてMOSトランジスタに
限定されることなく他のバイポーラトランジスタのよう
な素子であってもよい。In the above-described embodiment, the bonding pad formed so as to be superimposed on the semiconductor element incorporated in the semiconductor device has been described. However, the present invention is not limited to this. Needless to say, a bonding pad may be used. The semiconductor element is not limited to a MOS transistor but may be another element such as a bipolar transistor.
この場合、第５図に示すように、AlSi電極４はその表
面が絶縁膜３の表面と面一になる必要はなく、前記絶縁
膜３より浅く形成されたものであってもよい。In this case, as shown in FIG. 5, the surface of the AlSi electrode 4 does not need to be flush with the surface of the insulating film 3 and may be formed shallower than the insulating film 3.
また、他の実施例として、第６図に示すように、AlSi
電極４とAl電極５とを同じパターンで積層した構造とし
てもよいことはいうまでもない。このようにした場合、
製造面においてプロセスの増大をおこすことなく、本発
明の目的を達成することができるようになる。すなわ
ち、同一のたとえば蒸着装置にAlSi、Alの２つのソース
を配置し、各ソースを時間的に切換えて蒸着を施すよう
にすることができるようになる。As another embodiment, as shown in FIG.
Needless to say, the electrode 4 and the Al electrode 5 may be laminated in the same pattern. If you do this,
The object of the present invention can be achieved without increasing the number of processes in manufacturing. That is, two sources of AlSi and Al are arranged in the same vapor deposition apparatus, for example, and the vapor deposition can be performed by switching each source temporally.
第７図および第８図は、それぞれAl電極５の表面を平
坦にするためになされる変形例であり、それらいずれに
おいても半導体基板とオーミック接触する側においてAl
Si電極４で形成され、また表面においてはAl電極５で形
成されていればよい。FIG. 7 and FIG. 8 are modifications which are made to flatten the surface of the Al electrode 5, respectively.
What is necessary is just to be formed by the Si electrode 4 and to be formed by the Al electrode 5 on the surface.
以上説明したことから明らかなように、このように構
成した半導体装置によれば、その電極が少なくとも半導
体基板面とオーミック接触する側にてSiAl金属で形成さ
れている。このため、電極形成後にアニールと称される
熱処理を施した場合においても半導体基板内のSiが電極
側へ拡散するのを阻止することができるようになる。As is clear from the above description, according to the semiconductor device configured as described above, the electrode is formed of SiAl metal at least on the side in ohmic contact with the semiconductor substrate surface. For this reason, even when a heat treatment called annealing is performed after the electrode is formed, it is possible to prevent Si in the semiconductor substrate from diffusing toward the electrode.
また前記電極と接続されるボンディングパッドは少な
くともそのボンディングされる面にてAlで形成されてい
る。このため、ワイヤを超音波ボンディング法によりボ
ンディングする場合、そのパワーを大きくすることなく
行なうことができ、半導体素子に大きなストレスをかけ
ることがなくなる。したがってボンディングを何ら支障
なく行なうことができる。A bonding pad connected to the electrode is formed of Al at least on a surface to be bonded. For this reason, when bonding the wires by the ultrasonic bonding method, the bonding can be performed without increasing the power, and a large stress is not applied to the semiconductor element. Therefore, bonding can be performed without any trouble.
第１図は本発明による半導体装置の電極構造の一実施例
を示す構成図、第２図は第１図の詳細を示した構成図、
第３図は第１図に示す実施例においてAlに対するSiの含
有量を示すグラフ、第４図は本発明による効果を示す説
明図、第５図ないし第８図はそれぞれ本発明による他の
実施例を示す構成図である。 １…半導体基板、４…AlSi電極、５…Al電極、６…エピ
タキシャル成長層、７…ゲート酸化膜、８…ゲート電
極、9,10…拡散層、11…絶縁層、20…MOSトランジス
タ。FIG. 1 is a configuration diagram showing one embodiment of an electrode structure of a semiconductor device according to the present invention, FIG. 2 is a configuration diagram showing details of FIG. 1,
FIG. 3 is a graph showing the content of Si with respect to Al in the embodiment shown in FIG. 1, FIG. 4 is an explanatory view showing the effect of the present invention, and FIGS. 5 to 8 are other embodiments according to the present invention. It is a block diagram showing an example. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 4 ... AlSi electrode, 5 ... Al electrode, 6 ... Epitaxial growth layer, 7 ... Gate oxide film, 8 ... Gate electrode, 9,10 ... Diffusion layer, 11 ... Insulating layer, 20 ... MOS transistor.
Claims (2)
り接触させて形成された電極と、該電極に電気的に接続
して形成されたボンディングパッドとを有する半導体装
置において、前記電極は、少なくとも前記半導体基板の
主表面に接触する側がSiを含むAlで形成され、前記ボン
ディングパッドは、少なくともボンディングされる側が
Alで形成され、かつ前記電極と前記ボンディングパッド
は、前記半導体基板側からSiを含むAl層とAl層とを順次
積層させた二層構造で形成され、かつそれらの層が同一
パターンに形成されてなることを特徴とする半導体装
置。1. A semiconductor device having an electrode formed by making ohmic contact with a main surface of a semiconductor substrate and a bonding pad formed by being electrically connected to the electrode, wherein the electrode has at least the The side in contact with the main surface of the semiconductor substrate is formed of Al containing Si, and the bonding pad has at least a side to be bonded.
The electrode and the bonding pad are formed of Al, and the electrode and the bonding pad are formed in a two-layer structure in which an Al layer containing Si and an Al layer are sequentially stacked from the semiconductor substrate side, and the layers are formed in the same pattern. A semiconductor device, comprising:
造方法において、蒸着装置内にSiを含むAlとAlとの２つ
のソースを配置し、時間的に切り替えて前記Siを含むAl
層とAl層とを蒸着により形成することを特徴とする半導
体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein two sources of Al and Al containing Si are disposed in a vapor deposition apparatus, and the Al containing Al is changed over time.
A method for manufacturing a semiconductor device, comprising forming a layer and an Al layer by vapor deposition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1129533A JP2756826B2 (en) | 1989-05-23 | 1989-05-23 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1129533A JP2756826B2 (en) | 1989-05-23 | 1989-05-23 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02308539A JPH02308539A (en) | 1990-12-21 |
| JP2756826B2 true JP2756826B2 (en) | 1998-05-25 |
Family
ID=15011869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1129533A Expired - Lifetime JP2756826B2 (en) | 1989-05-23 | 1989-05-23 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2756826B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6400026B1 (en) | 1999-06-24 | 2002-06-04 | Nec Corporation | Semiconductor device with the copper containing aluminum alloy bond pad on an active region |
| US7514307B2 (en) | 2005-10-18 | 2009-04-07 | Nec Electronics Corporation | Method of manufacturing a semiconductor apparatus |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5686128B2 (en) * | 2012-11-29 | 2015-03-18 | トヨタ自動車株式会社 | Semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5249767A (en) * | 1975-10-20 | 1977-04-21 | Hitachi Ltd | Semiconductor device |
| JPS5380182A (en) * | 1976-12-25 | 1978-07-15 | Seiko Epson Corp | Semiconductor device |
| JPS63166273A (en) * | 1986-12-27 | 1988-07-09 | Tdk Corp | Vertical semiconductor device |
-
1989
- 1989-05-23 JP JP1129533A patent/JP2756826B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6400026B1 (en) | 1999-06-24 | 2002-06-04 | Nec Corporation | Semiconductor device with the copper containing aluminum alloy bond pad on an active region |
| US7514307B2 (en) | 2005-10-18 | 2009-04-07 | Nec Electronics Corporation | Method of manufacturing a semiconductor apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02308539A (en) | 1990-12-21 |
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