JPS60257166A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60257166A JPS60257166A JP11083084A JP11083084A JPS60257166A JP S60257166 A JPS60257166 A JP S60257166A JP 11083084 A JP11083084 A JP 11083084A JP 11083084 A JP11083084 A JP 11083084A JP S60257166 A JPS60257166 A JP S60257166A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- cathode
- metal plate
- gate
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- 239000007787 solid Substances 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 6
- 229910052802 copper Inorganic materials 0.000 abstract description 5
- 238000003825 pressing Methods 0.000 abstract description 3
- 229910000679 solder Inorganic materials 0.000 abstract description 2
- 229910000838 Al alloy Inorganic materials 0.000 abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 150000002739 metals Chemical class 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000012528 membrane Substances 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 101100215647 Aspergillus flavus (strain ATCC 200026 / FGSC A1120 / IAM 13836 / NRRL 3357 / JCM 12722 / SRRC 167) aflR gene Proteins 0.000 description 1
- 229910000861 Mg alloy Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007542 hardness measurement Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 229910052716 thallium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41716—Cathode or anode electrodes for thyristors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は加圧接触型の大容量半導体装置に係り（１）
特にエミッタ領域とベース領域が相互に入り組んだ構造
を有する大容量トランジスタやゲートターン等の半導体
装置に関するものである。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a pressurized contact type large-capacity semiconductor device (1) In particular, a large-capacity transistor or a gate turn The present invention relates to semiconductor devices such as the above.
〔発明の詳細な
説明の便宜上、以下ではゲート・ターンオフサイリスタ
（ＧＴＯ）を例にとって本発明を例にとって本発明を説
明する。[For convenience of detailed explanation of the invention, the present invention will be explained below by taking a gate turn-off thyristor (GTO) as an example.
ＧＴＯはアノード電極をプラス・カソード電極をマイナ
スとする方向に電圧を印加し、ゲート電極とカソード電
極間に順バイアスを印加するとターンオンし、ゲート電
極とカソード電極間に逆バイアスを印加するとオン状態
にあるＧＴＯを再びオフ状態に戻すことのできるスイッ
チング素子である。このようにＧＴＯは通常のサイリス
タと異なり、ゲート・カソード間の逆方向特性を良好に
する必要がある。さらに具体的に言えばゲート・カソー
ド間の逆方向もれ電流□を少なくし、かつ逆方向耐圧を
高くする他に、ｐペース層の横方向の抵抗を小さくする
必要がある。このためにＧＴＯでは通常のサイリスタと
異なり、ｎエミッタ領域（２）
を細いたんざく形となし、ｐベース領域はｎエミッタ領
域を取り囲んだ構造にするのが普通である。GTO is turned on when a voltage is applied in the direction of positive to the anode electrode and negative to the cathode electrode, and a forward bias is applied between the gate electrode and the cathode electrode, and it is turned on when a reverse bias is applied between the gate electrode and the cathode electrode. This is a switching element that can return a certain GTO to an off state. In this way, unlike a normal thyristor, the GTO needs to have good reverse characteristics between the gate and the cathode. More specifically, in addition to reducing the reverse leakage current □ between the gate and the cathode and increasing the reverse breakdown voltage, it is necessary to reduce the lateral resistance of the p-space layer. For this reason, in a GTO, unlike a normal thyristor, the n emitter region (2) is usually formed into a thin strip shape, and the p base region is structured to surround the n emitter region.
エミッタ電極の幅は通常５００μｍ以下であり、厚さは
１０μｍ程度であるため、電流容量を増やすとエミッタ
電極の長さ方向の電圧降下が大きくなる。したがって電
流容量を大きくするためには主電流通路がウェハの垂直
方向になるようにエミッタ電極の上に厚い金属板を加圧
接触させる必要がある。ただしＧＴＯの場合、ｐベース
電極とエミッタ電極とが相互に入り組んだ構造になって
いるため、実際にはエミッタ電極の高さをベース電極よ
りも高くする構造がとられる。第１図に従来のＧＴＯの
構造の一例を示す、１，２，３，４゜５はそれぞれ半導
体ウェハ、ｎエミッタ領域、ｐベース領域、ｎベース領
域、ｐエミッタ領域である。６はｎエミッタ領域の表面
上に形成された低抵抗接触第１主電極、７はベース領域
３の上の制御電極、８はＰエミッタ領域５の表面に低抵
抗接触した第２の主電極、９は第１の主電極６に矢印の
方向に圧力をかけたときに接触する第１の金属（３）
板、１０は第２の主電極８と固着した第２の金属板であ
る。また１１は表面安定化のための絶縁膜（例えば５ｔ
Ｏ２）である。Since the width of the emitter electrode is usually 500 μm or less and the thickness is about 10 μm, increasing the current capacity increases the voltage drop in the length direction of the emitter electrode. Therefore, in order to increase the current capacity, it is necessary to press a thick metal plate into contact with the emitter electrode so that the main current path is perpendicular to the wafer. However, in the case of GTO, since the p-base electrode and the emitter electrode are intertwined with each other, a structure is adopted in which the emitter electrode is actually higher than the base electrode. FIG. 1 shows an example of the structure of a conventional GTO, where 1, 2, 3, and 4.degree. 5 are a semiconductor wafer, an n emitter region, a p base region, an n base region, and a p emitter region, respectively. 6 is a low resistance contact first main electrode formed on the surface of the N emitter region; 7 is a control electrode on the base region 3; 8 is a second main electrode that is in low resistance contact with the surface of the P emitter region 5; 9 is a first metal plate (3) that comes into contact with the first main electrode 6 when pressure is applied in the direction of the arrow; 10 is a second metal plate fixed to the second main electrode 8; 11 is an insulating film for surface stabilization (for example, 5t
O2).
ＧＴＯは通常のサイリスタと異なり、ターンオフ時に主
電流の約１０％をゲート電極から引き抜くためにゲート
電極の抵抗を十分小さくする必要がある。このためには
制御電極は十分に厚くしなければいけない。また主電流
通路をウェハの垂直方向にするためには、第１の主電極
６（カソード電極）と第１の金属板（９）との接触抵抗
が十分小さくなるように加圧しなければいけない。一方
、カソード電極、ゲート電極はＳｔウェハとオーミック
接触し、かつ良好な導電性から通常ＡＱが使用されてい
る。Unlike a normal thyristor, the GTO requires a sufficiently low resistance of the gate electrode in order to extract about 10% of the main current from the gate electrode at turn-off. For this purpose, the control electrode must be sufficiently thick. Further, in order to make the main current path perpendicular to the wafer, pressure must be applied so that the contact resistance between the first main electrode 6 (cathode electrode) and the first metal plate (9) is sufficiently small. On the other hand, AQ is usually used for the cathode electrode and gate electrode because it makes ohmic contact with the St wafer and has good conductivity.
加圧する場合の問題点としては以下のものがある。十分
加圧しないと第１の金属板が装置の使用中にずれて、金
属板がカソード電極に片あたりしそれほど加圧しなくと
も、カソード電極がつぶれて横方向に広がり、ゲート電
極との間で短絡を引き起こす。金属板とゲート電極との
短絡も起こり（４）
易い。また金属板とカソード電極との間でスティッキン
グも起り易い状態となる。以上のことはＧＴＯが大電流
を通電するため、例えばφ３０ＩＩｌｌＩのＧＴＯに３
００Ａ程度流すと、素子は約１５０℃程度にもなるため
、上述した傾向はより顕著になる。Problems when applying pressure include the following. If sufficient pressure is not applied, the first metal plate will shift during use of the device, and the metal plate will hit the cathode electrode unevenly.Even if pressure is not applied that much, the cathode electrode will collapse and spread laterally, causing the gap between the metal plate and the gate electrode to collapse. cause short circuit. A short circuit between the metal plate and the gate electrode is also likely to occur (4). Furthermore, sticking is likely to occur between the metal plate and the cathode electrode. The above is because the GTO conducts a large current, so for example, a GTO of φ30III
When a current of about 00 A is applied, the temperature of the element reaches about 150° C., so the above-mentioned tendency becomes more pronounced.
（発明の目的〕
本発明の目的は平らな金属板をエミッタ上の主電極上に
接触抵抗を小さくした状態で配置でき。(Object of the Invention) An object of the present invention is to arrange a flat metal plate on the main electrode on the emitter with reduced contact resistance.
かつゲート、カソード間の短絡事故のない大電流をオン
・オフできる大電流半導体装置を提供するにある。Another object of the present invention is to provide a large current semiconductor device that can turn on and off a large current without causing short-circuit accidents between the gate and the cathode.
本発明は上記目的を達成するためになされたものであり
、カソード及びゲート電極を従来の純ＡＱでなく、ＡＭ
中に多く固溶する元素、例えばＭｇ、Ｌｉ、Ｃｕ等を添
加したＡＱ合金膜にすることに特徴がある。The present invention was made to achieve the above object, and the cathode and gate electrodes are made of AM instead of the conventional pure AQ.
The feature is that the AQ alloy film is made of an AQ alloy film to which a large amount of elements such as Mg, Li, Cu, etc. are added as a solid solution.
上配元索が添加されたＡＱ合金膜は純ＡＱに比べ、クリ
ープ強度が１０倍以上高いため、加圧しく５）
ても膜が変形することはなく、ゲートカソード間の短絡
事故及び金属板とのスティッキングを防止できる。Since the creep strength of the AQ alloy film to which the upper conductor has been added is more than 10 times higher than that of pure AQ, the film will not deform even if pressure is applied5), and there will be no risk of short circuits between the gate cathode or the metal plate. Sticking can be prevented.
拡散によりｎエミッタ、Ｐベースを作ったＳｌの第２の
主電極と第２の金属板とを７４０℃に加熱してＡＱろう
で接着した後、反対側の主面上のエミッタ電極とベース
電極を形成すべき部分のＳ１配化膜を除去した。次に９
９．９９％以上のＡＱ。After heating the second main electrode of Sl with an n emitter and a P base formed by diffusion and the second metal plate to 740°C and bonding them with AQ solder, the emitter electrode and base electrode on the opposite main surface are bonded. The S1 arrangement film was removed in the portion where it was to be formed. Next 9
AQ of 9.99% or more.
ＡＱ−５ｗｔ％Ｍｇ、ＡＭ−２％Ｔｉ、ＡＱ−４％Ｃｕ
、Ａｎ−２％Ｌｉ及びＡｊｉｌ−２％ｓｉのダーゲット
を用いスパッタによって上記膜を１０μｍデポした後、
ホトエツチングによりエミッタ電極とベース電極を作製
した。これらの膜を２通りの方法で評価した。１つはビ
ッカース硬度を測定する方法、もう１つはパッケージン
グ後、２００ｋｇ／ｃｄで加圧しつつ、ＲＴ〜１２０℃
の温度範囲に加熱冷却をＩＯＫ〜程度繰り返した後、耐
圧測定及び膜の変形量をめる方法である。AQ-5wt%Mg, AM-2%Ti, AQ-4%Cu
After depositing the above film to a thickness of 10 μm by sputtering using targets of An-2% Li and Ajil-2% Si,
An emitter electrode and a base electrode were fabricated by photoetching. These membranes were evaluated in two ways. One method is to measure Vickers hardness, and the other method is to measure the Vickers hardness after packaging, while applying pressure at 200 kg/cd, at RT to 120°C.
This method involves repeating heating and cooling to a temperature range of IOK or more, and then measuring the withstand pressure and calculating the amount of deformation of the film.
表１に硬さを測定した結果を示す。ＡＱ、ＡＱ（６） −２％Ｓ１膜に比べて本発明のＡＭ−２％Ｔ−ｉ 。Table 1 shows the results of hardness measurements. AQ, AQ(6) AM-2% Ti of the present invention compared to -2% S1 membrane.
ＡＱ−４％Ｍｇ、ＡＱ−２％Ｔｉ、Ａ１１ｌ−４％Ｃｕ
合金膜は２倍以上の硬さを示すことがわかる。AQ-4%Mg, AQ-2%Ti, A111-4%Cu
It can be seen that the alloy film exhibits more than twice the hardness.
表 Ｉ ＡＱ合金膜の硬さ
１但しＡｎを１として規準化している
またパッケージした後、ヒートサイクル試験を行った結
果、ＡＱ膜を用いた場合には２０００〜で、ＡＭ−２％
Ｓｉ膜の場合には６０００〜で耐圧が劣化した。一方、
Ａｆｌ−２％Ｉ、ｉ、Ａｆｉ−４％Ｍ ｇ ｖＡＱ−２
％Ｔｌ、ＡＱ−４％Ｃｕ合金膜の場合には全て１０００
０〜をクリアしたが、特にへΩ−４％Ｍｇ合金膜では２
００００〜をクリアし十分な信頼性を有することがわか
った。Table I Hardness of AQ alloy film 1 However, it is standardized with An as 1. After packaging, the heat cycle test results show that when AQ film is used, the hardness is 2000~ and AM-2%.
In the case of the Si film, the withstand voltage deteriorated at 6000 or higher. on the other hand,
Afl-2%I,i, Afi-4%M g vAQ-2
%Tl, all 1000 in case of AQ-4%Cu alloy film
0 to 2, but especially for the Ω-4% Mg alloy film.
0000~ and was found to have sufficient reliability.
（７）
第２図はヒートサイクル試験後における、膜の変形量を
測定した結果を示す。ＡＱ−２％Ｌｉ。(7) Figure 2 shows the results of measuring the amount of deformation of the membrane after the heat cycle test. AQ-2%Li.
ＡＱ−４％Ｍｇ、ＡＱ−２％Ｔｉ、ＡＱ−４％Ｃｕ合金
膜ではＡＱ、ＡＱ−２％Ｓｉ膜に比べ変形量が少ないこ
とがわかる。It can be seen that the amount of deformation is smaller in the AQ-4%Mg, AQ-2%Ti, and AQ-4%Cu alloy films than in the AQ and AQ-2%Si films.
本発明によればベース電極の小さい、平らなカソード電
極金属板を加圧接触してもゲート、カソード間の短絡の
ないＧＴＯが得られる。According to the present invention, a GTO without short circuit between the gate and the cathode can be obtained even when a flat cathode electrode metal plate with a small base electrode is brought into contact with pressure.
第１図は加圧接触型ＧＴＯの概略図、第２図はカソード
膜の変形量を示す図である。
１・・・Ｓ１ウエハ、２・・・ｎエミッタ、３・・・ｐ
ベース。
４・・・ｎベース、５・・・ｐエミッタ、６・・・エミ
ッタ電極、７・・・ベース電極、８・・・第２の主電極
、９・・・第１の金属板、１０・・・第２の金属板、１
１・・・絶縁板。
代理人 弁理士 高橋明夫
（８）
寮 （国
瞭２圀
薫 ）・−７，ｙ、（ａｏ（’／ａツ
ノ。FIG. 1 is a schematic diagram of a pressurized contact type GTO, and FIG. 2 is a diagram showing the amount of deformation of the cathode film. 1...S1 wafer, 2...n emitter, 3...p
base. 4... N base, 5... P emitter, 6... Emitter electrode, 7... Base electrode, 8... Second main electrode, 9... First metal plate, 10... ...Second metal plate, 1
1...Insulating board. Agent Patent Attorney Akio Takahashi (8) Dormitory (Kokuro 2 Kuni Kaoru)・-7,y, (ao('/atsuno.
Claims (1)
ェハの一方の主面におけるエミッタ上に形成された良導
電性からなる制御電極及び他方の主面に形成された良導
電性金属から成る第２の主電極を有し、該エミッタ上に
形成された主電極上に良導電性金属板を配置し、これら
の間の電気的接触抵抗を小さくした状態で動作せしめる
半導体装置において、該エミッタ上に形成された主電極
はＡ４合金からなり、その中に添加される元素はＡＱ中
に広い固溶限を有することを特徴とする半導体装置。 ２、特許請求の範囲第１項において、ＡＱ中の元素はＭ
ｇ ＊ Ｔ ｌ ＋ Ｌ ｉ ｅ Ｃｕであることを
特徴とする半導体装置。[Claims] 1. A control electrode having good conductivity formed on an emitter on one main surface of a semiconductor wafer having at least one pn junction therein, and a control electrode having good conductivity formed on the other main surface. In a semiconductor device that has a second main electrode made of metal, a highly conductive metal plate is placed on the main electrode formed on the emitter, and is operated with a reduced electrical contact resistance between them. . A semiconductor device, wherein the main electrode formed on the emitter is made of an A4 alloy, and the element added thereto has a wide solid solubility limit in AQ. 2. In claim 1, the element in AQ is M
A semiconductor device characterized in that g * T l + Li e Cu.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11083084A JPS60257166A (en) | 1984-06-01 | 1984-06-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11083084A JPS60257166A (en) | 1984-06-01 | 1984-06-01 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60257166A true JPS60257166A (en) | 1985-12-18 |
Family
ID=14545737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11083084A Pending JPS60257166A (en) | 1984-06-01 | 1984-06-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60257166A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01303910A (en) * | 1988-06-01 | 1989-12-07 | Hitachi Ltd | Solid-state electronic element, its manufacture and device utilizing the element |
| JPH02274008A (en) * | 1989-04-17 | 1990-11-08 | Hitachi Ltd | Solid-state electronic equipment, its manufacture, and device utilizing it |
| US6624519B1 (en) * | 1997-04-24 | 2003-09-23 | Micron Technology, Inc. | Aluminum based alloy bridge structure and method of forming same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5773945A (en) * | 1980-10-27 | 1982-05-08 | Hitachi Ltd | Semiconductor device |
| JPS57170566A (en) * | 1981-04-15 | 1982-10-20 | Toshiba Corp | Semiconductor device |
-
1984
- 1984-06-01 JP JP11083084A patent/JPS60257166A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5773945A (en) * | 1980-10-27 | 1982-05-08 | Hitachi Ltd | Semiconductor device |
| JPS57170566A (en) * | 1981-04-15 | 1982-10-20 | Toshiba Corp | Semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01303910A (en) * | 1988-06-01 | 1989-12-07 | Hitachi Ltd | Solid-state electronic element, its manufacture and device utilizing the element |
| JPH02274008A (en) * | 1989-04-17 | 1990-11-08 | Hitachi Ltd | Solid-state electronic equipment, its manufacture, and device utilizing it |
| US6624519B1 (en) * | 1997-04-24 | 2003-09-23 | Micron Technology, Inc. | Aluminum based alloy bridge structure and method of forming same |
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