JPH04290272A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH04290272A JPH04290272A JP3052906A JP5290691A JPH04290272A JP H04290272 A JPH04290272 A JP H04290272A JP 3052906 A JP3052906 A JP 3052906A JP 5290691 A JP5290691 A JP 5290691A JP H04290272 A JPH04290272 A JP H04290272A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- electrode
- region
- unit
- electrode layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005520 cutting process Methods 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 16
- 230000002950 deficient Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、電流容量を大きくする
ため複数の単位素子を１枚の半導体基板に集積し、並列
接続して用いる半導体装置およびその製造方法に関する
。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a plurality of unit elements are integrated on one semiconductor substrate and connected in parallel to increase current capacity, and a method for manufacturing the same.
【０００２】0002
【従来の技術】例えばＭＯＳ型電界効果トランジスタ
（以下ＭＯＳＦＥＴと記す） あるいは絶縁ゲート型バ
イポーラトランジスタ （以下ＩＧＢＴと記す） のよ
うにゲート電極への入力信号により主電流を制御する半
導体装置においては、大面積の主電極を流れる電流を制
御することが困難であるため、大容量化する場合には、
例えば特開昭６３−２７８２６４号公報に記載されてい
るように、容器内に数ｍｍ角の寸法の素子を並べ、それ
らのソース電極をＡｌ線のボンディングなどで相互に接
続することによりモジュール化して並列接続する方法が
とられている。[Prior art] For example, a MOS field effect transistor
In semiconductor devices such as MOSFETs (hereinafter referred to as MOSFETs) or insulated gate bipolar transistors (hereinafter referred to as IGBTs) in which the main current is controlled by input signals to the gate electrode, it is necessary to control the current flowing through the large-area main electrode. is difficult, so when increasing capacity,
For example, as described in Japanese Unexamined Patent Publication No. 63-278264, elements with dimensions of several mm square are arranged in a container and their source electrodes are connected to each other by bonding with Al wires to form a module. A method of parallel connection is used.
【０００３】しかし、このような方法では、容量が大き
くするには素子の数を多くしなければならないが、素子
の数が多くなるにつれてボンディングされる導線の配線
が複雑になり、容器内での断線などが起こりやすくなる
。さらに細い導線では、大電流を流した時に熱による断
線等もおこりやすい。However, with this method, the number of elements must be increased in order to increase the capacitance, but as the number of elements increases, the wiring of the conductive wires to be bonded becomes complicated, and the wiring inside the container becomes difficult. Wire breaks are more likely to occur. Furthermore, thin conductor wires are more likely to break due to heat when a large current is passed through them.
【０００４】この問題を解決するために、１枚の半導体
基板に多数の単位素子を集積することが考えられる。そ
して各素子の主電極に共通の電極体が圧接される加圧接
触構造にすれば、接続の信頼性が向上するばかりでなく
、接続導体のインダクタンス， 抵抗が小さくなり、ま
た基板を両面から冷却することができるので冷却効率を
上げることができる。結果として半導体装置としての特
性， 信頼性の向上につながる。In order to solve this problem, it is conceivable to integrate a large number of unit elements on one semiconductor substrate. If a pressure contact structure is adopted in which a common electrode body is pressed into contact with the main electrode of each element, not only will the reliability of the connection be improved, but the inductance and resistance of the connecting conductor will be reduced, and the board will be cooled from both sides. This makes it possible to increase cooling efficiency. As a result, this leads to improved characteristics and reliability as a semiconductor device.
【０００５】[0005]
【発明が解決しようとする課題】しかし、モジュール，
ＩＧＢＴの特性向上のために素子構造が微細化すると
、加圧時にゲート部の酸化膜などが機械的損傷を受けた
り、応力により特性が変化することが予想され、加圧接
触構造をとることが困難である。[Problem to be solved by the invention] However, the module,
As the element structure becomes finer in order to improve the characteristics of IGBTs, it is expected that the oxide film in the gate area will suffer mechanical damage when pressure is applied, or that the characteristics will change due to stress, making it impossible to adopt a pressure contact structure. Have difficulty.
【０００６】一方、１枚の基板に多数の単位素子を形成
する場合、すべての単位素子に欠陥がないとは限らず、
不良の単位素子が存在することが考えられる。このよう
な不良単位素子を切離して動作しないようにすれば半導
体装置の良品率が向上する。On the other hand, when forming a large number of unit elements on one substrate, not all unit elements are free of defects.
It is possible that a defective unit element exists. If such defective unit elements are separated and prevented from operating, the yield rate of semiconductor devices can be improved.
【０００７】本発明の目的は、微細素子構造をもってい
る場合でも、各単位素子の電極に電極体を容易に加圧接
触させることのできる半導体装置を提供することにある
。同時に製造工程中に不良単位素子の切離しが容易にで
きる半導体装置の製造方法を提供することにある。An object of the present invention is to provide a semiconductor device in which an electrode body can be easily brought into pressure contact with the electrode of each unit element even when the device has a fine element structure. At the same time, it is an object of the present invention to provide a method for manufacturing a semiconductor device in which defective unit elements can be easily separated during the manufacturing process.
【０００８】[0008]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明の半導体装置は、複数の単位素子が形成さ
れる半導体基板の一主面が複数の同じ高さの突出部を有
し、各単位素子のその突出部以外の低い部分に露出する
素子領域に接触すると共に突出部の頂面に被着する電極
層が設けられ、その電極層の突出部上の領域に共通に電
極体が圧接するものとする。そのような半導体装置は、
ＭＯＳＦＥＴ， ＩＧＢＴあるいはバイポーラトランジ
スタであることが有効である。またそのような半導体装
置の製造方法において、電極層形成後、各単位素子の電
気的特性を測定したのち、特性規定値を満足しない単位
素子の電極層を素子領域との接触部と突出部頂面上の領
域との間で切断するものとする。[Means for Solving the Problems] In order to achieve the above object, in the semiconductor device of the present invention, one main surface of a semiconductor substrate on which a plurality of unit elements are formed has a plurality of protrusions having the same height. An electrode layer is provided which is in contact with the element region exposed at the lower part of each unit element other than the protrusion and which is adhered to the top surface of the protrusion. The body shall be in pressure contact. Such a semiconductor device is
A MOSFET, IGBT or bipolar transistor is effective. In addition, in such a method for manufacturing a semiconductor device, after forming an electrode layer and measuring the electrical characteristics of each unit element, the electrode layer of a unit element that does not satisfy the specified characteristic value is removed from the contact area with the element region and the top of the protrusion. It shall be cut between the area on the surface.
【０００９】[0009]
【作用】半導体基板の突出部上にある電極層に電極体が
圧接するので、低い部分にある素子領域の露出面あるい
はその上の電極層に力が加わることがなく、機械的損傷
や応力による特性変化のおそれがなくなる。また、各単
位素子の特性測定ののち、不良単位素子の電極層を電極
体接触部と素子領域接触部の中間で切断すれば、電極体
が圧接していてもその単位素子の動作が阻止される。[Operation] Since the electrode body is in pressure contact with the electrode layer on the protruding part of the semiconductor substrate, no force is applied to the exposed surface of the element region in the lower part or the electrode layer above it, and there is no possibility of mechanical damage or stress. There is no possibility of changes in characteristics. Furthermore, after measuring the characteristics of each unit element, if the electrode layer of the defective unit element is cut between the electrode body contact part and the element area contact part, the operation of the unit element will be prevented even if the electrode body is in pressure contact. Ru.
【００１０】0010
【実施例】図１は本発明の一実施例のＩＧＢＴを示す。
図において、ｎ− 層１の一側にｐ＋ コレクタ層２が
設けられ、他側の表面層内に選択的にｐ領域３が、その
ｐ領域３の表面層内に選択的にｎ＋ エミッタ領域４が
それぞれ形成されている。ｐ領域３のｎ− 層１とｎ＋
領域４にはさまれた部分がチャネル領域で、二つのチ
ャネル領域にまたがってゲート酸化膜５を介してゲート
電極６が設けられ、ゲート電極６と絶縁されたエミッタ
電極７がｐ領域３およびｎ＋ 領域４に共通に接触して
いる。また、ｐ＋ コレクタ層２にはコレクタ電極８が
接触している。
この構造は公知のＩＧＢＴの構造であるが、この実施例
の場合、ｎ− 層１の表面に突出部１０が形成され段差
がある。段差は約２０μｍである。この段差は、例えば
エピタキシャル成長層であるｎ− 層１の上面にＳｉＯ
２ 膜でマスクを形成し、ＨＦ／ＨＮＯ３ 系のエッチ
ング液でエッチングすることにより得ることができる。
エミッタ電極７はＡｌのような導電性金属の層をパター
ニングしたものであるが、その際突出部１０の上にも延
在するようにする。
エミッタ電極７と突出部１０の頂面および側面はＳｉＯ
２ 膜１１で絶縁されている。そして、電極板９とコレ
クタ電極８とに上下から圧力を加えることにより、電極
板９を突出部１０上に延びたエミッタ電極８と圧接する
ことができる。電極板９の下面とｐ領域３， ｎ＋ 領
域４の上のエミッタ電極８との間にはｎ− 層１の段差
による距離があるため、電極板９の圧力の影響が及ぶこ
とはない。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an IGBT according to an embodiment of the present invention. In the figure, a p+ collector layer 2 is provided on one side of an n- layer 1, a p region 3 is selectively provided in the surface layer on the other side, and an n+ emitter region 4 is selectively provided in the surface layer of the p region 3. are formed respectively. n− layer 1 and n+ of p region 3
The part sandwiched between regions 4 is a channel region, and a gate electrode 6 is provided across the two channel regions via a gate oxide film 5. An emitter electrode 7 insulated from the gate electrode 6 is connected to the p region 3 and the n+ Commonly touching area 4. Further, a collector electrode 8 is in contact with the p + collector layer 2 . This structure is that of a known IGBT, but in this embodiment, a protrusion 10 is formed on the surface of the n- layer 1 and there is a step. The step difference is approximately 20 μm. This step is formed by, for example, SiO
This can be obtained by forming a mask with a 2 film and etching it with an HF/HNO3-based etching solution. The emitter electrode 7 is formed by patterning a layer of conductive metal such as Al, so that it also extends over the protrusion 10 . The top and side surfaces of the emitter electrode 7 and the protrusion 10 are made of SiO
2 Insulated by film 11. Then, by applying pressure to the electrode plate 9 and the collector electrode 8 from above and below, the electrode plate 9 can be brought into pressure contact with the emitter electrode 8 extending above the protrusion 10 . Since there is a distance between the lower surface of the electrode plate 9 and the emitter electrode 8 above the p region 3 and n+ region 4 due to the step of the n- layer 1, the pressure of the electrode plate 9 does not affect the emitter electrode 8.
【００１１】この状態でゲート電極６およびエミッタ電
極７にプローブを接触させ電気的特性を測定する。その
結果、ゲート電極６１の下の単位素子１２が不良である
ことがわかった場合、この単位素子のエミッタ電極７１
，７２を突出部１０の側面上１３， １４で切断する。
切断はレーザトリミングやエッチングなどで行う。これ
によりこの単位素子１２は動作しなくなり、半導体装置
全体としての特性としては問題なくなる。In this state, a probe is brought into contact with the gate electrode 6 and the emitter electrode 7 to measure the electrical characteristics. As a result, if the unit element 12 under the gate electrode 61 is found to be defective, the emitter electrode 71 of this unit element
, 72 are cut on the side surfaces 13 and 14 of the protrusion 10. Cutting is performed by laser trimming, etching, etc. As a result, this unit element 12 ceases to operate, and there is no problem with the characteristics of the semiconductor device as a whole.
【００１２】上記実施例では加圧接触型ＩＧＢＴについ
て述べたが、本発明は加圧接触型ＭＯＳＦＥＴあるいは
加圧接触型バイポーラトランジスタなどにも同様に実施
できる。In the above embodiments, a pressure contact type IGBT has been described, but the present invention can be similarly applied to a pressure contact type MOSFET or a pressure contact type bipolar transistor.
【００１３】[0013]
【発明の効果】本発明によれば、一つの半導体基板に集
積されるＩＧＢＴなどの各単位素子本体とその電極の圧
接部とを半導体基板一面上の段差で位置的に分離するこ
とにより、微細構造の場合でも素子特性に影響を与える
ことなく電極体を圧接することを可能にした。また、不
良単位素子の切離しを、電極層と圧接部と素子領域との
間で切断することにより簡単に行うことができ、不良基
板数を減らし、製造歩留まりを向上させることができた
。According to the present invention, the main body of each unit element such as an IGBT integrated on one semiconductor substrate and the press-contact portion of its electrode are separated positionally by a step on one surface of the semiconductor substrate. Even in the case of a structure, it is possible to press the electrode body without affecting the device characteristics. In addition, defective unit elements can be easily separated by cutting between the electrode layer, the press-contact portion, and the element region, thereby reducing the number of defective substrates and improving manufacturing yield.
【図１】本発明の一実施例のＩＧＢＴの要部断面図[Fig. 1] A cross-sectional view of the main parts of an IGBT according to an embodiment of the present invention.
１ ｎ− 層 ２ ｐ＋ コレクタ層 ３ ｐ領域 ４ ｎ＋ エミッタ領域 ５ ゲート酸化膜 ６ ゲート電極 ７ エミッタ電極 ８ コレクタ電極 ９ 電極板 １０ 突出部 １２ 単位ＩＧＢＴ素子 １３ 切断部 １４ 切断部 1 n- layer 2 p+ collector layer 3 p region 4 n+ emitter region 5 Gate oxide film 6 Gate electrode 7 Emitter electrode 8 Collector electrode 9 Electrode plate 10 Protruding part 12 Unit IGBT element 13 Cutting section 14 Cutting section
Claims (5)
一主面が複数の同じ高さの突出部を有し、各単位素子の
その突出部以外の低い部分に露出する素子領域に接触す
ると共に突出部の頂面に被着する電極層が設けられ、そ
の電極層の突出部上の領域に共通に電極体が圧接するこ
とを特徴とする半導体装置。1. One main surface of a semiconductor substrate on which a plurality of unit elements are formed has a plurality of protrusions having the same height, and contacts an element region exposed in a lower part of each unit element other than the protrusions. At the same time, an electrode layer is provided on the top surface of the protrusion, and an electrode body is commonly pressed into contact with a region of the electrode layer on the protrusion.
項１記載の半導体装置。2. The semiconductor device according to claim 1, which is a MOS field effect transistor.
る請求項１記載の半導体装置。3. The semiconductor device according to claim 1, which is an insulated gate bipolar transistor.
載の半導体装置。4. The semiconductor device according to claim 1, which is a bipolar transistor.
体装置の製造方法において、電極層形成後、各単位素子
の電気的特性を測定したのち、特性規定値を満足しない
単位素子の電極層を素子領域との接触部と突出部頂面上
の領域との間で切断することを特徴とする半導体装置の
製造方法。5. In the method of manufacturing a semiconductor device according to claim 1, after forming the electrode layer, measuring the electrical characteristics of each unit element, the electrode of the unit element that does not satisfy the specified characteristic value is determined. 1. A method of manufacturing a semiconductor device, comprising cutting a layer between a contact portion with an element region and a region on a top surface of a protrusion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3052906A JPH04290272A (en) | 1991-03-19 | 1991-03-19 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3052906A JPH04290272A (en) | 1991-03-19 | 1991-03-19 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04290272A true JPH04290272A (en) | 1992-10-14 |
Family
ID=12927884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3052906A Pending JPH04290272A (en) | 1991-03-19 | 1991-03-19 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04290272A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07202202A (en) * | 1993-12-24 | 1995-08-04 | Consorzio Per La Ric Sulla Microelettronica Nel Mezzogiorno | Mos device chip for electric power and package assembly |
| US5635734A (en) * | 1994-03-16 | 1997-06-03 | Hitachi, Ltd. | Insulated gate type semiconductor device in which the reliability and characteristics thereof are not deteriorated due to pressing action and power inverter using the same |
| JP2002170784A (en) * | 2000-12-01 | 2002-06-14 | Denso Corp | Silicon carbide semiconductor device and manufacturing method thereof |
-
1991
- 1991-03-19 JP JP3052906A patent/JPH04290272A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07202202A (en) * | 1993-12-24 | 1995-08-04 | Consorzio Per La Ric Sulla Microelettronica Nel Mezzogiorno | Mos device chip for electric power and package assembly |
| US5635734A (en) * | 1994-03-16 | 1997-06-03 | Hitachi, Ltd. | Insulated gate type semiconductor device in which the reliability and characteristics thereof are not deteriorated due to pressing action and power inverter using the same |
| JP2002170784A (en) * | 2000-12-01 | 2002-06-14 | Denso Corp | Silicon carbide semiconductor device and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5374831B2 (en) | Power electronic package having two substrates with a plurality of semiconductor chips and electronic components | |
| US7557434B2 (en) | Power electronic package having two substrates with multiple electronic components | |
| US6569764B1 (en) | Method of manufacturing a semiconductor package by attaching a lead frame to a semiconductor chip via projecting electrodes and an insulating sheet of resin material | |
| US7842545B2 (en) | Semiconductor package having insulated metal substrate and method of fabricating the same | |
| JP3675603B2 (en) | Semiconductor device | |
| US4161740A (en) | High frequency power transistor having reduced interconnection inductance and thermal resistance | |
| JPS59121871A (en) | Semiconductor device | |
| JP3319569B2 (en) | Pressure contact type semiconductor device | |
| US5366932A (en) | Semi-conductor chip packaging method and semi-conductor chip having interdigitated gate runners with gate bonding pads | |
| US5874774A (en) | Flat package semiconductor device | |
| JP2987088B2 (en) | MOS technology power device chips and package assemblies | |
| JPH04290272A (en) | Semiconductor device and manufacture thereof | |
| JP3629172B2 (en) | Pressure contact type semiconductor device | |
| CN101371344B (en) | Field effect transistor | |
| JP2669392B2 (en) | Semiconductor device and its mounting structure | |
| JPH09135023A (en) | Pressure-contact type semiconductor device | |
| JP2000074988A (en) | Production of semiconductor device | |
| US5798287A (en) | Method for forming a power MOS device chip | |
| US5821616A (en) | Power MOS device chip and package assembly | |
| JP2000114525A (en) | Semiconductor device and manufacture thereof | |
| CN115547963B (en) | Insulated gate bipolar transistor | |
| WO2020183603A1 (en) | Pressure-contact semiconductor device | |
| CN109994445B (en) | Semiconductor element and semiconductor device | |
| JPH0541485A (en) | Manufacture of mos semiconductor element | |
| JP2005064532A (en) | Semiconductor device |