JPS60102761A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a microscopic solder electrode having no uneven resistance and bridging on a conductive circuit generated by the running of solder by a method wherein no solder is provided on the non-contacting part of the internal electrode located at a stepped part, solder is provided only between the internal electrode and the electrode which is low-resistance-contacted to a semiconductor substrate. CONSTITUTION:A silicon oxide film 8 is formed on the N-emitter layer 1d juxtaposed on the main surface part constituting a rectangular narrow strip-form part which is divided into a plurality of parts and on the main surface of the silicon substrate 1 having a P-base layer 1c surrounding the layer 1d, and a cathode electrode and a gate electrode 10 are low-resistance-contacted to the layers 1c and 1d through the aperture provided on the film 8. Then, the electrode 10 is connected to the tooth-formed part 3a of a gate plate 3. No solder is allowed to be present on the electrode 10 and the non-contacting part of the stepped part 3b on the gate plate 3 by connecting the gate plate 3 to a gate terminal 7 at the position located higher than the main surface of the substrate 1.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to semiconductor devices such as transistors, static induction transistors, static induction thyristors, and gate turn-off thyristors in which one semiconductor layer such as an emitter layer has a fine pattern structure. In particular, it relates to its electrode structure.

[Background of the invention]

In the above semiconductor device, two semiconductor layers are exposed on the surface of the semiconductor substrate, one of which is divided into a plurality of strips, and each strip has a fine pattern structure surrounded by the other semiconductor layer. It becomes.

A first electrode is in low resistance contact with each strip, and a second electrode is in low resistance contact with the other semiconductor layer so as to substantially surround each strip.

Normally, each area formed by vertically projecting each strip onto the other main surface is considered to be an operating unit element, and multiple operating unit elements are compounded in order and in parallel within the semiconductor substrate. I regard it as such.

For those with a small current capacity, the strips are arranged in parallel so that their longitudinal directions are parallel to each other. In order to connect the semiconductor substrate with such a configuration to an external circuit, an internal conductor is placed inside the bag that houses the semiconductor substrate,
There is a so-called fine solder electrode in which an internal conductor is connected to a first electrode and a second electrode by solder (Japanese Patent Application Laid-open No. 78173/1983).

In order to improve the connection between the internal conductor and the second electrode and improve the characteristics of the semiconductor device, the internal conductor is the first.

Almost the entire length of each second electrode is connected by solder,
The end portion is connected to an external terminal introduced through the package. In this case, if the end is placed with a difference in level from the main surface of the semiconductor substrate and solder is applied all over the internal conductor and various heat treatments are performed, the solder will drip down and the collected solder will be removed. Even if it spreads horizontally and bridges between internal conductors, or even if it is bridged several times, it does not cause uniform sagging, which causes a difference in the overall resistance on the conductive path including each solder, and this Therefore, an unbalance occurs in the current flowing through the internal conductor, causing variations in the dynamic characteristics of the operating unit elements, and in extreme cases, they become inoperable.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a highly reliable fine solder electrode structure without uneven resistance or bridging on a conductive path due to solder dripping.

[Summary of the invention]

The present invention, which achieves the above object, is characterized in that solder is not provided on the non-contact portions of the internal electrodes at the stepped portions, and only solder is provided between the internal electrodes and the electrodes that are in low resistance contact with the semiconductor substrate. This is because we have set it up.

[Embodiments of the invention]

The present invention will be described below with reference to embodiments shown in the drawings.

In FIG. 1, 1 is a silicon substrate with a gate turn-off thyristor function, 2.3 is a comb-shaped copper cathode plate and gate plate as internal conductors, 4.5 is a ceramic insulating stand fi, 6 .7 is a cathode terminal and a gate terminal made of copper which are led out from a package (not shown) and connected to an external circuit. As shown in FIG. 2, the silicon substrate 1 has a p-emitter layer 1a, an n-base layer ib, a p-base layer IC, and an n-etched vine layer 1d, which are adjacent to each other and have different conductivity types in sequence between the upper and lower main surfaces. ing. The p base layer IC and the n emitter layer 1d are exposed on the upper main surface. The n-emitter layer 1d is divided into a plurality of parts, each of which is a strip-like strip and arranged in parallel on the upper main surface with their longitudinal directions aligned. Each n emitter layer 1d has a p base/! It is surrounded by IC.

1e is a layer with high n impurity concentration. n emitter layer 1d is n
A substantially elliptical shape is provided for each n emitter layer 1d in a portion where the ring portion of the emitter layer 1d is vertically projected onto the lower main surface side. A silicon oxide film 8 is provided as a surface stabilizing film on the upper main surface, and a cathode electrode 9 and a cathode electrode 10 are connected to the n-emitter layer 1 through the entire opening provided in the silicon oxide film.
Low resistance contact is made to the d and p base layer IC. The cathode electrode 9 and the gate electrode 10 have a three-layer structure of chromium-nickel-silver from the silicon substrate 1 side, but the layer divisions are omitted in the drawing. The gate electrode 10 is n
Each n emitter layer 1 is arranged on both sides of the emitter layer 1d.
It almost surrounds d.

The cathode electrode 9 is connected to the toothed portion 2a of the cathode plate 2 through solder 11, and the gate electrode 10 is connected to the toothed portion 3a of the cathode plate 3 through solder 12. An anode electrode 13 having a three-layer structure of chromium-nickel-silver is provided on the lower main surface of the silicon substrate 1 from the main surface side, and includes h and p emitter layers 1a.

It is in low resistance contact with the n impurity high concentration layer.

The silicon substrate 1 and the insulating stand 4.5 are placed on a copper base (not shown). As is clear from FIG. 1, the ends of the cathode plate 2 and gate plate 3 are connected with a step at a position higher than the cathode terminal 6, gate terminal 7, and the upper main surface of the silicon substrate 1. 1, the cathode plate 9 and gate plate 10 are entirely covered with a nickel film.

It is omitted in FIG.

The cathode plate 9 and the gate plate 10 are connected to the silicon substrate 1 in the following manner.

A copper foil with a nickel film on one side is attached to a polyimide isoisodroquinazolinedione film with an adhesive, with the nickel film facing the film, and the copper foil and nickel film are etched as shown in Figure 3. Remove it and
Apply fine pattern processing. FPC in this condition
(Flexible printed C1rcuit
). In Fig. 3, 21 is FPC, 22 is film, 23 and 24 are fine patterns (copper foil after 1st process),
The copper foil 23 is the cathode plate 2. The copper foil 24 becomes the gate plate 3.

A nickel film, a lead film, and a tin film are sequentially laminated on the copper foil of this F'PC 21 by plating technology. The nickel film is attached to the copper foil 2 together with the nickel film previously provided on the copper foil 23 and 24.
3 and 24 are completely covered.

The lead film and the tin film are connected to the cathode 'PIL pole 9. of the silicon substrate 1 while the copper foils 23 and 24 are connected to the cathode 'PIL pole 9. Gate electrode I
It is provided only in the area corresponding to the area connected to O.

This region is shown with diagonal lines in FIG.

Similarly, the thickness of the lead layer is 20 μm, and the thickness of the tin layer is about 1 μm.

Next, the silicon substrate 1, which has been separately subjected to impurity diffusion treatment, is heated to around 280C to form a cathode.9. In order to align the gate electrode 10 and the FPC copper foils 23 and 24, the silicon substrate 1 and the FPC 21 are temporarily bonded by using the melting of the tin layer on the PPC 21.

Furthermore, for the temporarily bonded silicon substrate 1 and FPC 21,
A heat treatment of 360 to 380 t is performed to promote mutual diffusion of the lead layer and tin layer on the PPC 21 to form an alloy solder.This alloy solder forms the cathode electrode 9 on the silicon substrate 1. The gate electrode 10 and the copper foils 23 and 24 on the FPC 21 are connected with high precision. At this time, the adhesive that adhered the film 22 and the copper foils 23 and 24 deteriorates due to thermal history, and the film 22 peels off from the copper foils 23 and 24, and the copper foil 23 is attached to the cathode plate 3. The copper foil 24 is the gate plate 3
becomes. Since the copper foils 23 and 24 are flat at this point,
After the shaping process, as shown in FIG. 1, a silicon substrate 1, insulating stands 4, 5, . Cathode terminal 6. The gate terminals 7 and the like are arranged at predetermined positions and soldered together.

As shown in FIG. 4, there is no solder in the portion of the stepped portion 3b of the gate plate 3 that is not in contact with the gate electrode 10. As shown in FIG. Therefore, even if some thermal history is applied to the gate plate 3, molten solder will not drip down. Since there is no solder on the step portion 3b and only a predetermined amount of solder on the toothed portion 3a, the gate electrode 1 on the silicon substrate 1
Since the electrical resistance on the conductive path from 0 to the step portion 3b is almost uniform in the plurality of toothed portions 3a, the gate electrode 3
The gate signal flowing through each toothed portion 3 B f is uniform,
Therefore, each operating unit element operates uniformly in parallel.

4, 31a and 31b are metal vapor deposited films provided on the insulating stand 5 to improve soldering.

32 and 33 are solder, which is placed as a foil between the gate plate 3, the gate terminal 7, and the insulating base 5, and is melted and integrated by heat treatment.

Since there is no solder on the stepped portion 3b of the gate terminal 73, the solder does not sag during heat treatment to bridge the cathode electrode 9 and the gate ilt electrode 10.

FIG. 5 shows a situation in which solder is also provided on the stepped portion 3b, and as a result of the solder hanging down, the solder 41 bridges between both electrodes 9 and 10.

I have explained the gate plate above, but these (9) This also applies to the cathode plate 2 side.

In the conventional device that caused solder droop, the non-uniformity of the parallel operation led to a deterioration of the characteristics, and the effect was particularly significant on the transient switching characteristics, and a decrease in capacity of about 10% was confirmed at the current level, but in the present invention, No capacity reduction occurred.

In the conventional device in which solder is provided on the entire gate plate 3, the occurrence rate of bridging due to solder is 20 to 50%, but in the present invention, the occurrence rate is 0%.

In the above embodiments, both the cathode plate 2 and the gate plate 3 are provided with a fine solder electrode structure, but the present invention can be practiced even if the structure is applied to only one of them. Further, although the p emitter layer 1a is short-circuited to the n-impurity high concentration layer 1e and the anode electrode 13, a non-short-circuit structure may also be used. The cathode electrode 9 and the gate electrode 10 do not need to be located on the same plane.

That is, the p base layer 1c may be etched down, and the gate electrode 10 may be provided at the inner bottom thereof.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain a semiconductor device having a highly reliable fine solder electrode structure without uneven resistance or bridging on the conductive path due to solder dripping (10).

[Brief explanation of the drawing]

FIG. 1 is a perspective view of a silicon substrate and its surrounding members showing an embodiment of the present invention, FIG. 2 is a cross-sectional view of the silicon substrate shown in FIG. 1, and FIG. 3 is a diagram of an FPC used in the present invention. 4 is an enlarged view of the main part of the silicon substrate shown in FIG. 1, and FIG. 5 is a plan view of the main part of the silicon substrate in which the cathode electrode and the gate electrode are bridged with solder. 1...Silicon base, 1a...p emitter layer, 1b
...n base 11J, lc...p pace/Lid.
...n emitter layer, 1e...n high impurity concentration layer, 2.
... Cathode plate, 2a... Teeth, 3... Gate plate, 3a... Teeth, 3b... Step portion, 4, 5...
Insulation stand, 6... cathode terminal, 7... gate terminal,
8... Silicon oxide film, 9... Cathode electrode, 10
...Gate electrode, 11,12°32.33.41...
・Solder, 13... Anode electrode, 21... FPC,
22...Film, 23.24...Copper (11) foil, 31a, 31b...Metal vapor deposition film. Agent Patent Attorney Akio Takahashi (12) #2 /3 /”,j#2

Claims (1)

[Claims] 1゜Two semiconductors with different conductivity types are exposed on the surface of the semiconductor substrate during the lifetime, one semiconductor layer is divided into a plurality of strips, and each nuclear strip is surrounded by the other semiconductor layer. A first electrode of substantially the same shape is in low-resistance contact with each strip, and a second electrode is in low-resistance contact with the other semiconductor layer so as to substantially surround each strip of one of the semiconductor layers. In a semiconductor device in which an internal conductor is connected to at least one of the two electrodes by soldering, and one end side of the internal conductor has a step with the surface of the semiconductor substrate, one of the internal conductors at the step part. A semiconductor device characterized by the fact that solder does not exist in the non-contact parts with the electrodes, but only in the connection parts between one electrode and the internal conductor.