JPS63293639A - 順序正しくないフエツチをモニタするための装置 - Google Patents

順序正しくないフエツチをモニタするための装置

Info

Publication number
JPS63293639A
JPS63293639A JP63093613A JP9361388A JPS63293639A JP S63293639 A JPS63293639 A JP S63293639A JP 63093613 A JP63093613 A JP 63093613A JP 9361388 A JP9361388 A JP 9361388A JP S63293639 A JPS63293639 A JP S63293639A
Authority
JP
Japan
Prior art keywords
address
order
fetch
fetches
stack
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63093613A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0552968B2 (en, 2012
Inventor
フイリツプ・ジヨージ・エマ
ジユシユワ・ウイリソン・ナイト、サード
ジエームズ・ハーバート・ポマーリン
ルドルフ・ネイザン・リクスチヤーフアン
フランク・ジヨン・スパラシオ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS63293639A publication Critical patent/JPS63293639A/ja
Publication of JPH0552968B2 publication Critical patent/JPH0552968B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
JP63093613A 1987-05-18 1988-04-18 順序正しくないフエツチをモニタするための装置 Granted JPS63293639A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/051,792 US4991090A (en) 1987-05-18 1987-05-18 Posting out-of-sequence fetches
US51792 1987-05-18

Publications (2)

Publication Number Publication Date
JPS63293639A true JPS63293639A (ja) 1988-11-30
JPH0552968B2 JPH0552968B2 (en, 2012) 1993-08-06

Family

ID=21973404

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63093613A Granted JPS63293639A (ja) 1987-05-18 1988-04-18 順序正しくないフエツチをモニタするための装置

Country Status (4)

Country Link
US (1) US4991090A (en, 2012)
EP (1) EP0302999B1 (en, 2012)
JP (1) JPS63293639A (en, 2012)
DE (1) DE3884101T2 (en, 2012)

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US5781753A (en) 1989-02-24 1998-07-14 Advanced Micro Devices, Inc. Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions
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US5093777A (en) * 1989-06-12 1992-03-03 Bull Hn Information Systems Inc. Method and apparatus for predicting address of a subsequent cache request upon analyzing address patterns stored in separate miss stack
JPH0348951A (ja) * 1989-07-18 1991-03-01 Fujitsu Ltd アドレスモニタ装置
US5185871A (en) * 1989-12-26 1993-02-09 International Business Machines Corporation Coordination of out-of-sequence fetching between multiple processors using re-execution of instructions
US5197139A (en) * 1990-04-05 1993-03-23 International Business Machines Corporation Cache management for multi-processor systems utilizing bulk cross-invalidate
US5151981A (en) * 1990-07-13 1992-09-29 International Business Machines Corporation Instruction sampling instrumentation
US5446850A (en) * 1991-01-15 1995-08-29 International Business Machines Corporation Cross-cache-line compounding algorithm for scism processors
US5257354A (en) * 1991-01-16 1993-10-26 International Business Machines Corporation System for monitoring and undoing execution of instructions beyond a serialization point upon occurrence of in-correct results
US5261071A (en) * 1991-03-21 1993-11-09 Control Data System, Inc. Dual pipe cache memory with out-of-order issue capability
US5630157A (en) * 1991-06-13 1997-05-13 International Business Machines Corporation Computer organization for multiple and out-of-order execution of condition code testing and setting instructions
US5317711A (en) * 1991-06-14 1994-05-31 Integrated Device Technology, Inc. Structure and method for monitoring an internal cache
US5636363A (en) * 1991-06-14 1997-06-03 Integrated Device Technology, Inc. Hardware control structure and method for off-chip monitoring entries of an on-chip cache
JP2786574B2 (ja) * 1992-05-06 1998-08-13 インターナショナル・ビジネス・マシーンズ・コーポレイション コンピュータ・システムにおける順不同ロード動作の性能を改善する方法と装置
US5355471A (en) * 1992-08-14 1994-10-11 Pyramid Technology Corporation Multiprocessor cache coherency tester that exercises the coherency logic exhaustively and also detects errors in a processor using an automatic CPU sort
US6735685B1 (en) 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
EP0663083B1 (en) 1992-09-29 2000-12-20 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US5488706A (en) * 1992-12-18 1996-01-30 Amdahl Corporation Retry request system in a pipeline data processing system where each requesting unit preserves the order of requests
US5467473A (en) * 1993-01-08 1995-11-14 International Business Machines Corporation Out of order instruction load and store comparison
US5493669A (en) * 1993-03-03 1996-02-20 Motorola, Inc. Data processor for simultaneously searching two fields of the rename buffer having first and second most recently allogated bits
JP2560988B2 (ja) * 1993-07-16 1996-12-04 日本電気株式会社 情報処理装置および処理方法
US6138230A (en) * 1993-10-18 2000-10-24 Via-Cyrix, Inc. Processor with multiple execution pipelines using pipe stage state information to control independent movement of instructions between pipe stages of an execution pipeline
US5463745A (en) * 1993-12-22 1995-10-31 Intel Corporation Methods and apparatus for determining the next instruction pointer in an out-of-order execution computer system
US5535358A (en) * 1993-12-27 1996-07-09 Matsushita Electric Industrial Co., Ltd. Cache memory control circuit and method for controlling reading and writing requests
US5588126A (en) * 1993-12-30 1996-12-24 Intel Corporation Methods and apparatus for fordwarding buffered store data on an out-of-order execution computer system
US5627985A (en) * 1994-01-04 1997-05-06 Intel Corporation Speculative and committed resource files in an out-of-order processor
US5898854A (en) * 1994-01-04 1999-04-27 Intel Corporation Apparatus for indicating an oldest non-retired load operation in an array
US5452426A (en) * 1994-01-04 1995-09-19 Intel Corporation Coordinating speculative and committed state register source data and immediate source data in a processor
US5577200A (en) * 1994-02-28 1996-11-19 Intel Corporation Method and apparatus for loading and storing misaligned data on an out-of-order execution computer system
US5465336A (en) * 1994-06-30 1995-11-07 International Business Machines Corporation Fetch and store buffer that enables out-of-order execution of memory instructions in a data processing system
US5699538A (en) * 1994-12-09 1997-12-16 International Business Machines Corporation Efficient firm consistency support mechanisms in an out-of-order execution superscaler multiprocessor
TW295646B (en, 2012) * 1995-01-25 1997-01-11 Ibm
US5649155A (en) * 1995-03-31 1997-07-15 International Business Machines Corporation Cache memory accessed by continuation requests
US5751946A (en) * 1996-01-18 1998-05-12 International Business Machines Corporation Method and system for detecting bypass error conditions in a load/store unit of a superscalar processor
US5737636A (en) * 1996-01-18 1998-04-07 International Business Machines Corporation Method and system for detecting bypass errors in a load/store unit of a superscalar processor
JP2806359B2 (ja) * 1996-04-30 1998-09-30 日本電気株式会社 命令処理方法及び命令処理装置
JP2783259B2 (ja) * 1996-07-18 1998-08-06 日本電気株式会社 半導体パッケージとその製造方法
US6021261A (en) * 1996-12-05 2000-02-01 International Business Machines Corporation Method and system for testing a multiprocessor data processing system utilizing a plurality of event tracers
US5909698A (en) * 1997-03-17 1999-06-01 International Business Machines Corporation Cache block store instruction operations where cache coherency is achieved without writing all the way back to main memory
US6289437B1 (en) * 1997-08-27 2001-09-11 International Business Machines Corporation Data processing system and method for implementing an efficient out-of-order issue mechanism
JP2004094533A (ja) * 2002-08-30 2004-03-25 Hajime Seki 計算機システム
US9483409B2 (en) 2015-02-05 2016-11-01 International Business Machines Corporation Store forwarding cache
US20250258670A1 (en) * 2024-02-13 2025-08-14 Apple Inc. Reservation station with multiple entry types

Citations (1)

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JPS6077241A (ja) * 1983-10-05 1985-05-01 Hitachi Ltd 情報処理装置

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Also Published As

Publication number Publication date
JPH0552968B2 (en, 2012) 1993-08-06
DE3884101T2 (de) 1994-04-21
EP0302999A2 (en) 1989-02-15
US4991090A (en) 1991-02-05
DE3884101D1 (de) 1993-10-21
EP0302999A3 (en) 1991-11-06
EP0302999B1 (en) 1993-09-15

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