JPS6329297B2 - - Google Patents

Info

Publication number
JPS6329297B2
JPS6329297B2 JP55030353A JP3035380A JPS6329297B2 JP S6329297 B2 JPS6329297 B2 JP S6329297B2 JP 55030353 A JP55030353 A JP 55030353A JP 3035380 A JP3035380 A JP 3035380A JP S6329297 B2 JPS6329297 B2 JP S6329297B2
Authority
JP
Japan
Prior art keywords
memory
address
processor
cache memory
translation mechanism
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55030353A
Other languages
English (en)
Japanese (ja)
Other versions
JPS56127261A (en
Inventor
Tadaaki Bando
Yasushi Fukunaga
Tetsuya Kawakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Industry and Control Solutions Co Ltd
Original Assignee
Hitachi Engineering Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Engineering Co Ltd, Hitachi Ltd filed Critical Hitachi Engineering Co Ltd
Priority to JP3035380A priority Critical patent/JPS56127261A/ja
Publication of JPS56127261A publication Critical patent/JPS56127261A/ja
Publication of JPS6329297B2 publication Critical patent/JPS6329297B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
JP3035380A 1980-03-12 1980-03-12 Multiprocessor system Granted JPS56127261A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3035380A JPS56127261A (en) 1980-03-12 1980-03-12 Multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3035380A JPS56127261A (en) 1980-03-12 1980-03-12 Multiprocessor system

Publications (2)

Publication Number Publication Date
JPS56127261A JPS56127261A (en) 1981-10-05
JPS6329297B2 true JPS6329297B2 (cs) 1988-06-13

Family

ID=12301478

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3035380A Granted JPS56127261A (en) 1980-03-12 1980-03-12 Multiprocessor system

Country Status (1)

Country Link
JP (1) JPS56127261A (cs)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5898893A (ja) * 1981-12-09 1983-06-11 Toshiba Corp 情報処理装置
US4616341A (en) * 1983-06-30 1986-10-07 International Business Machines Corporation Directory memory system having simultaneous write and comparison data bypass capabilities
GB8408444D0 (en) * 1984-04-02 1984-05-10 Hemdal G Computer systems
JPS63170898A (ja) * 1986-07-01 1988-07-14 株式会社　東宏企画 電子安定器
US5247649A (en) * 1988-05-06 1993-09-21 Hitachi, Ltd. Multi-processor system having a multi-port cache memory

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS529495A (en) * 1975-07-12 1977-01-25 Yasumoto Takahashi Coin receiving device of vending machine

Also Published As

Publication number Publication date
JPS56127261A (en) 1981-10-05

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