JPS63287071A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain high mutual conductance and low gate resistance, by depositing the same metal film as source and drain electrodes on a gate electrode, and determining the interval between the gate electrode and the source and drain electrodes with the width of the sidewalls of the gate. CONSTITUTION:On a GaAs substrate 1, an N-type channel layer 2, a gate electrode 3, and low resistance N<+> layers 4a and 4b are formed. An Si nitride film 6 is deposited on the entire surface. The film 6 is covered with a photoresist film 7. The film 7 is etched, and the protruding upper surface of the film 6 is exposed. With resist films 7a and 7b as masks, the film 6 is etched in an isotropic pattern. Anisotropic etching is further performed, and Si nitride films 6a and 6b on both sides of the electrode 3 are removed. Then an SOG film 8 is applied by spin coating. The entire surface is etched, and the upper surfaces of the films 6a and 6b are exposed. Only the Si nitride films 6a and 6b are etched away, and the SOG films 8a and 8b are made to remain as the sidewalls of the electrode 3. Au, Ge, Ni and Au are sequentially evaporated and source and drain electrodes 5a and 5b and a gate electrode 9 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to improvement of a gallium arsenide Schottky junction field effect transistor (hereinafter referred to as "GaAs MESFET").

[Conventional technology]

The schematic configuration of a GaAs MESFET manufactured using the conventional gate/n+ self-alignment technology is shown in the second example.
As shown in the figure.

In FIG. 2, 1 is a semi-insulating GaAs substrate, 2 is an n-type channel layer formed on the main surface of this semi-insulating GaAs substrate 1, and 3 is a gate electrode that is in Schottky contact with the n-type channel layer 2. It is made of a high melting point material, such as a high melting point metal, a high melting point metal silicide, etc.
, 4b are low resistance n+ layers formed adjacent to the gate electrode 3 by ion implantation and annealing using the gate electrode 3 of B as a mask, and 5a and 5b are low resistance n+ layers formed on each of these low resistance n+7@4a and 4b. The source and drain electrodes are ohmically connected.

Here, in a semiconductor device using a GaAsIA integrated circuit formed by this type of GaAsM ES FET or this GaA sMI SF E '1)', it is generally difficult to realize an ultra-high-speed operation element. Various improvements are currently being considered to further improve performance. 1 for this improvement
The two major points are the mutual conductance g of the FET.
The goal is to increase m, and for this purpose, it is extremely important to reduce the gate length and reduce the series resistance It between the gate and source.

and 01) series resistance R between the gate and source.

A gate/n+ self-line (self-alignment) method is known as a means for reducing the
is the device configuration shown in FIG. 2 described above. However, in the case of Party B, 1) Important points I. in realizing the device configuration are:
The purpose is to form a low resistance n'Jfida, 4b, and for this purpose, as described above, with the gate electrode 3 formed,
Annealing 1 to activate the implanted ions: approximately
In normal cases, d is heat treated to about 800℃.
I am a connoisseur. Therefore, for this purpose, the gate electrode 3 may be melted by this heat treatment or made of Ga.
A material that does not react with As and exhibits good Schottky characteristics is used, and various materials such as tungsten silicide (WS) are being considered for this electrode material.

[Problems to be solved by the invention] ° - Conventional gate/n' self-alignment line GaAsMES as described above
i''ET has a high mutual conductance gta6! and excellent characteristics, but generally the heat-resistant gate film as the gate electrode 3 is made of, for example, tungsten silicide (W). S
In the case of i
If the gate length is shortened, the gate resistance increases, which limits high-frequency operation, making it difficult to apply it to microwave linear FETs that require a large gate width and low gate resistance. In the meantime, there was one point.

This invention was made to solve the above-mentioned conventional problems, and its purpose is to have high mutual conductance and low gate resistance, even at high frequencies in the microwave band. ^ The purpose is to obtain a method for manufacturing a semiconductor device that operates with high performance.

[Means for solving problems]

A method for manufacturing a semiconductor device according to the present invention includes the steps of: forming a first film on a semiconductor substrate on which a gate electrode is formed; and covering an area other than the top surface of a convex portion of the first film with a resist film. etching the first film using the resist film as a mask to form an opening in the first film so that the upper surface of the gate electrode and at least a part of the side surfaces of the gate electrode are exposed; After removing the first film by etching, remove the resist film and apply the second film to the entire surface.
li process, and etching the second film to expose the gate electrode and the upper surface of the first film, leaving the second film only on the sides of the gate electrode, and selectively removing the first film. The method includes a step of depositing a conductive film on the upper surface of the gate electrode and the side walls of the gate electrode to form an upper gate layer.

[Effect]

In this invention, since a metal film having the same structure as the source/drain electrode can be deposited on the gate electrode, the gate resistance can be significantly reduced.1. Furthermore, since the spacing between the gate electrode and the source and drain electrodes is determined by the width of the gate sidewall, it can be determined with good uniformity and reproducibility, and since they are formed in a self-aligned manner, the spacing can be significantly reduced compared to conventional methods. , the source series resistance can also be lowered. ) Therefore,
Ultra high speed operation^ performance GaAs MESFE'r can be obtained.

〔Example〕

Hereinafter, regarding this invention,
One embodiment of the method for manufacturing T will be described in detail with reference to FIGS. 1(a) to 1(J).

FIGS. 1(a) to (j) are sectional views of main parts showing embodiments of the present invention in the order of steps, and the same arrows as those in FIG. 2 indicate the same or equivalent parts.

First, as shown in FIG. 1(a), an n-type channel layer 2. Gate electrode 3゜low resistance n+
Forms PJ4a and 4b. Note that here, for the sake of subsequent explanation, the thickness of the gate electrode 3 is 1. to, 3p, but it will be clear from the following description that it is not necessarily limited to 0.3-.

Next, as shown in FIG. 1(b), a first film, for example, a silicon nitride film (hereinafter referred to as SiN film) 6, is applied to the entire surface with a thickness of 0.
．． Deposit at 3 μm. This deposition method has a desired step coverage property, and for example, plasma CVD method can be selected. In case B, the upward SiN gland 6 completely covers the step of the gate electrode 3, and the height of the convex portion of the SIN film 6 is 0.3 g.

The width is 0.24 m longer on one side than the width of the gate electrode 3. However, this length of 0.2 μm is variable to some extent depending on the deposition conditions of the SiN film 6.
As shown in Figure (C), the surface is made flat by applying a coating film, such as a photoresist. Next, Figure 1 (
As shown in d), the upper surface of the convex portion of the photoresist SiN film 6 is exposed by 02 plasma etching or the like. Next, Figure 1 (
As shown in e), the remaining photoresist films 7a, 7
SiNfi6 isotropically using b as a mask, for example, CF
Etching is performed by plasma etching using 4 gases. However, this etching must be done carefully. This is because, as shown in FIG. 1(e), since the etching is isotropic, the etching of the SiN film 6 is caused by the remaining b
t also advances in the lateral force direction toward the F portion of the photoresist films 7a and 7b (this is called an undercut), but as will be clear from the later explanation, the amount of undercut causes the
This is because the distance between the 1i pole 3 and the source/drain electrode is determined. In reality, in order to execute this process at the production level, for example, the following methods can be considered.

As is well known, in dry etching technology, the types of molecules and radicals present in the etching gas can be determined by monitoring the light emitted by plasma (this is generally called emission spectroscopy).

It is possible to obtain a certain degree of knowledge regarding the amount, and in fact, it is often used as a method for detecting the end point of etching. In the example given here, since CF4 gas is used for etching the SiN film 6, it is effective to monitor the emission intensity of fluorine radicals at 704 m, for example.

Changes in emission intensity will be explained using FIG. 3 as an example.

As etching progresses from the state shown in Figure 1(d), S
Fluorine radicals, which are etching species, are consumed in the exposed portion of the iN film 6, and the emission intensity is low (during °l-1 in FIG. 3). However, when the top surface of the SiN film 6 reaches the same height as the top surface of the gate electrode 3 (t, in FIG. 3), 3iN M! j! 60 The surface area rapidly decreases and the luminescence intensity rapidly increases, making it possible to detect point B. Since undercutting of the SiN film 6 starts at this point, the amount of undercutting is determined depending on how long etching is continued after this, but at the time t2 when the predetermined time 'r2 has elapsed. If the etching is finished at , the desired amount of undercut can be obtained. The time ゛l'2 is determined experimentally in advance, and in order to cope with fluctuations in the etching rate due to the conditions of the etching equipment and the total exposed area of the SiN film on the substrate to be processed, it must be determined in advance of the actual etching process. An effective method is to keep the relationship with the obtained time T constant, that is, to obtain a constant α of T2/1°□−a, and then determine T2 on the spot.

The state shown in FIG. 1(e) is that the remaining SiN films 6a, 6b are removed by the above method.
If the amount of amperage under b is, for example, 0, 1 am
It has been processed to become. Next, by applying anisotropic etching such as reactive ion etching, the SiN films 6a and 6b on both sides of the gate electrode 3 can be removed into a shape as shown in FIG. 1(f). , during anisotropic etching, the above-mentioned undercut remains unchanged at all. Photoresist film 7a.

7b is then removed with gold. Next, as shown in FIG. 1(g), the second film, a 5OG (spin-on-glass) film (for example, OCI manufactured by Tokyo Ohka Co., Ltd.), is heat-treated to form a silicon oxide film. spin) 8 to 1-1. , the outermost surface is flattened by applying appropriate heat treatment. Furthermore, as shown in FIG. 1(h), the upper surfaces of the gate electrode 3 and 5iNIII 25a, 6b are exposed by etching the entire surface, for example, plasma etching. Etching can be stopped at this point using the above-mentioned emission spectroscopic analysis method. Next, as shown in FIG. 1(i), the SOG films 8a and 8b remaining on both sides of the gate electrode 3 are not etched and are etched with SiN.
If only the 1pcj 5ap6b is etched using a method such as wet etching using a phosphoric acid solution, the SOG films 8u and 8bl will remain as the side walls of the gate electrode 3, and their shape will be as shown in FIG. 1(i). It has an overhanging shape. 1. Next, as shown in FIG. 1(j), a material that makes ohmic contact with n-type GaAs, such as AuGe,
Ni and Au are sequentially deposited by vacuum evaporation. Source and drain electrodes 5a, 5b are formed on the low fLW anti-n+ layers 4a, 4b, and at the same time AuGe/Ni/Au#! is deposited to form the upper gate layer 9. In this way, the desired GaAs MESFET can be manufactured.

The GaAs MESFE 'l' obtained as described above has a high mutual conductance r; rm6! due to the gate/n+ cell line technology. Since it is possible to provide a low-resistance metal film on the relatively high-resistance 1)1 melting point gate in a maintained state, the overall gate resistance can be suppressed to a sufficiently low level, and such GaAs MES
FETs exhibit good operating characteristics even in high frequency ranges.

In this example, the SiN film 6 is etched sequentially into isotropic and anisotropic etches, and using the processed IR, the SOG film (here, The most distinctive feature lies in the shape of the sidewall (8), which is a silicon oxide film. Since the low resistance layer above the gate electrode 3 and the ohmic electrode are simultaneously formed using this side wall, a sufficient overhang shape is reliably realized. That is, because of this shape, there is no fear that the low wind resistance layer above the gate electrode 3 and the ohmic electrode will come into electrical contact.

Furthermore, as already explained, the distance between the gate electrode 3 and the ohmic electrode is 0.0.
The current time can be kept as small as 3 μs, which helps reduce the source series resistance (1).

In addition, according to the conventional photolithography technique, the ohmic electrode is placed close to the gate electrode 3 in this way, and
It has always been difficult to arrange them so that they do not touch each other, considering reproducibility.

It should be noted that the various types and configurations used in the above embodiments are not limited to these, but the selection ratio in the etching apparatus can be secured to 3 to 4V, which can realize the process described in the first embodiment. It goes without saying that if you can get a combination, put it in place.''

Further, the substrate material is not limited to GaAs, and the gate structure does not need to be an MS structure.

Furthermore, in the above embodiment, the case where the low resistance n+ layers da, 4b have already been formed in the process of forming the upper gate electrode 3 is taken up, but it is not necessary to form the low resistance n+ layers da, 4b. In some cases, there is no low resistance n during this process.
It is also possible to form + layers 4a, 4b.

Further, the Fll:T structure does not need to be of the gate/n'' self-aligned type.

〔Effect of the invention〕

As explained above, the present invention is applicable to game 1. a step of forming a first film on the semiconductor substrate on which the tr2 pole is formed; a step of imiming the first film with a resist film other than the top surface of the convex portion; etching to provide an opening in the first film so that the upper surface of the gate electrode and at least a part of the side surfaces of the gate electrode are exposed; and after removing the first film on the sides of the gate electrode by etching, A process of removing the resist film and applying a second film to the entire surface, etching the second film, exposing the upper surface of the gate electrode and the first crotch, and applying the second film to the gate 1/electrode side. A step of selectively removing the first layer while leaving only the first layer on the upper surface of the gate electrode, and a step of depositing a conductive film on the upper surface of the electrode and the side wall of the gate electrode to form the upper gate layer. It consists of dimensions.

By using gate sidewalls with well-controlled shapes, it is possible to form an upper gate layer with low resistivity on the top of the gate without fear of contact with the source/drain electrodes. It is possible to reduce the resistance and obtain F'E '1'' with excellent high frequency operating characteristics.J

[Brief explanation of the drawing]

1(a) to 1(j) show important parts of an embodiment of the method for manufacturing a semiconductor device of the present invention, in which 1 is a semi-insulating GaAs substrate, 2 is an n-type channel; layer,
3 is a gate electrode, 4a, db are low Jt (anti-n+ layers, 5
a, 5b are source/drain electrodes, 6.6a,
6b is 5iNlpJ, 7, 7a, and 7b are 1-resist 1) 53, 8, 8a, and 8b are SOG lq, and 9 is an upper gate layer. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1! , photoresist layer Fig. 1 4a 4b Fig. 1 4a 4b

Claims (5)

[Claims] (1) A step of forming a first film on a semiconductor substrate on which a gate electrode is formed, a step of covering an area other than the upper convex portion of the first film with a resist film, and using the resist film as a mask. etching the first film to provide an opening in the first film so that an upper surface of the gate electrode and at least a part of the side surfaces of the gate electrode are exposed; After removing the first film by etching, removing the resist film and applying a second film on the entire surface, etching the second film and removing the top surface of the gate electrode and the first film. is exposed so that the second film remains only on the side of the gate electrode, and the second film is selectively exposed to the first film.
removing the film to form a gate electrode sidewall; depositing a conductive film on the upper surface of the gate electrode and the gate electrode sidewall;
A method of manufacturing a semiconductor device, comprising the step of forming an upper gate layer. (2) The method for manufacturing a semiconductor device according to claim (1), wherein the second film is a coating film. (3) The method for manufacturing a semiconductor device according to claim (2), wherein the coating film is spin-on glass. (4) The first film is etched isotropically to form an opening so that at least a part of the side surface of the gate electrode is exposed, and then anisotropically etched to expose the side surface of the gate electrode. A method for manufacturing a semiconductor device according to claim (1), characterized in that the method is carried out according to the method described in claim (1). (5) The conductive film is made of a material that can form an ohmic contact with the semiconductor substrate, and by depositing the conductive film, a source electrode and a drain electrode are formed simultaneously with the upper gate layer. A method for manufacturing a semiconductor device according to claim (1).