JPS63285025A - 3-state output circuit - Google Patents

Abstract

PURPOSE:To obtain an economical 3-state output circuit whose instruction execution time is ended at medium speed by using a series connection comprising a p-channel MISFET and 2 n-channel MISFETs for an output circuit, and using a switch circuit for a logic circuit. CONSTITUTION:A logic circuit 21c consists of a switch circuit S and a 1st p-channel MISFET P1 whose gate is connected to a control signal terminal 2, whose source is connected to a power terminal 4 and whose drain is connected to a node N1. An output terminal 22c consists of a 2nd p-channel MISFET whose gate is connected to the node N1, whose source is connected to a power terminal 4, the 1st n-channel MISFET Q1 whose gate receives a control signal V1, whose drain is connected to the drain of the FET P2, the 2nd n-channel MISFET Q3 whose gate receives a voltage VN1 at the node N1, whose drain is connected to the source of the FET Q1 and whose source is connected to ground and an output terminal 3 connected to a node N2.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a three-state output circuit.

[Conventional technology]

In general, three-state output circuits are used as bus drive circuits because they have advantages such as being able to connect a plurality of gate output circuits at the same time and having extremely low leakage current in a high impedance state.

FIG. 3 is a circuit diagram of a first example of a conventional three-state output circuit.9 This three-state output circuit 20. are a logic circuit 21 and an output circuit 22 . It is composed of

The logic circuit 213 receives the data signal ■1 of the data signal terminal 1.
as an input, an inverter 6 that gives an output signal to the fifth node N5, and a control signal 2 of the control signal terminal 2 as input,
The inverter 5 provides an output signal to the sixth node N6.

Further, the output circuit 21. , connect the source side to power terminal 4 (!l
Through the third and fourth p-channel MISFETs P and P4, two of which are connected in series, and the ninth node N9, which is connected to the output terminal 3, two MISFETs are connected with the source side facing the ground point. a third and a fourth n-channel M connected in series;
Total of 4 MISFETs with ISFET Q3 and Q4
It is constructed by connecting in series.

Here, logic circuit 21. to the output circuit 22. The fifth to eighth nodes N5 to N8 on the signal path to M
ISFET P3, P4 and MISF
It is connected correspondingly to the gates of ET Q3 and Q4.

Next, the operation of this three-state output circuit 203 will be explained.

FIG. 4 is a signal waveform diagram of each part for explaining the operation of the circuit of FIG. 3.

During the period t1 to t5, when a high level H or low level L signal is applied to the data signal terminal 1 and the control signal terminal 2, voltages shown as VN5 to ■N8 appear at the nodes N5 to N8, respectively.

First, the control signal V2 is at a low level and passes through a certain period +j3.
At +j5, the two FETs P4 and Q that sandwich the node N9 are in the off state at the same time, so the voltage VN9 appearing at the node N9, that is, the output signal ■3, is such that both FETs are in a high impedance state as shown by the dotted line. Therefore, the voltage is divided by the leakage current ratio.

Next, both the control signal V2 and the data signal ■1 are at high level H.
During period t2, the two FETs above node N9
Both P and P4 are on, and the lower FETQ
4 is in the off state, so the output signal V3 becomes high level H.

During the period t4 when the control signal ■2 is at a high level H and the data signal V1 is at a low level, the two Fs above the node N9
ET Q3 and Q4 are both on, and the lower F
Since ETP is in the off state, the output signal 3 becomes a low level L.

Therefore, the output terminal 3 outputs the data signal V1 and the control signal V2.
Depending on the combination of signals, one of the three states of high level H, low level L, and high impedance is indicated.

FIG. 5 is a circuit diagram of a second example of a conventional three-state output circuit.

The logic circuit 21b receives the data signal (1) and the control signal (2) as input, and has an output terminal connected to the tenth node NIO.
D circuit 10 and inverter 7 which receives control signal 2 as input
It consists of a NOR circuit 11 which inputs the output of and data signal 1 and whose output terminal is connected to the eleventh node Nll.

The output circuit 22b is a fifth p-channel M whose source is connected to the power supply terminal 4 and whose drain is connected to the twelfth node N1□.
ISFET p5 and a fifth n-channel MISFET whose source is grounded and whose drain is connected to node N12.
It consists of two series circuits with TQ5.

Note that the output terminal 3 is connected to the node NI2.

Next, the operation of this three-state output circuit will be explained.

FIG. 6 is a signal waveform diagram of each part for explaining the operation of the circuit of FIG. 5.

When signal waveforms as shown in FIG. 6 are given as the data signal (1) and control signal (2) during the period tl to t5,
As the output of the logic circuit 21b, the voltages VNIO and VNII of the nodes NIO and Nll are applied to the FETs P and Q5.
input into the gate. As a result, the output signal V3 has the waveform shown in FIG.

Here, the data signal Vl, the control signal ■2, and the output signal ■3
The three waveforms shown in FIG. 4 are the same as those shown in FIG.

However, when the output signal V of the output circuit 22b is at either the high level H or the low level L, the point where only one FET above or below the node N12 is in the on state is the third point. This is different from the case of the output circuit 228 shown in the figure.

[Problem that the invention seeks to solve]

Among the conventional three-state output circuits described above, in the case of the first example, the logic circuit 21. The number of elements in the inverter 6 is as small as 4, and in a design in which the data signal 2 is an inverted input, two elements of the inverter 6 can be omitted, which is economical.
．． has a large number of MISFETs, the series on-resistance of the MISFETs at high level H and low level L is large, and the output impedance when looking at the output terminal 3 side from the load side is high.
Coupled with the capacitance present in the load bus, this will degrade the pulse response characteristics, so generally the pulse width of control signal ■2 is 1.
There is a problem that the application is limited to small-scale ICs with a slow instruction execution time longer than μs and a small number of parallel 3-state output circuits.

Generally, the on-resistance of an n-channel MISFET is determined by the difference in carrier movement behavior.
Due to the large value of about twice the on-resistance of ISFET, especially the high level H at which FETs P3 and P4 are in the on-state.
The pulse response characteristics are poor in the case of

Furthermore, even if the dimensions of the n-channel MISFET element design are increased in order to balance the on-resistance value of the n-channel MISFET, the on-resistance will be improved, but at the same time, the capacitance of the element will increase. Pulse response characteristics are hardly improved, and the cost increases due to an increase in chip area.

Next, in the case of the 3-state output circuit 20b of the second example, the output circuit 22b has a small element configuration with two MISFETs, the output impedance is halved, the pulse response characteristic is improved, and the pulse width of the control signal 2 is reduced. It is suitable for high-speed instruction execution time of 150 ns or less, but on the contrary, it is suitable for logic circuits 21
b is complex and has a large number of elements (10), so when a large number of 1.3 state output circuits are incorporated into an IC, the chip area increases and the cost increases, so there is a problem that its use is limited to high-speed instruction execution times. there were.

The purpose of the present invention is to reduce the output impedance by using an output circuit with a simple logic circuit, a small number of elements, and a single n-channel MISFET with high on-resistance, and to achieve an economical and medium-speed instruction execution time. The object of the present invention is to provide a 3-state output circuit.

[Means for solving problems]

The three-state output circuit of the present invention has the following features: (A) The input side is connected to the data signal terminal and the control signal terminal, the output side is connected to the first node, and the control signal controls whether to pass or block the data signal. a logic circuit comprising a switch circuit and a first n-channel MISFET that inputs the control signal to the gate, connects the source to the power supply, and connects the drain to the first node; (B) the gate is connected to the first node; a second node connected to the first node to input the data signal and having a source connected to the power source;
The control signal is input to the p-channel MI 5FET and the gate 1, and the drain is connected to the second
The first n-channel MISFET is connected to the drain of the n-channel MISFET, the gate is connected to the first node to input the data signal, and the drain is connected to the source of the first n-channel MISFET. , a second n-channel MI 5FET whose source is grounded, and an output circuit having an output terminal connected to the second node.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. The switch circuit S includes an inverter 9 connected to the data signal terminal 1 on the input side, and an n-channel MISFET whose output end is connected to the first node Nl and whose gate is connected to the control signal terminal 2.
It consists of a series connection with a transmission gate T composed of.

Logic circuit 21. connects this switch circuit S, the gate is connected to the control signal terminal 2, the source is connected to the power supply terminal 4,
and a first n-channel M connecting the drain to the node N.
It is composed of ISFET P.

Output circuit 22. is a second p-channel MISF whose gate is connected to node N1 and whose source is connected to power supply terminal 4.
ET, a first n-channel MISFET Ql whose gate receives the control signal V2 and whose drain is connected to the drain of the FET p2 via the second node N2, whose gate receives the voltage VN1 of the node N1, and whose drain is connected to the drain of the FET p2. is FETQ
a second n-channel M I S F E T Q 2 connected to the source of + and whose source is grounded, and a node N2
and an output terminal 3 connected to the terminal.

Next, this 3-state output circuit 20. Explain the operation.

FIG. 2 is a signal waveform diagram of each part for explaining the operation of the circuit of FIG. 1.

The waveforms of the signals 1 to V3 of the data signal terminal 1, control signal terminal 2, and output terminal 3 during the period t1 to t5 are the same as the waveforms of the first and second examples of the conventional three-state output circuit described above, respectively. are the same.

During a period when the control signal ■2 is at a low level, jl+1, . 1.
Now, since FET Pl is in the on state, the voltage at node N1 is V
H+ becomes a high level H, FET P2 is turned off, and FET Q+ also inputs the voltage N3 of the third node N3 to its gate, and both are turned off, so that the output terminal 3 becomes a high impedance state.

During this period, the transmission gate T cuts off the output of the data signal ``l'' to the node N by the control signal ``2''.

During periods t2 and t4 when the control signal 2 is at a high level H, the transmission gate T is in an on state, and the data signal 2 is at the same level as the voltage at the node N.

Therefore, during the period t2 when the data signal V is at a high level H,
Since the voltage VNI is also at a high level H, FET Pl is turned off, FETs Qs and Ql are both turned on, and the output signal ■3 is also at a high level! (It becomes.

In addition, during the period t4 when both the data signal ■1 and the voltage VN1 are at low level L, FET Pl is in the on state and FET Q2 is in the on state.
turns off, and the output signal v3 also goes to low level L.

This 3-state output circuit 20. FE of the output circuit 22c of
The number of T is 3, and it is a p-channel MIS with high on-resistance.
The FET is one FET Pl, with a small on-resistance n
Channel MI 5FET FET Q, and Ql 2
Since the output impedance of the output terminal 3 at the high level I4 and the low level L state are both balanced with the value of the on-resistance of one p-channel FET, the pulse of the control signal Width is 100~1000ns
Suitable for medium speed bus drive circuits.

At the same time, the number of elements in the logic circuit 22c is also as small as four.

In the above embodiment, the switch circuit S includes the inverter 9 and the transmission gate T, but other switch means may be used. Furthermore, if the logical value of the data signal 1 is reversed, the inverter 9 may be omitted.

〔Effect of the invention〕

As explained above, according to the present invention, the output circuit includes one p-channel MISFET and two n-channel MISFETs.
By using a series connection of T, the output impedance at high and low levels of the output terminal is lowered, and the effect is that medium-speed instruction execution time is possible, which was not possible with conventional low-speed 3-state output circuits. can get.

Furthermore, by simplifying the logic circuit by using a switch circuit, there is an effect of obtaining economical efficiency that could not be achieved with conventional high-speed 3-state output circuits, which had a large number of elements and were expensive.

That is, the pulse width of control signal (2) is 100 to 1000.
This has the effect of providing a 3-stay I/output circuit that is suitable for both performance and economy, such as a medium-speed bus drive circuit with an instruction execution time of ns.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a signal waveform diagram of each part to explain the operation of the circuit of FIG. 1, and FIG. Example circuit diagram, 4th
The figure is a signal waveform diagram of each part to explain the operation of the circuit in Figure 3, Figure 5 is a circuit diagram of a second example of a conventional 3-state output circuit, and Figure 6 is the operation of the circuit in Figure 5. FIG. 3 is a signal waveform diagram of each part for explaining. 1...Data signal terminal, 2...Control signal terminal, 3...
...Output terminal, 4...Power supply terminal, 5-9...Inverter, 1O-NAND circuit, 1l-NOR circuit, 20°-20c...3 stay 1. Output circuit, 213-21°...・Logic circuit, 22. ~22. ...output circuit, N,
~NI2...1st to 12th nodes, P, ~P5...
1st to 5th p-channel MISFET, Q+
~Q,...first to fifth n-channel MISFETs, S
...Switch circuit, T...Transmission gate, t1-t,
...Period, ■1...Data signal, ■2...Control signal, V3...Output signal, VNI~■N! 2...Voltage at node N, 〜〜N1□.

Claims (1)

[Claims] (A) A switch circuit whose input side is connected to a data signal terminal and a control signal terminal, whose output side is connected to a first node, and whose control signal controls whether to pass or block the data signal. , a first p that inputs the control signal to a gate, has a source connected to a power supply, and has a drain connected to the first node.
a logic circuit having a channel MISFET; (B) a second transistor whose gate is connected to the first node to input the data signal and whose source is connected to the power supply;
channel MISFET, the first n-channel MISFET whose gate receives the control signal and whose drain is connected to the drain of the second p-channel MISFET via a second node, and whose gate is connected to the first node. a second n-channel MISFET that is connected to and receives the data signal, whose drain is connected to the source of the first n-channel MISFET, and whose source is grounded; and an output terminal that is connected to the second node. A 3-state output circuit comprising: an output circuit having: