JPS63119324A - Logic circuit - Google Patents

Abstract

PURPOSE:To obtain an IC which is operated at high speed with a low power consumption and has the high degree of integration, by preventing a current from being conducted to a logic circuit in a steady state. CONSTITUTION:A third transistor 28 is set to the conductive state or the cut-off state in accordance with conductive states or cut-off states of a first TRs 20 and 22 due to first input signals A and. A fourth TR 30 is set to the cut-off state or the conductive state in accordance with conductive states or cut-off states of second TRs 24 and 26 due to second input signals, the inverse of A and the inverse of B complementary to first input signals, therefore, a non- inverted output or an inverted output is taken out as the logic output corresponding to first or second input signals. Since a current path is cut off and the current is not conducted in the steady state after the completion of the switching operation, power is not consumed in the steady state, and the degree of integration in the IC is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to logic circuits, and particularly to increasing the speed of logic operations and reducing current consumption.

[Conventional technology]

Conventionally, logic circuits used in GaAs ICs include DC
F L (Direct Coupled PET L
ologic), BFL (Buffered FET)
Logic), etc.

As shown in Figure 3, the DCFL obtains a logical output f by switching FETs 2 and 4 according to the inputs A, B, but has the characteristics of slow operation speed and relatively low power consumption. There is.

In addition, as shown in FIG. 4, the BFL configures an inverter by installing a FET 10 as a common active load for the FET 6.8, and uses the inverter output as a buffer, consisting of an FET 12, a diode 14, and an FET 16. It is taken out through a level shift circuit,
Although it operates faster than DCFL, it consumes a large amount of power.

[Problem that the invention seeks to solve]

By the way, GaAs IC is said to be capable of high-speed operation, but high-speed operation and power consumption are closely related, and with conventional technology, attempting to increase speed increases power consumption, so it is difficult to integrate It has not been possible to increase the efficiency of the technology, and its practical application has been hindered.

Therefore, the present invention provides a logic circuit suitable for GaAs1C that operates at high speed and reduces power consumption.

[Means for solving problems]

The logic circuit of the present invention includes a first transistor (a group of transistors or a single transistor such as FETs 20 and 22 in the embodiment) which becomes conductive or cut-off depending on the first input signal (input signals A and B in the embodiment). a second transistor (1 transistor) which becomes conductive or cut-off depending on a second input signal (input signals τ, T in the embodiment) having a complementary relationship with the first input signal; Example FET24
．． a group of transistors or a single transistor such as 26) and a third transistor connected in series with the first transistor to become conductive in response to a human force applied through the second transistor when the second transistor is conductive. (FET28 in the example) and the first transistor (FET28 in the example) connected in series with the second transistor.
0 or FET22) conducts, the first transistor (
a fourth transistor (FET30 in the embodiment) that becomes conductive in response to an input applied through the FET20 or FET22 that is in a conductive state;
Non-inverting output (Q) or inverting output (Q) depending on the input signal of
100).

[For production]

With this structure, the third transistor becomes conductive or cutoff depending on the conduction or cutoff state of the first transistor caused by the first human input signal, and also has a complementary relationship with respect to the first input signal. The fourth transistor is turned on or off depending on the conduction or cutoff state of the second transistor caused by the second input signal. An inverted output or an inverted output can be taken out.

〔Example〕

FIG. 1 shows an embodiment of the logic circuit of the present invention.

FET forming a transistor group as the first transistor
20 and 22 are connected in parallel with the drain p on the high potential side and the source S on the low potential side, and the first input signals A and B are applied to independent input terminals 32 and 34 of each gate G.

Each of the FETs 20 and 22 is, for example, an enhancement type FET, which becomes conductive when the input signals A and B are at a high level (H) exceeding a threshold potential, and is cut off when the input signals are at a low level (L) below the threshold potential. state.

Further, FETs 24 and 26 are installed as second transistors, and independent input terminals 36 and 38 of each gate have
Second human input signals τ, T (inverted signals of input signals A, B) having a complementary relationship to the first input signals A, B are applied. Each of the FETs 24 and 26 is also configured as an enhancement type FET, and is in a conductive state when the input signal -1 is at a high level (H) exceeding the threshold potential, and the human input signal τ, is below the threshold potential. When it is at a low level (L), it is in a cutoff state.

Then, FET28 is connected in series with FET20 and FET22 as a third transistor, and this FET2B is
When FET24.26 conducts, each FET24.26
It is made conductive by an input applied to the gate through. Further, FET30 is connected in series with FET24 and FET26 as a fourth transistor, and when FET20 or FET22 is conductive, FET30 is connected in series with FET24 and FET26.
It is rendered conductive by an input applied to the gate through FET 20 or FET 22.

Therefore, this logic circuit consists of FET20.22.28
OR circuit configured by and FET24.26.3
0 is paralleled with the NOR circuit configured by 0, and voltage vdd is applied to the power supply terminal 39,
A non-inverted output Q is taken out as a logic output from an output terminal 40 provided on the source side of FETs 20 and 22 (7), and an inverted output 100 is taken out from an output terminal 42 provided on the source side of FET 26.

The logical operation of this logic circuit is shown in Fig. 2 (a) and (b).
Explain with reference to.

Input signals A, B, A, B are applied as logic inputs to input terminals 32.34.36.38, respectively.

As shown in FIG. 2(a), when either of the input signals A and B is at a high potential H or a low potential, one of the FETs 20 and 22 on the H input side becomes conductive (second Figure (a)
(in this case, the FET 20 is in a conductive state and the FET 22 represented by a broken line is in a cut-off state), and when the potential of the common source S of the FET 20.22 becomes a high potential due to the voltage V a a, the non-inverting output Q of the output terminal 40 becomes H. This becomes the output. Then, since the potential of the source S of FET20.22 is applied to the gate G of FET30, FET30 becomes conductive, and the potential of its drain D becomes the ground potential.

At this time, since either input signal A or B is an H input, either input signal τ or ■ becomes an input, and the FE
Either T24 or T26 is in the cut-off state ((a in Figure 2)
), the FET 24 indicated by the broken line is in the cut-off state, and the FET
26 is conducting), but since FETs 24 and 26 are connected in series, unless both are conducting, FET 26
The potential of the source S of is left to the switching operation of the FET 30. Since the FET 30 is in a conductive state due to the H potential of the source S of the FET 20, the potentials of the source S of the FET 26 and the drain D of the FET 30 become the ground potential, and the inverted output of the output terminal 42 becomes an L output. Since the L potential of the source S of the FET 26 is applied to the gate G of the FET 28, the FE
T28 is in the cut-off state, and the non-inverting output Q of the output terminal 40
is maintained in a stable state.

Furthermore, as shown in FIG. 2(b), when input signals A and B both become L, input signals τ and ■ both become H,
As shown by the broken line, both FETs 20 and 22 are in the cut-off state,
Both FETs 24 and 26 become conductive. At this time, F
The potential of the source S of ET26 becomes H potential due to the voltage Vaa, and the FET28 becomes conductive, so the potential of its drain D becomes the ground potential, and the potential of the FET20.22 becomes the ground potential.
Since FET 28 is in a cut-off state, the drain D of FET 28 is disconnected from power supply voltage vdd and becomes reliably at ground potential. The drain D of the FET 28, which is at this ground potential, is F
Since it is connected to the gate G of ET30, FET30
is in a cut-off state. As a result, the non-inverted output Q of the output terminal 40 becomes an L output, and the inverted output i of the output terminal 42 becomes an H output.

For this logical operation, the logical formula is A+B=Q...(1) A-B=A+B=Q...(2) The truth table is shown in Table 1.

Table 1 Therefore, when either logic input A or B is H,
The non-inverting output Q is disconnected from ground potential and connected to FET 20.
At this time, the inverted output is cut off from the power supply voltage Vdd and becomes the ground potential through the FET 30.

Furthermore, when both logic inputs A and B are disconnected, the non-inverting output Q is released from the power supply voltage V (ld) and becomes the ground potential via the conductive FET 28, and the inverting output i is at the ground potential. It is disconnected from the power supply voltage V (Il+) and has a potential due to the power supply voltage V (Il+).

As is clear from the above operation, in this logic circuit, the current path is cut off and no current flows in the steady state after the switching operation is completed, so no power consumption occurs in the steady state, so it is difficult to integrate it into an IC. The degree of integration can be increased.

By the way, the conventional logic circuit shown in FIG. 3 or 4 uses a so-called ratio method in which current flows in a steady state, and in this method, a switching FET, a load, and a FET are used to obtain the necessary logic amplitude. It is necessary to set conditions so that the It was difficult to provide the large current drive capability necessary for this purpose. On the other hand, in the logic circuit of the present invention, no current flows in the steady state, so there is no restriction on the size of the current as in the ratio method.
By providing a sufficiently large current drive capability and a sufficiently large logic amplitude, desired logic operations can be performed, and high-speed switching can be realized even with a large logic load.

In particular, in highly integrated ICs, the capacitance due to wiring becomes large, and the logic circuit is inevitably required to have current drive capability, but the logic circuit of the present invention is not limited in current drive capability. It is extremely useful for realizing highly integrated, high-speed ICs, as it has no power consumption in the steady state and has a sufficiently large current supply capacity during switching. By using the logic circuit of the present invention, it is possible to realize a high-speed, highly integrated IC with low power consumption.

In addition, in the embodiment, two sets of FEs are used as the first transistor.
T20.22, two sets of FETs as the second transistor
24 and 26, each of them may be composed of a single FET, or may be composed of three or more elements.

〔Effect of the invention〕

According to this invention, high-speed logic operation can be realized by high-speed switching, and the current drive capacity can be increased.
There is no current consumption after the logic operation is completed, and low power consumption can be achieved.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the logic circuit of the present invention, Fig. 2 is a circuit diagram showing the operating state of the logic circuit shown in Fig. 1, and Figs. 3 and 4 are circuit diagrams showing a conventional logic circuit. FIG. 20.22...FET (first transistor) 24
．． 26...FET (second transistor) 28...
・FET (third transistor) 30...FET
(Fourth transistor) A, B...First input signal τ, ■...Second input signal Q...Non-inverting output 100...Inverting output 20.22--First transistor 24.26...Second transistor 28...Third transistor Criminal...Fourth transistor Figure 1 Figure 2 (b) Figure

Claims (1)

[Scope of Claims] A first transistor that becomes conductive or cut off in response to a first input signal; and a first transistor that becomes conductive in response to a second input signal that has a complementary relationship to the first input signal. a third transistor that is connected in series with the first transistor and becomes conductive in response to an input applied through the second transistor when the second transistor is conductive; a fourth transistor that is connected in series with the second transistor and becomes conductive in response to an input applied through the first transistor when the first transistor is conductive; A logic circuit that outputs a non-inverted or inverted output.