JPS6328466Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display circuit, and more particularly to an improvement in a display circuit for driving a bar graph display device.

A bar graph display device is a device in which a large number of display segments are arranged in parallel, and when the display is continuously displayed up to the position corresponding to the value of the input signal, it becomes a bar graph display, which corresponds to the value of the input signal. If only the positions that have been set are displayed, a point display similar to a pointer display can be obtained. The display circuit that drives this bar graph display device includes a central processing unit that takes in external information and performs calculations to output display information, and a latch circuit that latches the display information output from this central processing unit. , and a segment decoder that takes in the output of this latch circuit and supplies a decoded signal to each display segment of a bar graph display device is generally used.

However, in the display circuit having the above configuration, since the segment decoder is fixed, the display of the bar graph display device is also fixed to either bar graph display or point display. For example, a bar graph display is suitable for displaying the magnitude of an input signal, and a point display is suitable for displaying a tuning position or the like. Therefore, when using a bar graph display device, if the display mode can be easily changed, the display mode can be switched to the optimum display mode according to the type of input information.
In this case, it is conceivable to provide a bar graph display circuit and a point display circuit in parallel and to select and use both circuits, but this would result in a complicated and expensive circuit.

Furthermore, in the display circuit configured as described above, since display data is output in parallel from the central processing unit, the number of display output ports increases in response to an increase in the maximum number of display segments that can be arranged in parallel. become. As a result, many of the limited number of terminals in the central processing unit integrated into an IC (semiconductor integrated circuit) are used exclusively for outputting display data, and the number of terminals exclusively used for display information is reduced. The problem is that the number of functions of the central processing unit decreases as the number of functions increases.

Therefore, the purpose of the present invention is to use a simple circuit that can be used by switching between a bar graph display and an arbitrary number of point displays, and to always display only three output ports regardless of the increase in displayed information. An object of the present invention is to provide a display circuit that can be used for various purposes.

In order to achieve this purpose, the present invention has a display information output terminal that serially sends out a number of pulses corresponding to the content of display information to the central processing unit, and a clear signal that is sent to the central processing unit prior to the start of sending out the next display information. A bar graph display device is provided with a clear signal output terminal for sending out and a display mode control signal output terminal, and each output of a shift register is provided with display information as a clock input, a clear signal as a clear input, and a display mode control signal as a shift input. is supplied to each display segment. Hereinafter, a display circuit according to the present invention will be explained in detail using embodiments shown in the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a display circuit according to the present invention, which is particularly applied to detect and display the rotational speed of a rotating body. In the figure, 1 is a waveform shaping circuit that shapes into a pulse the rotation detection signal A supplied from a pickup coil (not shown) that magnetically detects a protrusion provided on a part of a rotating body, for example. and is supplied to the central processing unit 2. The CPU 2 counts the signal interval of the rotation detection signal A supplied via the waveform shaping circuit 1 using a clock pulse or the like, and calculates the rotation speed by calculating the counted value. The rotational speed information calculated in this way is outputted as follows by using the output ports P ₁ to _{P 3} of the CPU 2. First, a clear signal B is sent from the output port _P2 , and then a rotation speed signal C of serial pulses corresponding to the rotation speed value as display information is sent from the output port _P1 . In this case, the display mode control signal D is sent out from the output port _P3 in synchronization with the rotational speed signal C. In other words, in the bar graph display mode, the output is always "H" when the rotational speed signal C is sent.
In the point display mode, "H" is output only during the first pulse generation period of the serial pulse train constituting the rotational speed signal C. 3a and 3b are
The rotational speed signal C output from output port P ₁ of CPU 2 is used as clock input CK ₁ and CK ₂ , and the clear signal B output from output port P ₂ is used as clear input.
CL ₁ and CL ₂ are shift registers, and the shift register 3a shifts the display mode control signal D output from the output port P ₃ of the CPU 2 to the shift input IN ₁
and the shift register 3b is the shift register 3a.
By setting the signal shift input IN ₂ to be sent from the final stage output terminal Q ₈ of , the shift input signal is sequentially shifted every time the rotational speed signal C is supplied. 4
is a large number of display segments not shown (in this case
It is a bar graph display device in which 16 units) are arranged in a straight line, and the output signal input terminals IN 1 to IN ₁ are sent out from the respective output terminals Q ₁ to Q ₁₆ of the shift registers 3a and 3b.
It is configured to supply each display segment via IN ₁₆ .

In the display circuit configured in this manner, when the rotating body (not shown) starts to rotate, a pick-up coil (not shown) provided close to the rotating body is activated by a protrusion provided on a part of the rotating body. A rotation detection signal A is generated every time passage is detected. This rotation detection signal A is supplied to the CPU 2 after being shaped into a pulse shape in the waveform shaping circuit 1 .
The CPU 2 sequentially takes in the rotation detection signals A supplied via the waveform shaping circuit 1, and calculates the intervals of the rotation detection signals A by counting them using clock pulses or the like. Then, this rotation detection signal A
Since the interval is related to the rotational speed of the rotating body, the CPU 2 calculates the rotational speed by calculating this count value. The rotational speed signal C calculated in this way is transmitted to the shift registers 3a and 3b.
The data is displayed on the bar graph display device 4 via the CPU 2, and this display is configured to have two modes, bar graph display and point display, which are controlled by the CPU 2. Hereinafter, the operation will be explained separately for the bar graph display mode and the point display mode.

A. Bar graph display mode In the bar graph display mode, the display mode control signal D at the "H" level is constantly output from the output port _P3 of the CPU 2. The rotational speed signal C obtained as described above is output from the output port _P1 , but prior to sending out the rotational speed signal C, the clearing signal shown in FIG. _2a is sent from the output port P2. Signal B is sent out. When clear signal B is generated, soft registers 3a,
3b are both cleared and the outputs sent from each output terminal _Q1 to _Q16 become "L" as shown in FIG. Become. When the shift registers 3a and 3b are cleared in this way, the CPU 2
As shown in FIG. _2b , a rotational speed signal C consisting of a serial pulse train of a number corresponding to the calculated rotational speed is sent from the output port P1 of the shift registers 3a and 3b to the respective clock input terminals CK1, _3b of the shift registers 3a and 3b. CK ₂
supplied to Therefore, shift registers 3a, 3
Input signals b supplied to the shift input terminals IN ₁ and IN ₂ are taken in and sequentially shifted up every time the rotational speed signal C of the serial pulse train is supplied.

That is, in the bar graph display mode, the display mode control signal D at the "H" level is always sent out from the output port _P3 of the CPU 2, as described above. Therefore, the shift input IN ₁ of the shift register 3a will always remain in the "H" state,
When the first pulse of the rotational speed signal C shown in _FIG . ₁ sends out the "H" signal shown in FIG. 2c. Next, when the second pulse of the rotational speed signal C is generated, the shift register 3a
In order to shift up the "H" signal supplied to the shift input terminal _IN1 , the output of the output terminal _Q2 also becomes "H" as shown in FIG. 2d. In this way,
Every time each pulse of the rotational speed signal C represented by a serial pulse train is supplied, the "H" signal is sequentially shifted as shown in _{FIG .} A continuous "H" signal is output.

On the other hand, the shift register 3b also sequentially takes in and shifts up the shift input supplied to the shift input terminal _IN2 every time each pulse of the rotational speed signal C is sent out. Since is the final stage output of the shift register 3a, the output signals sent from each output terminal _Q9 to _Q16 will continue to be in the "L" state at the time of clearing until the previous stage shift register 3a is fully up. Become. Then, when the eighth pulse of the rotational speed signal C is generated and the shift register 3a becomes a full shift, the "H" signal sent from the output terminal _Q8 is supplied to the shift input terminal _IN2 of the shift register 3b. Become. Therefore, in the circuit configured as described above, the outputs of the shift registers 3a and 3b are continuously and sequentially changed to the "H" signal up to the position corresponding to the number of serial pulses of the rotational speed signal C output from the CPU 2. Along with this, the display on the bar graph display device 4 also changes from the shift register 3.
The number of "H" signal shift outputs of a and 3b, that is, the number corresponding to the number of serial pulses constituting the rotational speed signal C, are sequentially and continuously displayed, and the rotational speed of the rotating body is displayed as a bar graph. In this case, the display on the bar graph display device 4 is based on the shift register 3.
The pulse period of the serial pulse train constituting the rotation speed signal C is sequentially increased and displayed in response to the shift up operation of the rotation speed signal C in the shift registers 3a and 3b.
By raising it within the operating range of 3b, one bar graph is displayed almost simultaneously.

Next, the CPU 2 updates the rotational speed signal C at a predetermined period, and at the time of updating, as in the case described above, after the clear signal B is generated, the rotational speed signal C is updated by the number of pulses in the serial pulse train. A rotational speed signal C is generated. Therefore, the bar graph display on the bar graph display device 4 is as follows.
Although it is constantly rewritten in accordance with the update cycle in the CPU 2, as described above, by accelerating the pulse cycle of the serial pulse that constitutes the rotational speed signal C, the shift registers 3a, 3
The operation of b becomes instantaneous, and as a result, flickering in the refresh display can be almost eliminated, making it as if the rotational fluctuation of the rotating body were being displayed changing at the update cycle of the rotational speed signal C. It will be displayed. In the device configured as described above, since the rotational speed signal C is composed of a serial pulse train and is sent out from the output port _P1 , shift registers 3a and 3b are used.
By increasing the number of cascade connections and the number of parallel segments in the bar graph display device 4, the display range can be freely expanded.

B Point display mode In point display mode, display mode control signal D output from output port _P3 of CPU2
is generated synchronously only when the first pulse of the rotational speed signal C is generated. In other words, in point display mode, the output port of CPU2 is first
A clear signal B shown in FIG. 3a is generated from _P2 , and the shift registers 3a and 3b are cleared. When the clearing of the shift registers 3a and 3b is completed in this way, the rotational speed signal C, which indicates the value according to the number of pulses of the serial pulse train, is output from the output port _P1 of the CPU 2 as in the case of the bar graph display described above. The output is as shown in Figure 3b. In this case, the CPU 2 outputs a display mode control signal D for the point display mode which becomes "H" only in synchronization with the first pulse of the rotational speed signal C, as shown in FIG. 3c, from its output port _P3 . Ru. Therefore, when the first pulse of the rotational speed signal C is generated, the shift register 3a takes in the "H" signal of the display mode control signal D supplied to the shift input terminal _IN1 and shifts it. As shown in FIG. 3d, an "H" signal is output only from the output terminal _Q1 . next,
When the second pulse of the rotational speed signal C is generated, the shift register 3a takes in the display mode control signal D supplied to the shift input terminal _IN1 and sequentially shifts it. However, at the time when the second pulse of the rotation speed signal C is generated, the display mode control signal D is "L" as shown in FIG. 3c, so this "L" signal is taken in. As a result, the output signals output from the output terminals Q ₁ and Q ₂ are "L" and "L" as shown in Fig. 3d and e.
It becomes “H”. As described above, the display mode control signal D supplied to the shift input terminal IN ₁ is applied only when the rotation speed signal C starts generating (when the first pulse is generated). Each time a pulse is generated, an "L" signal is taken in and sequentially shifted up, and "H" signals are output from the output terminals _Q1 to _Q8 of the shift register 3a as shown in FIG. 3d to k. It is shifted up each time each pulse of the rotational speed signal C is generated.
On the other hand, the shift register 3b also _sequentially takes in and shifts up the shift input supplied to the shift input terminal _IN2 every time each pulse of the rotational speed signal C is generated. Since the output of the final stage output terminal _Q8 of the shift register 3a is "L" under normal conditions,
The shift register 3b takes in this "L" signal and shifts it, and the output terminals _Q9 to _Q16 maintain the "L" state at the time of reset. When the output terminal _Q8 of the shift register 3a becomes "H" with the generation of the eighth pulse, this "H" signal is supplied to the shift input terminal _IN2 of the shift register 3b. Therefore, when the ninth pulse of the rotational speed signal C is generated, this "H" level shift input is taken in and shifted, so that only the output terminal _Q9 of the shift register 3b is input as shown in FIG. The output shown in is sent out, and the output of the output terminal _Q8 of the shift register 3a becomes "L" again. As a result, the shift register 3b outputs the final stage output terminal _Q8 of the shift register 3a every time a pulse of the rotational speed signal C is generated.
In order to sequentially take in and shift the "L" level shift signals supplied to the shift input terminal _IN2 from the output terminals Q9 to Q16, one "H" signal is outputted from the output terminals _Q9 to _Q16 as shown in FIG. ``Outputs will be generated in a state in which the outputs move up in sequence. The shift operation of this "H" signal is stopped when the pulse of the rotational speed signal C stops. As a result, the shift registers 3a and 3b receive the rotational speed signal C.
The state in which the "H" signal is shifted to the output stage corresponding to the number of pulses continues to be maintained. Therefore,
In this way, the bar graph display device 4, which receives the outputs of the shift registers 3a and 3b whose one "H" output terminal is sequentially shifted up, displays one display segment in response to the movement of the "H" signal. The value corresponding to the rotational speed signal C is displayed as a point by lighting and moving and then stopping. In this case, the point display will light up and move, but by accelerating the pulse cycle of the rotational speed signal C, the point display will instantly move to a predetermined position, and the eye characteristics and display segment The movement of the lighting becomes almost invisible due to the delay in the occurrence of .

Next, the CPU 2 updates the rotational speed signal C at a predetermined period, as in the case of the bar graph display mode described above, and at the time of this update, the clear signal B is updated as in the case described above. After generation, a rotational speed signal C is generated which is represented by the number of pulses of the serial pulse train. Therefore, the point display on the bar graph display device 4 is as follows:
Although it is constantly rewritten in accordance with the update cycle in the CPU 2, as described above, by accelerating the pulse cycle of the serial pulse that constitutes the rotational speed signal C, the shift registers 3a, 3
The operation of b becomes instantaneous, and the flickering of the point display in the refresh display can be almost eliminated, as if the rotational fluctuation of the rotating body were being displayed changing at the update cycle of the rotational speed signal C. will be displayed.

Therefore, in the display circuit configured in this way, the software of CPU2 must be changed to output port _P3.
By simply switching the display mode control signal D supplied to the shift input terminal _IN1 of the shift register 3a, the bar graph display and point display can be easily changed. Furthermore, since the display information is supplied as a serial pulse train from the output port _P1 of the CPU 2 to the shift registers 3a and 3b, the display range can be expanded without being affected by the number of output ports.

In the above embodiment, a case has been described in which point display is performed by supplying an "H" signal to only one display segment, but the present invention is not limited to this. No, 2
~3 display segments may be displayed consecutively to widen the range of point display. In this case, the first pulse train of the serial pulse train constituting the display information is
It is sufficient to generate a display mode control signal that becomes "H" during a predetermined number of consecutive pulse periods including the th pulse period.

Furthermore, since the shift register sequentially takes in and shifts shift input signals at the active level, each output terminal of this shift register generates a parallel output that is latched for approximately one update period. That will happen. As a result, the output of the shift register can be directly supplied to the bar graph display device, which eliminates the need to provide a latch circuit between the shift register and the bar graph display device, simplifying the circuit. It will be possible to achieve this.

As explained above, according to the display circuit according to the present invention, although the circuit configuration is simple, the display of the bar graph display device can be easily switched between the bar graph display and an arbitrary number of points. Along with this, the bar graph display device can be multi-functional. Furthermore, according to the present invention, the number of output ports of the CPU (central processing unit) is not affected by the expansion of the display range, and any amount of display can be performed by exclusively using three output ports. I can do it. In addition, since the shift register sequentially takes in and shifts the shift input signal at the active level, from each output terminal of this shift register,
A latched parallel output is generated for approximately one update period. As a result, the output of the shift register can be directly supplied to the bar graph display device, which eliminates the need to provide a latch circuit between the shift register and the bar graph display device, simplifying the circuit. It has various excellent effects such as the ability to achieve

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a display circuit according to the present invention, and FIGS. 2 a to 3 a to 3 a to n are operation waveform diagrams of each part of the circuit shown in FIG. 1. 1... Waveform shaping circuit, 2... Central processing unit (CPU), 3a, 3b... Shift register, 4...
...Bar graph display device.

Claims (1)

[Claims for Utility Model Registration] (1) Display information represented by the number of pulses of a serial pulse train is generated from a first output port in response to a predetermined update cycle, and the display information is sent out. a central processing unit that generates a clear signal from a second output port and a display mode control signal from a third output port immediately before the display, and a serial pulse train that is reset by the clear signal and configures the display information. a shift register section that takes in the display mode control signal as a shift input and sequentially shifts the display mode control signal according to each pulse; and a bar graph in which a plurality of display segments each driven by each output of the shift register section are arranged in parallel. a display device, the display mode control signal is at an active level during the transmission period of the display information in the bar graph display mode, and is at the active level during the transmission period of the display information in the point display mode. A display circuit constituted by a signal that is at an active level only during a predetermined continuous pulse period including at least the first pulse of a serial pulse train constituting the display circuit. (2) The display circuit according to claim 1, wherein the central processing unit is unified by a semiconductor integrated circuit, so that the number of output terminals is limited.