JPS6328467Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display circuit, and more particularly to an improvement in a display circuit for driving a bar graph display device.

A bar graph display device is a device in which a large number of display segments are arranged in parallel, and when the display is continuously displayed up to the position corresponding to the value of the input signal, it becomes a bar graph display, which corresponds to the value of the input signal. If only the positions that have been set are displayed, a point display similar to a pointer display can be obtained. The display circuit that drives this bar graph display device includes a central processing unit that outputs display information by taking in external information and calculating it, and a latch circuit that latches display information output from this central processing unit. , and a segment decoder that takes in the output of this latch circuit and supplies a decoded signal to each display segment of a bar graph display device is generally used.

However, in the display circuit with the above configuration, since the display data is output in parallel from the central processing circuit, the number of display output ports of the central processing unit increases as the display amount increases. . As a result, most of the limited number of terminals in the central processing unit integrated with an IC (semiconductor integrated circuit) are used for outputting display data, resulting in an increase in the number of terminals for displaying information. The problem is that the number of functions of the central processing unit decreases as the number of functions increases.

Furthermore, in the display circuit having the above configuration, since the segment decoder is fixed, the display on the bar graph display device is fixed to either bar graph display or point display. For example, a bar graph display is suitable for displaying the magnitude of an input signal, and a point display is suitable for displaying a tuning position or the like. Therefore, when using a bar graph display device, if the display mode can be easily changed, the display mode can be switched to the optimum display mode according to the type of input information. In this case, it is conceivable to provide a bar graph display circuit and a point display circuit in parallel and to select and use both circuits, but this would result in a complicated and expensive circuit.

To solve this problem, the applicant has proposed a two-mode display type that can switch between bar graph display and point display by exclusively occupying only three output ports of the central processing unit. A display circuit has been proposed. This display circuit outputs display information represented by the number of pulses of a serial pulse train from a first output port of the central processing unit in accordance with a predetermined update cycle, and immediately before the display information is sent out. A clear signal is sent out from the second output port, and a display mode control signal is sent out from the third output port to be supplied to the shift register section in which the shift registers are cascaded. After the shift register section is cleared by the clear signal, the display mode control signal is input as a shift input, and each time a pulse of the serial pulse train that constitutes the display information is supplied, it takes in the pulses of the serial pulse train and shifts them sequentially, and each output of this shift register section is supplied to each display segment of the bar graph display device for display. By constantly setting the display mode control signal to an active level, the active signal is sequentially shifted to a position corresponding to the display information and output, resulting in a bar graph display. Furthermore, if the display mode control signal is set to the active mode only during the first pulse generation period of the serial pulse train that constitutes the display information, the output of the shift register section, which is active at only one location, will be sequentially shifted to the position corresponding to the display information. Accordingly, a point is displayed on the bar graph display section at a position corresponding to the displayed information.

However, although the display circuit with the above configuration has various features such as having a small number of display output ports to the central processing unit and being able to perform two types of display, bar graph display and point display, when updating the display information, all displays are displayed. Since the display segment must be shifted up sequentially from the first display segment after the segments are turned off, the time it takes for the display to go off when updating the display information becomes longer, and this problem increases as the amount of display increases. are doing.

Therefore, an object of the present invention is to provide a display circuit which can perform two types of display, a bar graph display and an arbitrary number of point displays, and which can shorten the turn-off time when updating display information. Hereinafter, one embodiment of the display circuit according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a display circuit according to the present invention, which is particularly applied to detecting and displaying the rotational speed of a rotating body. In the figure, 1 is a waveform shaping circuit that shapes into a pulse the rotation detection signal A supplied from a pickup coil (not shown) that magnetically detects a protrusion provided on a part of a rotating body, for example. and supplies it to a central processing unit (hereinafter referred to as CPU) 2. The CPU 2 counts the signal interval of the rotation detection signal A supplied via the waveform shaping circuit 1 using a clock pulse or the like, and calculates the rotation speed by calculating the counted value.

In this case, the CPU 2 has an output port _P1 that sends out the display mode control signal B, and an output port that sends out the rotational speed signal C as display information as a signal expressed by the number of pulses of a serial pulse train.
P ₂ and output ports P ₃ to _{P 6} that send out independent clear signals D ₁ to _{D 4} to respective shift registers to be described later. 3a to 3d are shift registers, which are output ports _P2 of CPU2.
The rotational speed signals C sent out from the ports are respectively clock inputs CK ₁ to CK ₄ , and the clear signals D ₁ to D ₄ output from the output ports P ₃ to _{P 6} are respectively cleared inputs CL ₁ to _{CL 6} . shift register 3
a uses the display mode control signal B sent from the output port _P1 of the CPU 2 as a shift input IN ₁ , and shift registers 3b to 3d sequentially input the final stage outputs of the previous shift registers as shift inputs IN ₂ to IN 1, respectively.
By setting IN ₄ , they are connected in cascade to form a shift register section. Reference numeral 4 denotes a bar graph display device in which a large number of display segments (32 in this case) (not shown) are arranged in a straight line, and output signals are sent from output terminals Q ₁ to _{Q 32} of shift registers 3 a to 3 d. is configured to be supplied to each display segment via input terminals IN ₁ to IN ₃₂ .

In the display circuit configured in this manner, when the rotating body (not shown) starts to rotate, a pick-up coil (not shown) provided close to the rotating body is activated by a protrusion provided on a part of the rotating body. A rotation detection signal A is generated every time passage is detected. This rotation detection signal A is supplied to the CPU 2 after being shaped into a pulse in the waveform shaping circuit 1 . CPU
2 is calculated by sequentially taking in the rotation detection signals A supplied through the waveform shaping circuit 1 and counting the intervals of the rotation signals A using clock pulses or the like. Since the interval of this rotation detection signal A is related to the rotation speed of the rotating body, the CPU 2
calculates the rotation speed by calculating the count value.

The rotational speed signal C obtained in this manner is displayed on the bar graph display device 4 via the shift registers 3a to 3d. It is configured to be controlled accordingly. Hereinafter, the operation will be explained separately for the bar graph display mode and the point display mode.

A. Bar graph display mode In the bar graph display mode, an "H" level display mode control signal B is constantly output from the output port _P1 of the CPU 2. The rotational speed signal C obtained as described above is output from the output port _P2 , but prior to sending out the rotational speed signal C, a clear signal _D1 is sent from the output port _P3 to the second output port. It is sent out as shown in Figure a. When the clear signal _D1 is generated, only the shift register 3a is cleared and the outputs sent from each output terminal _Q1 to _Q8 all become "L" as shown in FIG. 2 _d1 to _d8 . Along with this, eight display segments to which the shift register 3a of the bar graph display device 4 is connected become non-displayed. In this way, when the clearing of the first stage shift register 3a is completed, a rotational speed signal C consisting of a serial pulse train of a number corresponding to the calculated rotational speed is output from the output port _P2 of the CPU 2 as shown in FIG. 2b. is sent to the clock input terminal of shift register 3a.
Supplied to CK ₁ . The shift register 3a takes in the always "H" level display mode control signal B, shown in _FIG . That will happen. Therefore, from each output terminal _Q1 to _Q8 of the shift register 3a, "H" signals are sequentially shifted up and outputted in a continuous state as shown in FIG. 2 _d1 to _d8 , Along with this, the bar graph display device 4
Also in the display, the continuously lit portion of the display segment extends from the lower digit to the upper digit. Then, when the seventh pulse of the rotational speed signal C is generated, that is, just before the "H" signal is shifted to the final output stage of the shift register 3a, a clear signal _D2 is generated from the CPU 2, and the shift register 3b is cleared. Therefore, the signals sent out from the output terminals Q ₉ to Q ₁₆ of the shift register 3b are surely "L" as shown in FIG. 2 f ₁ to f ₈ . In addition, since the shift register 3b uses the final stage output of the previous stage shift register 3a as a shift input, the cleared "L" of the final stage of the shift register 3a during the first to seventh pulse generation period of the rotational speed signal C. By sequentially shifting the signals, the outputs of the respective output terminals _Q1 to _Q7 are set to "L". Therefore, the clear signals D ₂ to _{D 4} are used to ensure the clearing of each shift register 3b to 3c, and to clear unnecessary displays that remain when the number of shifts is extremely small compared to the previous display. They are necessary for erasing the information, and are configured so that all the clear signals D ₁ to D ₄ are generated without fail when updating the display information.

Next, the rotational speed signal C shown in FIG.
During the generation period of the 16th pulse, each output terminal _Q9 to
The outputs shown in FIG. ₂ f1 to _f8 are sent from _Q16 to sequentially control the lighting of the corresponding display segments in the bar graph display device 4. On the other hand, the next stage shift register 3c takes in and shifts the "L" signal output from the final stage output terminal _Q16 of the shift register 3b, and also outputs the clear signal shown in FIG. 2g.
Cleared by _D3 , all become "L" as shown in FIG. ₂ h1 to _h8 .

Next, the 17th to
During the generation period of the 24th pulse, in order to take in the "H" signal sent from the final output terminal _Q16 of the shift register 3b and shift it sequentially, the signal is sent from each output terminal _Q17 to _Q24 of the shift register 3c. is Fig. 2 h ₁ ~
An "H" signal shown at _h8 is sent to sequentially control the lighting of the corresponding display segments on the bar graph display device 4. On the other hand, the next stage shift register 3d
takes in and shifts the "L" signal output from the output end _Q16 of the final stage of the shift register 3c, and is cleared by the clear signal _D4 shown in FIG _. All become "L" as shown in _j8 .

Next, the 25th to
During the generation period of the 32nd pulse, in order to take in the "H" signal output from the final output terminal Q ₂₄ of the shift register 3c and shift it sequentially, the output terminals Q ₂₅ to _{Q 32} of the shift register 3d are is Fig. 2 j ₁ ~
An "H" signal shown at _j8 is sent to sequentially control the lighting of the corresponding display segments on the bar graph display device 4. Therefore, in this case, the 32 display segments provided in the bar graph display device 4 are set to the rotation speed signal C by the first to 32nd pulses of the rotation speed signal b shown in FIG. 2b. The lights are sequentially turned on in accordance with the pulse period, and a full-scale bar graph display is performed. In this case, the display length of the bar graph display is determined by the number of pulses in the serial pulse train that constitutes the rotational speed signal C.

The bar graph display displayed in this way is
New information is sequentially displayed by being rewritten in the same manner as described above at each predetermined update cycle. In this case, in the above configuration, instead of erasing all displays at the same time and then rewriting them as in the conventional device described above, when updating the display, the entire display is divided into multiple parts, and each division is sequentially updated. Since the data is erased and rewritten sequentially, the off-light portion during updating is extremely short, with a maximum of one segment, and as a result, display flickering is greatly reduced, improving display quality. will improve.

B Point display mode In point display mode, display mode control signal B output from output port _P1 of CPU2
are generated synchronously only when the first pulse of the rotational speed signal C is generated. In other words, in point display mode, as in bar graph display mode, first output port P ₃ of CPU2 is
Then, a clear signal D1 shown in FIG. _3a is generated, and the shift register 3a is cleared. In this way, when the clearing of the shift register 3a is completed, the same as in the case of the bar graph display mentioned above.
From the output port P2 of the CPU ₂ , a rotational speed signal C whose value is indicated by the number of pulses of the serial pulse train is outputted as shown in FIG. 3b. in this case,
The CPU 2 outputs a display mode control signal B for the point display mode which becomes "H" in synchronization with only the first pulse of the rotational speed signal C, as shown in FIG. 3c, from its output port _P1 . Therefore, when the first pulse of the rotational speed signal C is generated, the shift register 3a takes in the "H" signal of the display mode control signal B supplied to the shift input terminal _IN1 and shifts it. As shown in Figure 3 _d1 , an "H" signal is output only from the output terminal _Q1 . next,
When the second pulse of the rotational speed signal C is generated, the shift register 3a takes in the display mode control signal B supplied to the shift register input terminal _IN1 and sequentially shifts it. However, this rotational speed signal C
At the time when the second pulse is generated, the display mode control signal B is at "L" as shown in FIG. 3c, so this "L" signal is taken in and shifted sequentially. , the output signals sent from the output terminals Q ₁ and Q ₂ are "L" and "H" as shown in FIG. 3 d ₁ and d ₂ . And shift input terminal IN ₁
As described above, the display mode control signal B is supplied only when the rotation speed signal C starts generating (when the first pulse is generated). The "L" signal is taken in and shifted up sequentially, and from the output terminals Q ₁ to Q ₈ of the shift register 3a, the signals d ₁ to _{d 8} in FIG.
As shown in , one "H" signal is the rotational speed signal C.
will be shifted up each time each pulse is generated.

On the other hand, each time a pulse of the rotational speed signal C of the shift register 3b is generated, the shift input supplied to the shift input terminal _IN2 is sequentially taken in and shifted up _. Since the final stage output of the shift register 3a is "L" due to the clear signal _D1 ,
The shift register 3b takes in this "L" signal and shifts it, and the output terminals _Q9 to _Q16 maintain the "L" state at the time of reset. Since the clear signal D2 shown in FIG. 3e is generated from the CPU ₂ in conjunction with the generation of the seventh pulse, the shift register 3b
is cleared and all outputs become "L". Next, with the generation of the eighth pulse, the shift register 3a
When "H" is shifted to the output terminal _Q8 of the shift register 3b, this "H" signal is transferred to the shift input terminal of the shift register 3b.
It will be supplied to IN ₂ . Therefore, at the time when the ninth pulse of the rotational speed signal C is generated, this "H" level shift input is taken in and shifted, so that the output terminal _Q9 of the shift register 3b
The output shown in FIG. 3 f1 is sent out from the shift register _3a , and the output from the output terminal _Q8 of the shift register 3a becomes "L" again. As a result, the shift register 3b outputs "L" from the final stage output terminal _Q8 of the shift register 3a every time a pulse of the rotational speed signal C is generated.
In order to sequentially take in and shift the level output signals as shift inputs, one "H" output is sequentially moved to the upper level from the output terminals _Q9 to _Q16 as shown in Fig. 3 f1 _{to f8} . A state output is generated. From then on,
A similar operation is performed sequentially every time a pulse of the rotation speed signal C is generated, and from each output terminal Q ₁₇ to Q ₃₂ of the shift registers 3c and 3d to h ₁ to _{h 8} and j ₁ to j ₈ in FIG. As shown, an output in which one "H" signal is shifted is sent out. Note that the clear signals D ₁ to D ₄ are sent to the CPU 2 every time pulses constituting the rotational speed signal C are generated for the number of stages of the shift registers 3a to 3d.
This ensures that each of the shift registers 3a to 3d is cleared, and also that the remaining display is erased when the next smaller amount is displayed.

Each of the shift registers 3a to 3d described above
The shift operation of the "H" signal at this point is stopped when the pulse of the rotational speed signal C stops. Therefore, in this way, the shift registers 3a to 3 in which one "H" signal output terminal is sequentially shifted up
The bar graph display device 4 which inputs the output of d is
In response to the movement of the "H" signal, one display segment lights up and moves and then stops, thereby displaying the value corresponding to the rotational speed signal C as a point.

Next, as in the case of the bar graph display described above, the CPU 2 updates the rotational speed signal C at predetermined intervals and repeats the above-described operation to sequentially display new information as points.

Furthermore, since the shift register sequentially takes in and shifts shift input signals at the active level, each output terminal of this shift register generates a parallel output that is latched for approximately one update period. That will happen. As a result, the output of the shift register can be directly supplied to the bar graph display device, which eliminates the need to provide a latch circuit between the shift register and the bar graph display device, simplifying the circuit. It will be possible to achieve this.

As explained above, the display circuit according to the present invention is
It operates with the display range of the bar graph display divided into multiple parts, and when updating the display information, each division is erased by a time-sharing clear signal supplied from the CPU, and then the writing operation is performed sequentially. Therefore, the off-light portion at the time of updating is extremely short, being within the range of one section at most, and as a result, display flickering is greatly reduced and display quality is improved. Furthermore, according to the present invention, it is possible to easily switch between bar graph display and point display by simply changing the display mode control signal generated from the CPU, and this allows for multi-functionality. . Furthermore, since the shift register sequentially takes in and shifts shift input signals at the active level, each output terminal of this shift register generates a parallel output that is latched for approximately one update period. That will happen. As a result, the output of the shift register can be directly supplied to the bar graph display device.
Accordingly, it is no longer necessary to provide a latch circuit between the shift register and the bar graph display device, resulting in various excellent effects such as simplification of the circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the display circuit according to the present invention, and FIGS. 2 a to j ₈ and 3 a to j ₈ are operational waveform diagrams of each part of the circuit shown in FIG. 1. 1...Waveform shaping circuit, 2...Central processing unit, 3
a to 3d...shift register, 4...bar graph display device.

Claims (1)

[Claims for Utility Model Registration] (1) A display mode control signal is generated from the first output port, and display information expressed by the number of pulses of the serial pulse train is generated from the second output port in accordance with a predetermined update cycle. a central processing unit that generates clear signals from the third to nth output ports in a time-division manner, and third to nth output ports of the central processing unit;
Display mode control is provided in which a plurality of shift registers are connected in cascade, each being cleared by a clear signal generated from the n-th output port, each using the display information as a clock input, and generated from the central processing unit. A shift register section that receives a signal as a shift input of a first-stage shift register, and a bar graph display device in which a plurality of display segments each driven by each output of the shift register section are arranged in parallel,
In the bar graph display mode, the display mode control signal is at an active level during the transmission period of the display information, and in the point display mode, the display mode control signal is at an active level at all levels during the transmission period of the display information, and in the point display mode, the display mode control signal is at an active level at all levels during the transmission period of the display information. The clear signal is composed of a signal that is at an active level only for a predetermined pulse period, and each clear signal is composed of a time-sharing signal that sequentially clears the next stage shift register immediately before the shift output of each shift register moves to the next stage. display circuit. (2) The display circuit according to claim 1, wherein the central processing unit is unified by a semiconductor integrated circuit.