JPS5927991B2 - electronic tape counter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic tape counter that counts and displays the running amount of a tape, and particularly relates to an electronic tape counter that counts and displays the running amount of a tape.
0) and an electronic tape counter that can maintain display accuracy above a certain level without increasing or decreasing the counter capacity in any way with respect to the length of a tape such as an open reel tape.

Conventionally, various electronic tape counters have been proposed for counting and displaying the amount of tape travel, but generally they are equipped with one frequency divider and a counter, and the number of displayed digits is fixed depending on the capacity of this counter. ing. Therefore, even if the display accuracy of the tape running amount can be adjusted by changing the dividing ratio of the frequency divider, the number of displayed digits is fixed, so when used in devices with a large total tape running amount such as open reel. There was a problem.

In other words, in order to prevent overflow, it is necessary to set a large frequency division ratio. In this case, the display accuracy becomes rough with respect to the amount of tape travel, which is undesirable. It has the disadvantage that it cannot be used to search for delicate positions on the tape, and as a result, it is necessary to increase the counter capacity by selecting an appropriate frequency division ratio. In view of the above points, the present invention was made to solve such problems, and its purpose is to provide cassette tapes (C-30 to C
-120) and open reel tape, without increasing or decreasing the counter capacity in any way.
To provide an extremely versatile electronic tape counter that can maintain display accuracy above a certain level.

In order to achieve such an object, the present invention uses the content of the frequency division ratio as the data of the least significant digit of the display when the frequency division ratio matches the carry ratio of the counter. , embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing an embodiment of an electronic tape counter according to the present invention, in which one frequency divider is used.

In the figure, CLK is a clock input, DIV is a divider input for setting the division ratio of the frequency divider, RT is a reset input, and U/D is an up-down input for controlling the counter. SS is a selection switch that selects the frequency division ratio of the frequency divider, and its output becomes the depider input DIV as a setting signal. DD-UD-CNT is a divided up-down counter connected in series between the clock input terminal and an n-ary counter to be described later.
The D-CNT uses the pulse b generated as the tape runs as the clock input CLK, and operates as a frequency divider having a variable frequency division ratio of orders including a frequency division ratio of 1/n. is configured to be set by a 2-bit divider input DIV by a selection switch SS.

Here, as the clock input CLK of this divided up-down counter (hereinafter referred to as a frequency divider) DD-UD-CNT, for example, a magnet arranged on a disk integrated with the shaft of the tape supply reel is used. The signal is picked up using a magneto-electric transducer, shaped into a waveform, and then amplified. DT-CNT is a 3-digit counter that receives the output of the frequency divider DD-UD-CNT.
-CNT constitutes an m-digit n-ary counter whose counting input is the frequency-divided output of the frequency divider DD-UD-CNT.

MP is the output of the frequency divider DD-UD-CNT and a 3-digit counter (hereinafter referred to as n-ary counter) DT-C.
a scanner (multiplexer) which receives the output of the NT as an input and is controlled by the output of a digital scanner described later;
DS is n-ary counter DT-CNT and frequency divider DD-U
The parallel output of D-CNT is input, and the selection switch S
A data selector that switches its output according to the division ratio selected by S, and this data selector DS is 1
When a division ratio of /n is selected, the frequency divider DD-UD-CN
The output from T is the data of the NO digit, and the output from the n-ary counter DT-CNT is sent as the data of the n1 to Nm+1 digit, and when a frequency division ratio other than the frequency division ratio of 1/2 is selected. NO output from n-ary counter DT-CNT
~ Send as Nm digit data and divider DD-UD
-Equipped with a function to cut off the output from CNT.

DIS1 is an (m+1) digit display that displays the output of the data selector DS via the decoder driver DD.
This display device DIS1 is configured to control the display by controlling the voltage applied to the segments of the numeric display elements.

0SC is an internal oscillator that oscillates at a frequency of 30KHz, D
TS is a digital scanner that scans the output of the internal oscillator 0SC, and is configured to control the decoder driver DD and multiplexer MP by the scan output.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

First, in this embodiment, the frequency division ratio of the frequency divider DD-UD-CNT is selected from among 1/4, 1/8, 1/10, and 1/16, for example, by a 2-bit divider from a manually operated selection switch SS. When selected by the input DIV and a division ratio of 1/10 is selected, the frequency divider DD-UD-CN
The contents of T are sent to the multiplexer MP as data of the first digit, and are displayed in four digits on the display DIS1 together with the data of the three-digit counter DT-CNT. Also, 1/
When dividing ratios of 4, 1/8, and 1/16 are selected,
The data of the frequency divider DD-UD-CNT is sent to the multiplexer M
It is connected to the open output terminal in the data selector DS through P, and the data of the n-ary counter DT-CNT is connected to the output terminals of the 1st to 100th digits, so the display DIS
l is displayed in 3 digits. On the other hand, in the multiplexer MP, a divided up-down counter (frequency divider) DD-UD-C is controlled by the up-down input U/D.
Scan the data from the NT and n-ary counter DT-CNT with the scanner signal from the digital scanner DTS,
The segment and data output (7 bits) are sent to the decoder driver DD via the data selector DS.

At the same time, the digital scanner DTS sends a date scanning output (4 bits) to the decoder driver DD, and dynamically drives the display device DIS for dynamic display. At this time, a numeric display element indicating the amount of tape travel lights up. In addition, as described above, in the data selector DS, when the frequency division ratio of 1/n is selected, the output from the frequency divider DD-UD-CNT is used as the data of the NO digit, and the data is transferred to the n-ary counter DT-CNT.
Sends the output from n1 to Nm+1 digit data, and when a frequency division ratio other than 1/n is selected,
The output from the n-ary counter DT-CNT is sent as data of NO to Nm digits, and the frequency divider DD-UD-CN
Cut off the T output.

The frequency divider DD-UD-CNT and the n-ary counter DT-CNT are reset by manual operation of a reset switch (not shown) and by an initial reset input RT when the power is turned on.

In this way, when the frequency division ratio matches the carry ratio of the counter, the contents of the frequency divider are used as the data of the lowest digit of the display, so that the capacity of the counter is not increased or decreased in any way with respect to the tape length. Since the display function can be maintained above a certain level without any trouble, there is no need to make any circuit changes to match the equipment used, and the electronic tape counter can be manufactured as a general-purpose, highly integrated unit, resulting in lower prices. It can take a while.

The present invention has been described above using an example in which clocks are obtained based on the rotation of a tape supply reel as a clock source, but the present invention is not limited to this. can be used as a clock source.

Further, in the above embodiment, the case where the display is driven dynamically has been described as an example, but it goes without saying that the display may be driven statically. Furthermore, the segment and data output I from the data selector DS are configured with 7 bits because the number display is 7 segments, but the least significant digit numeric data may also be configured with an 8-bit word. In this case, the digital scanning output port may have one period of 4 bits. FIG. 2 is a block diagram showing another embodiment of the present invention, showing only the parts necessary for explanation.

In FIG. 2, the same parts as in FIG. 1 are given the same reference numerals, and their explanation will be omitted. The difference from Fig. 1 is that there are multiple stages of frequency dividers connected in cascade, such as a three-stage divided up-down circuit.
The reason is that it is composed of a counter (frequency divider). Note that DIS2 is a (m+x) (x is the number of frequency dividers) digit display. The frequency divider includes a first-stage frequency divider DD-UD-CNT that divides the clock input CLK, and a second-stage frequency divider that receives the divided output of this frequency divider DD-UD/CNTl as input. Frequency divider DD-UD-CNT2 and this frequency divider DD-U
It is composed of a third-stage frequency divider DD-UD-CNT3 that takes the frequency-divided output of D-CNT2 as input and sends the frequency-divided output to the next-stage n-ary counter DT-CNT. These frequency dividers having a plurality of variable frequency division ratios including frequency ratios are connected in series between the clock input terminal and the n-ary counter DT-CNT.

With this configuration, the third stage frequency divider DD-UD-C
When the frequency division ratio of NT3 is 1/10, 4 digits are displayed on the display DIS2, 2nd and 3rd stage frequency dividers DD-UD-CNT2, DD
-When the frequency division ratio of UD-CNT3 is 1/10, the display DI
5-digit display on S2, 1st, 2nd, and 3rd stage frequency divider DD-UD-
When the frequency division ratio of CNTl to DD-UD-CNT3 is 1/10, six digits can be displayed on the display DIS2.

The data selector DS in the embodiment shown in FIG. 2 selects the output from the frequency divider when the frequency division ratio of 1/n is selected. - The output from the n-ary counter DT-CNT is sent as f-Nm+X-digit data, and when a division ratio other than 1/n is selected, the n-ary counter DT-CNT -N output from CNT
It sends out O to Nm digit data and controls to cut off the output from the frequency divider. As explained above, according to the present invention, when the frequency division ratio matches the carry ratio of the counter, the contents of the frequency divider are used as the data of the least significant digit of the display. Since there is no need to make any changes to the circuit to match the equipment used, the electronic tape counter can be manufactured as a highly versatile unit, and the cost can be reduced, so the practical effect is It is extremely large.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of an electronic tape counter according to the present invention, and FIG. 2 is a block diagram showing another embodiment of the present invention. DD-UD-CNT, DD-UD-CNT, ~3・゜・
...divided up-down counter, SS...
...Selection switch, DT-CNT...3-digit counter, DS...Data selector, DD...Driver, DIS1, DIS2...
···display.

Claims (1)

[Claims] 1 A plurality of clocks having a frequency division ratio of 1/n are connected in series between a clock input terminal that receives pulses generated as the tape runs as a clock input and an m-digit n-ary counter that counts the frequency-divided output. a frequency divider having a variable frequency division ratio, a selection switch for selecting the frequency division ratio, and a frequency division ratio selected by the selection switch with parallel outputs of the n-ary counter and the frequency divider as inputs; A data selector that switches its output according to the
The data selector consists of a (m+x) (x is the number of frequency dividers) digit display that is displayed via a driver;
When a dividing ratio of /n is selected, the output from the frequency divider is n^0 to n^x^-^1 digit data, and the output from the n-ary counter is n^x to n^. It is sent as data of m^+^x digits, and when a frequency division ratio other than the frequency division ratio of 1/n is selected, the output from the n-ary counter is transmitted as n_0 to n^
An electronic tape counter characterized in that it is configured to transmit data as m-digit data and to control the output from the frequency divider to be cut off.