JPS63283366A - Cyclic type noise reducing device - Google Patents

Abstract

PURPOSE:To prevent the generation of an internal after image by applying a saturation type amplitude limit to a difference signal exceeding a prescribed threshold level and applying a general proportional operation having a linear area across a blind sector to the difference signal below the threshold level. CONSTITUTION:When the difference signal between an input video signal and a delay output video signal exceeds the prescribed threshold level, the saturation type amplitude limit by an amplitude limit circuit 14 and a coefficient circuit 17 is applied and when it is below the threshold level, the general proportion operation having the linear area across the blind sector by an adder-subtracter 16 is applied. Accordingly, when the difference signal exceeds the threshold level, as the difference signal grows larger, the coefficient is suppressed to shorten an after image time constant and when the difference signal goes below the threshold level, as the difference signal grows smaller, a response sensitivity to the step change of the input video signal is enlarged and a time for setting an output is shortened. Thereby, the generation of an unnecessary after image can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cyclic noise reduction device that performs cyclic noise reduction on a video signal.

[Prior Art] Among the noise reduction devices that reduce noise using field correlation or frame correlation of Video No. 43, a single image memory is used and the noise reduction target is rotated to equivalently reduce multiple images. A cyclic noise reduction device that can achieve the same effect as using a memory has the advantage of being cheaper to manufacture than a non-cyclic noise reduction device.

The conventional cyclic noise reduction device R1 shown in FIG. 5 supplies an input video signal as a subtracted input to a pair of subtracters 3.4 sandwiching a coefficient multiplier 2 whose coefficient K is less than 1. The output video signal obtained from the subtracter 4 is sent to the subtracter 3 via an image memory 5 whose delay time is a field period or a frame period, which is made to match an integer line period by rounding down or rounding up the line fraction. It is configured to use subtractive human power. The input video signal passes through a subtracter 3 and a coefficient unit 2, and then is subtracted from the original signal by a subtracter 4 to obtain (1-K
), and the delayed output video signal, which is output from the subtracter 4 and delayed in the image memory 5, is multiplied by passing through the subtracter 3, the coefficient unit 2, and the subtracter 4. The difference signal between the input video signal and the delayed output video signal obtained from the subtracter 3 has a high level for videos with movement, and for videos with rapid movement, the coefficient K is set to a high value in order to increase the noise reduction effect. The larger the afterimage time constant becomes.

[Problems to be Solved by the Invention] The above-mentioned conventional cyclic noise reduction device 1 uses an R, which uses the difference signal as an address, for the difference between the input video signal and the delayed output video signal.
Since the configuration is such that multiplication is performed by a unique coefficient K read out from the OM, a ROM is required in addition to the image memory 5, which poses problems such as increasing the manufacturing cost of the entire device.

On the other hand, a cyclic noise reduction device (not shown) using a bit shift register type coefficient multiplier has been proposed, aiming at an amplitude limiting effect by saturation characteristics like the coefficient multiplier 2. In this case, for example, an 8-bit difference signal, which is the difference between an input video signal and a delayed output video signal, is divided into 4 by a divider.
The configuration is such that the amplitude is limited by bit shifting and subtracting the shifted signal from the original signal.
If the original arrival signal is 15 or less, the output of the divider is zero, so no subtraction is actually performed, and the rounding error that occurs when handling an image input with little movement, similar to a still image, as a digital signal. There is a problem that the image remains without being canceled out until the end, resulting in an internal afterimage generation source.

[Means for Solving the Problems] The present invention solves the above problems by subtracting a delayed output video signal in which the output video signal is delayed by approximately one field or l frame period from the input video signal, A cyclic noise reduction device that multiplies the obtained difference signal by a coefficient of 1 or less in a coefficient multiplier, and then subtracts it from the input video signal to obtain an output video signal, the coefficient multiplier having a predetermined A saturation type amplitude limit is applied to the differential signal exceeding the threshold level, and a roughly proportional calculation having a linear region with a dead zone in between is applied to the differential signal below the threshold level. Features.

[Function] The present invention provides an input video signal and a field or field.
The difference signal between the output video signal and the delayed output video signal, which is obtained by delaying the output video signal over the frame period, is multiplied by a coefficient of 1 or less to apply a cyclic noise low band, and if this difference signal exceeds a predetermined threshold level, , saturation type amplitude limitation is applied, and if it is below the threshold level, a roughly proportional calculation with a linear region with a dead band in between is performed, thereby aiming at adaptive noise reduction and reducing noise generated accompanying digital processing. Eliminate the negative effects of rounding errors.

[Examples] Examples of the present invention will be described below with reference to FIGS. 1 to 4. FIG. 1 is a circuit configuration diagram showing an embodiment of the cyclic noise reduction device of the present invention, and FIGS.
A diagram showing the input/output characteristics of the coefficient multiplier shown in FIG. 1 and a partially enlarged view thereof, and FIG. 4 are signal waveform diagrams of various parts of the circuit shown in FIG. 1, respectively.

In FIG. 1, the cyclic noise reduction device ll is a conventional coefficient multiplier 2.
Instead, a coefficient multiplier 12 is provided to selectively use a saturation element and a dead band element depending on the magnitude of the difference signal. The coefficient unit 12 used in the embodiment includes an absolute value conversion circuit 13 that takes the absolute value of the differential signal input, an amplitude limiting circuit 14 that applies saturation type amplitude limiting to the output of the absolute value converting circuit 13, and an amplitude limiting circuit 14. A relative value conversion circuit 15 for restoring the output of the output signal corresponding to the polarity of the anti-difference signal input, an adder/subtractor 16 for imparting dead band characteristics, and a coefficient circuit 17 are connected in series, and this series-connected circuit is connected to the subtracters 3 and 4. Furthermore, the absolute value conversion circuit 13 includes a polarity discrimination circuit 18 that discriminates the polarity of the differential signal input, and a level discrimination circuit 19 that discriminates the level.
There is a connection. The relative value conversion circuit 15 and the adder/subtractor 16 are controlled by a polarity discrimination circuit 18, and the amplitude limiting circuit 14, the adder/subtractor 16, and the coefficient circuit 17 are controlled by a level discrimination circuit 19, and are saturated amplitude limiting elements. and dead zone elements are used properly.

That is, the amplitude limiting circuit 14 applies saturation type amplitude limiting to a differential signal input exceeding a predetermined threshold level Vo, and performs the amplitude limiting in response to a control output from the level discrimination circuit 19. The relative value conversion circuit 15 is
Depending on the polarity discrimination output of the polarity discrimination circuit 18, a positive or negative sign is attached to the output of the amplitude limiting circuit 14, and the sign is restored. Further, the coefficient circuit 17 receives the control output of the level discrimination circuit 19 for the difference signal exceeding the threshold level Vo, and can switch the coefficient K in stages so as to be inversely proportional to the level of the difference signal. Therefore, in the embodiment, the threshold level VO
For a differential signal exceeding 7/8.3/4 on the coordinate plane showing the input/output characteristics shown in FIG. I/
2, a region where the amplitude gradually decreases and a region where the amplitude is limited to a constant level are formed. Note that the difference signal is at the threshold level V
o or less, the coefficient of the coefficient circuit 17 is fixed to 1.

The adder/subtractor 16 includes a level discrimination circuit 19. operates only when it determines that the difference signal is below the threshold level Vo, and subtracts or adds a numerical value l to the difference signal according to the polarity determination output of the polarity determination circuit 18. Here, if the polarity of the difference signal is positive, l is subtracted, and if the polarity is negative, l is added. Therefore, as shown in FIG.
It is expressed as ~1/2・(lX+l 1-IX-1l), and a dead zone is formed in which the output Y does not appear for the differential signal force X whose absolute value is less than 1, and the differential signal force whose absolute value exceeds 1. Only in X, a linear region proportional to (X-1) or (x+1) is formed.

Here, when a sinusoidal differential signal input is applied to the coefficient unit 12, signal waveforms as shown in FIGS. 4(A) to (D) are observed. As already mentioned, the coefficient multiplier 12 selectively uses the saturation type amplitude limiting element and the dead band element depending on the magnitude of .

That is, the large-level differential signal X that satisfies IXI>Vo is amplitude limited by the amplitude limiting circuit 14, and multiplied by a coefficient K that decreases as the level increases by the coefficient circuit 17, so that the differential signal becomes large. It is possible to suppress the occurrence of afterimages that tend to appear accompanying video signals.
Furthermore, the smaller the level of the differential signal, the larger the coefficient K becomes, so that it is possible to suppress afterimages and increase the noise reduction effect.

On the other hand, a small level of differential signal human power X that satisfies IXI<Vo
Regarding, the very low level differential signal X with IX1≦1 is sliced by the adder/subtractor 16, and the overall amplitude is limited by the sliced amount. Also, IXI>
For a differential signal human power X of 1, the larger the absolute value, the closer the output absolute value is to the input absolute value. In other words, the coefficient multiplied by the differential signal human power 1/2.0
As such, it gradually decreases. In this case, coefficient circuit 1
Since the coefficient of 7 remains fixed at l, the coefficient unit 1
2 is determined by the adder/subtractor 16, and it can be seen that the smaller the differential signal power X, the greater the response sensitivity to a step change in the video signal power. This is important from the perspective of shortening settling time.
For example, compared to a case where the coefficient K is fixed at 3/4, the delay in rising due to a relatively slow response in the first half of rising can be sufficiently compensated for by rapid recovery in the latter half of rising.

Furthermore, after settling, if the differential signal input is within ±1, the output of the coefficient multiplier 12 is zero, so the cyclic loop is essentially cut off, and the input video signal is not subtracted at all by the subtracter 4. It is output as an output video signal without any change.

Therefore, it is possible to prevent the inconvenience that rounding errors and the like generated in the process of converting into a digital signal produce new errors through coefficient multiplication by the coefficient unit 12, causing unnecessary afterimages.

As described above, in the cyclic noise reduction device +1, when the difference signal between the input video signal and the delayed output video signal exceeds the predetermined threshold level Vo, the amplitude limiting circuit I4
The coefficient circuit 17 performs saturation type amplitude limiting, and if it is below the threshold level Vo, the adder/subtracter 16 performs a roughly proportional operation on the linear region across the dead zone, so it is a target for noise reduction. If the video signal contains many moving parts, and as a result the difference signal exceeds the threshold level VO, by suppressing the coefficient as the difference signal becomes larger, the afterimage time constant can be shortened, and if the difference signal decreases, The noise reduction effect can be increased by increasing the coefficient, and if the difference signal becomes less than the threshold level ■ 0, the response sensitivity to step changes in the input video signal becomes smaller as the difference signal becomes smaller, using approximately proportional calculation including a dead zone. By increasing the output voltage, shortening the time until the output settles, and not being sensitive to differential signals below a certain range, it is possible to prevent rounding errors that occur during the digital signal conversion process from causing unnecessary afterimages. can.

In the above embodiment, the adder/subtractor 16 subtracts the numerical value A if the polarity of the differential signal input is positive, and adds A if the polarity is negative, and for inputs where IXI≦A. may be configured such that the output is forcibly set to zero. In that case, the relationship (input/output characteristics) between the output Y and the input X is expressed as y=x-1/2-(lX+AI-IX-AI), and the range IXI≦A is defined as a dead zone.

[Effects of the Invention] As explained above, in the present invention, when the difference signal between the input video signal and the delayed output video signal exceeds a predetermined threshold level, saturation type amplitude limitation is applied, and the difference signal between the input video signal and the delayed output video signal exceeds the threshold level. If it is below, the configuration is configured to perform approximately proportional calculation with a linear region with a dead zone in between, so if the video signal targeted for noise reduction contains many moving parts and as a result, the difference signal exceeds the threshold level, By suppressing the coefficient as the difference signal increases, the afterimage 1 time constant can be shortened, and as the difference signal decreases, the noise reduction effect can be increased by increasing the coefficient, and furthermore, when the difference signal is below the threshold level, the coefficient can be increased to increase the noise reduction effect. Then, by approximately proportional calculation including a dead band, the smaller the difference signal, the greater the response sensitivity to step changes in the input video signal, shortening the time until the output settles, and making it less sensitive to difference signals below a certain range. By not doing so, excellent effects such as being able to prevent rounding errors and the like occurring in the process of converting into digital signals from causing unnecessary afterimages can be prevented.

[Brief explanation of the drawing]

Fig. 1 is a circuit configuration diagram showing an embodiment of the recursive noise reduction device of the present invention, and Figs. 2 and 3 are diagrams showing input/output characteristics of the coefficient multiplier shown in Fig. 1 and their parts, respectively. Enlarged view,
Figure 4 is a signal waveform diagram of each part of the circuit shown in Figure 1.
FIG. 1 is a circuit configuration diagram showing an example of a conventional cyclic noise reduction device. 3.4. ,, Kosanki, 5. ．． ．． image memory. 11. , cyclic noise reduction device, 12. ,,Coefficient unit,13. ,, Absolute value conversion circuit, 14. , , amplitude limiting circuit, 15. ,, relative value conversion circuit, 16. ,. Adder/subtractor, 17. , ,Coefficient circuit, 18. ,, polarity discrimination circuit, 19. ,,level discrimination circuit.

Claims (1)

[Claims] subtracting a delayed output video signal obtained by delaying the output video signal by approximately one field or one frame period from the input video signal;
A cyclic noise reduction device that multiplies the obtained difference signal by a coefficient of 1 or less in a coefficient multiplier, and then subtracts it from the input video signal to obtain an output video signal, the coefficient multiplier having a predetermined A cyclic type that has a configuration in which a saturation type amplitude limit is applied to a differential signal exceeding a threshold level, and a roughly proportional calculation having a linear region with a dead zone in between is applied to a differential signal below the threshold level. Noise reduction device.