JP2755112B2 - Contour correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contour correction circuit for improving the sharpness of an image by making the rising and falling edges of an image portion sharper.

[0002]

2. Description of the Related Art Conventionally, a contour correction circuit for sharpening a video signal has been used in order to improve blurring of an image and lack of resolution when the video signal is projected on a screen of a television receiver or the like. I have. FIG. 5 is a block diagram showing an example of a conventional contour correction circuit, and its configuration and operation will be described together with the waveform diagram shown in FIG. The waveforms a to g shown in FIG. 6 correspond to the signals a to g in FIG.

In FIG. 5, a signal a (waveform a in FIG. 6) input to an input terminal 1 is input to a delay circuit 2 and is delayed by a predetermined time to become a signal b (waveform b in FIG. 6). This signal b is input to the delay circuit 3 and further delayed for a predetermined time to become a signal c (waveform c in FIG. 6). Arithmetic unit 4 receives input signal a and signal b, and arithmetic unit 4 outputs signal d (waveform d in FIG. 6) by subtracting input signal a from signal b. Similarly, the arithmetic unit 5 receives the signal b and the signal c, and the arithmetic unit 5 outputs a signal e (a waveform e in FIG. 6) by subtracting the signal c from the signal b.

The signal d and the signal e are input to an adder 6, and the adder 6 adds the signal d and the signal e to output a signal f (a waveform f in FIG. 6) which is a contour component. Further, the signal f is input to the adder 7, and the adder 7 adds the signal b output from the delay circuit 2 to the signal f, and outputs a signal g (a waveform g in FIG. 6) from the output terminal 8. As can be seen from FIG. 6, the output signal g has a sharper rising and falling edge portion than the input signal a, and is a sharpened video signal whose contour has been corrected.

[0005]

In the conventional contour correction circuit, the output signal is as shown by a waveform g in FIG.
By performing sharpening, pre-shooting occurs at the edge,
Overshoot occurs. By the way, rising,
In order to further sharpen the fall and further improve the sharpness, it is necessary to increase the amount of addition of the signal f which is the contour correction signal. When the contour correction signal has a waveform twice as large as the waveform f as shown by the waveform h in FIG. 6, the output signal becomes the signal i shown by the waveform i in FIG. , The level of the overshoot increases and the edge becomes steeper than the signal g.

However, if the preshoot and the overshoot are emphasized too much, the outline looks like a white or black border on the screen, which is visually unnatural, so that the preshoot and the overshoot are as thin as possible. In the conventional contour correction circuit, if the rising and falling edges are made steeper and the sharpness is to be further improved, the pre-processing is required along with an increase in the amount of addition of the contour correction signal. Shooting and overshoot levels increase, and unnaturalness on the screen becomes noticeable. That is, the conventional contour correction circuit has a problem that sharpness cannot be improved without increasing adverse effects on image quality due to preshoot and overshoot.

The present invention has been made in view of such a problem, and makes it possible to make the rising and falling steep without increasing the levels of preshoot and overshoot, and to further reduce the width of the shoot. An object of the present invention is to provide a contour correction circuit capable of reducing visual unnaturalness by reducing the thickness.

[0008]

According to the present invention, in order to solve the above-mentioned problems of the prior art, (1) an input first signal (A) is converted into a first delay time and a first signal, respectively. A second delay time greater than the delay time, a third delay time greater than the second delay time, and a second to a fifth delay time delayed by a fourth delay time greater than the third delay time. Signal (B ~
E) generating means (12 to 15), and a signal obtained by subtracting the second signal from the third signal and a signal obtained by subtracting the fourth signal from the third signal. Means (16-20) for generating a sixth signal (G)
And subtracting the first signal from the third signal to obtain a seventh signal
Means (21) for generating the signal (H) of the second signal, means (22) for subtracting the fifth signal from the third signal to generate the eighth signal (I), and the seventh signal Means (23) for generating a ninth signal (J) by taking the maximum value of the second signal and the eighth signal; and a means for taking the minimum value of the seventh signal and the eighth signal and inverting the same. Means (24, 25) for generating the tenth signal (K), and means (26) for generating the eleventh signal (L) by taking the maximum value of the ninth signal and the tenth signal. Means (27 to 29) for generating a twelfth signal (M) having only a negative component of the minimum value of the ninth signal and the tenth signal, and the twelfth signal from the eleventh signal To generate a thirteenth signal (N) by subtracting
0), means (31) for multiplying the sixth signal and the thirteenth signal to generate a fourteenth signal (0), and adding the fourteenth signal and the third signal. Means (32) for generating a fifteenth signal (P), which is an output signal whose contour has been corrected by means of a contour correction circuit. The signal (A) is divided into a first delay time and a second delay time longer than the first delay time, respectively.
, A third delay time greater than the second delay time, and second to fifth signals (B to D) delayed by a fourth delay time greater than the third delay time. Generating means (12 to 15), a signal obtained by subtracting the second signal from the third signal, and a signal obtained by subtracting the fourth signal from the third signal, and Means (16 to 20) for generating a signal (G) of No. 6 and means (23) for generating a seventh signal (H) by taking the maximum value of the first signal and the fifth signal. Means for generating an eighth signal (I) by taking the minimum value of the first signal and the fifth signal, and subtracting the third signal from the seventh signal. Means for generating a ninth signal (J) (2
1) means for subtracting the eighth signal from the third signal to generate a tenth signal (K); and a maximum value of the ninth signal and the tenth signal. Take the eleventh
Means (26) for generating the signal (L) of the second signal, and the twelfth signal of only the negative component of the minimum value of the ninth signal and the tenth signal.
Means (27-29) for generating the signal (M) of the second signal; means (30) for generating the thirteenth signal (N) by subtracting the twelfth signal from the eleventh signal; Means (31) for multiplying the fourteenth signal and the thirteenth signal to generate a fourteenth signal (O), and an output signal whose contour has been corrected by adding the fourteenth signal and the third signal And a means (32) for generating a fifteenth signal (P).

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A contour correction circuit according to the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a first embodiment of the contour correction circuit of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the first embodiment of the contour correction circuit of the present invention, and FIG. FIG. 4 is a block diagram showing a second embodiment of the correction circuit, and FIG. 4 is a waveform diagram for explaining the operation of the second embodiment of the contour correction circuit of the present invention.

First, the configuration and operation of the first embodiment of the contour correction circuit of the present invention shown in FIG. 1 will be described with reference to the waveform diagram shown in FIG. Note that waveforms A to P shown in FIG. 2 correspond to signals A to P in FIG.

In FIG. 1, a signal A (waveform A in FIG. 2) input to an input terminal 11 is input to a delay circuit 12 and is delayed by a predetermined time to become a signal B (waveform B in FIG. 2). Is input to the delay circuit 13 and further delayed by a predetermined time to become a signal C (waveform C in FIG. 2). Here, the sum of the delay times of the delay circuits 12 and 13 is set to be equal to the delay time of the delay circuit 2 in FIG. 5 for comparison with the conventional example. The signal C is input to the delay circuit 14 and is delayed for a predetermined time to become a signal D (waveform D in FIG. 2). This signal D is input to the delay circuit 15 and further delayed for a predetermined time to generate a signal E.
(Waveform E in FIG. 2). Here, the delay circuits 14 and 15
Is set equal to the delay time of the delay circuit 3 in FIG. 5 for comparison with the conventional example.

The signal B and the signal C are input to the arithmetic unit 16, and the arithmetic unit 16 subtracts the signal B from the signal C. Similarly, the arithmetic unit 17 receives the signal C and the signal D, and the arithmetic unit 17 subtracts the signal D from the signal C. These computing units 1
The outputs of 6 and 17 are input to an adder 18, which adds them and outputs a signal F (waveform F in FIG. 2).
The signal F is amplified by the amplifier 19, and thereafter, the signal G (waveform G in FIG. 2) is clipped by being limited by a predetermined level or more by the amplitude limiter 20, and is input to the multiplier 31.

On the other hand, the input signal A and the signal C
Is input, and the arithmetic unit 21 subtracts the input signal A from the signal C and outputs a signal H (waveform H in FIG. 2). Similarly, the arithmetic unit 22 receives the signal C and the signal E, and the arithmetic unit 22 subtracts the signal E from the signal C and outputs a signal I (waveform I in FIG. 2). These signals H and I are input to the maximum value comparator 23 and the minimum value comparator 24. The maximum value comparator 23 detects the larger one of the inputted signals H and I and detects the larger one of the signals J (FIG. 2).
Is output. The minimum value comparator 24 detects the smaller one of the input signals H and I, and the inverting amplifier 25 inverts the output of the minimum value comparator 24 and outputs a signal K (waveform K in FIG. 2). . These signals J and K are output from the maximum value comparator 26.
And the minimum value comparator 27.

The maximum value comparator 26 receives the input signals J, K
Of the input signals J and K, the minimum value comparator 27 outputs a signal L (waveform L in FIG. 2).
Detect the smaller one. The output of the minimum value comparator 27 and the reference voltage output from the reference voltage generator 28 are input to the minimum value comparator 29. Here, since this reference voltage is set equal to the DC (direct current) bias voltage of the minimum value comparator 27, the output of the minimum value comparator 29 is output to the minimum value comparator 2
7, a signal M (waveform M in FIG. 2) which is only the negative component of the output is obtained. The signal L and the signal M are input to the arithmetic unit 30,
Arithmetic unit 30 subtracts signal M from signal L to obtain signal N (FIG. 2).
Is output.

Further, the signal N is input to a multiplier 31,
The multiplier 31 multiplies the signal G output from the amplitude limiter 20 by the signal N, and outputs a contour correction signal O (waveform O in FIG. 2). The contour correction signal O is input to the adder 32, and the adder 32 outputs the signal C output from the delay circuit 13.
The contour correction signal O is added to generate a contour-corrected signal P (waveform P in FIG. 2), which is output from an output terminal 33.

The contour correction circuit of the first embodiment is constructed and operates as described above. As described above, the signal G input to the multiplier 31 is obtained by amplifying the signal F so that its rise and fall become steep, and limiting its level. Therefore, the edge portion of the contour correction signal O obtained by multiplying the signal G by the signal G is also very steep. as a result,
The rise and fall of the output signal P are steeper than those of the output signal according to the conventional example (waveform g in FIG. 6), and the level of the shoot is equivalent. As described above, according to the present invention, the sharpness can be improved without increasing the adverse effect on the image quality due to the preshoot and the overshoot.

Further, it can be seen that the shoot width x of the output signal P according to the present invention is smaller than the shoot width y of the output signal g according to the conventional example. By the way, the shoot width y in the conventional example is represented by signals a, b, c (waveforms a, b,
It is determined by the contour correction signal f obtained by adding and subtracting from c). As described above, the total delay time of the delay circuits 12 and 13 in FIG. 1 is equal to the delay time of the delay circuit 2 in FIG. 5, and the total delay time of the delay circuits 14 and 15 in FIG. ,
The waveforms a, b, and c in FIG. 6 are equal to the waveforms A, C, and E in FIG. 2 because they are set equal to the delay circuit 3 in FIG. In the present invention, the shoot width x is determined by the signal G input to the multiplier 31, and this signal G is obtained by adding and subtracting the signals B, C, and D. Therefore, signals A,
The circuit of the present invention in which the shoot width is determined by the signals obtained from the signals B, C and D is narrower than the conventional circuit in which the shoot width is determined by the signals obtained from C and E. Note that the shoot width x can be varied by the delay time of the delay circuits 13 and 14. If the shoot width x is made thinner, the outline of the outline on the screen becomes thinner and unnaturalness is reduced.

Next, the configuration and operation of the second embodiment of the contour correction circuit of the present invention shown in FIG. 3 will be described with reference to the waveform diagram shown in FIG. Note that waveforms A to P shown in FIG. 4 correspond to signals A to P in FIG. In FIG. 3, the same parts as those in FIG. 1 are denoted by the same reference numerals.

In FIG. 3, a signal A (waveform A in FIG. 4) input to an input terminal 11 is input to a delay circuit 12 and is delayed by a predetermined time to become a signal B (waveform B in FIG. 4). Is input to the delay circuit 13 and further delayed for a predetermined time to become a signal C (waveform C in FIG. 4). Here, the sum of the delay times of the delay circuits 12 and 13 is set to be equal to the delay time of the delay circuit 2 in FIG. 5 for comparison with the conventional example. The signal C is input to the delay circuit 14 and is delayed for a predetermined time to become a signal D (waveform D in FIG. 4). This signal D is input to the delay circuit 15 and further delayed for a predetermined time to generate a signal E.
(Waveform E in FIG. 4). Here, the delay circuits 14 and 15
Is set equal to the delay time of the delay circuit 3 in FIG. 5 for comparison with the conventional example.

The signal B and the signal C are input to the arithmetic unit 16, and the arithmetic unit 16 subtracts the signal B from the signal C. Similarly, the arithmetic unit 17 receives the signal C and the signal D, and the arithmetic unit 17 subtracts the signal D from the signal C. These computing units 1
The outputs of 6 and 17 are input to an adder 18, which adds them and outputs a signal F (waveform F in FIG. 4).
This signal F is amplified by the amplifier 19, and thereafter, the signal G (waveform G in FIG. 4) is clipped by being limited by a predetermined level or more by the amplitude limiter 20, and is input to the multiplier 31.

On the other hand, the input signal A and the signal E are input to the maximum value comparator 23 and the minimum value comparator 24. The maximum value comparator 23 detects the larger one of the input signals A and E and outputs a signal H (waveform H in FIG. 4).
Detects the smaller one of the input signals A and E and outputs a signal I (waveform I in FIG. 4). Arithmetic unit 21 receives signal H
The arithmetic unit 21 subtracts the signal C from the signal H and outputs a signal J (waveform J in FIG. 4). Similarly,
The signal C and the signal I are input to the arithmetic unit 22, and the arithmetic unit 22
Is the signal K obtained by subtracting the signal I from the signal C (waveform K in FIG. 4)
Is output. These signals J and K are input to the maximum value comparator 26 and the minimum value comparator 27.

The maximum value comparator 26 receives the input signals J and K
Of the input signals J and K, the minimum value comparator 27 outputs the signal L (waveform L in FIG. 4).
Detect the smaller one. The output of the minimum value comparator 27 and the reference voltage output from the reference voltage generator 28 are input to the minimum value comparator 29. Here, since this reference voltage is set equal to the DC (direct current) bias voltage of the minimum value comparator 27, the output of the minimum value comparator 29 is output to the minimum value comparator 2
7, a signal M (waveform M in FIG. 4) which is only the negative component of the output of FIG. The signal L and the signal M are input to the arithmetic unit 30,
Arithmetic unit 30 subtracts signal M from signal L to obtain signal N (FIG. 4).
Is output.

Further, the signal N is input to the multiplier 31,
The multiplier 31 multiplies the signal G output from the amplitude limiter 20 by the signal N and outputs a contour correction signal O (waveform O in FIG. 4). The contour correction signal O is input to the adder 32, and the adder 32 outputs the signal C output from the delay circuit 13.
And a contour correction signal O to generate a contour-corrected signal P (waveform P in FIG. 4), which is output from an output terminal 33.

The outline correction circuit of the second embodiment operates and operates as described above. As described above, the signal G input to the multiplier 31 is obtained by amplifying the signal F so that its rise and fall become steep, and limiting its level. Therefore, the edge portion of the contour correction signal O obtained by multiplying the signal G by the signal G is also very steep. as a result,
The rise and fall of the output signal P are steeper than those of the output signal according to the conventional example (waveform g in FIG. 6), and the level of the shoot is equivalent. As described above, according to the present invention, the sharpness can be improved without increasing the adverse effect on the image quality due to the preshoot and the overshoot.

Further, it can be seen that the shoot width x of the output signal P according to the present invention is smaller than the shoot width y of the output signal g according to the conventional example. By the way, the shoot width y in the conventional example is represented by signals a, b, c (waveforms a, b,
It is determined by the contour correction signal f obtained by adding and subtracting from c). As described above, the total delay time of the delay circuits 12 and 13 in FIG. 3 is equal to the delay time of the delay circuit 2 in FIG. 5, and the total delay time of the delay circuits 14 and 15 in FIG. ,
The waveforms a, b, and c in FIG. 6 are equal to the waveforms A, C, and E in FIG. 4 because they are set equal to the delay circuit 3 in FIG. In the present invention, the shoot width x is determined by the signal G input to the multiplier 31, and this signal G is obtained by adding and subtracting the signals B, C, and D. Therefore, signals A,
The circuit of the present invention in which the shoot width is determined by the signals obtained from the signals B, C and D is narrower than the conventional circuit in which the shoot width is determined by the signals obtained from C and E. Note that the shoot width x can be varied by the delay time of the delay circuits 13 and 14. If the shoot width x is made thinner, the outline of the outline on the screen becomes thinner and unnaturalness is reduced.

[0026]

As described in detail above, the contour correction circuit of the present invention, having the above-described configuration, can increase the rise and fall of the preshoot and overshoot without increasing the preshoot and overshoot levels as compared with the conventional contour correction circuit. The fall can be steeper, and the width of the shoot can be narrower. Therefore, the sharpness of the image can be further improved, and the visual unnaturalness on the screen can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the first embodiment of the present invention.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a waveform chart for explaining the operation of the second embodiment of the present invention.

FIG. 5 is a block diagram showing a conventional example.

FIG. 6 is a waveform chart for explaining a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Input terminal 12-15 Delay circuit 16,17,21,22,30 Operation unit 18,32 Adder 19 Amplifier 20 Amplitude limiter 23,26 Maximum value comparator 24,27,29 Minimum value comparator 25 Inverting amplifier 28 Reference voltage generator 31 Multiplier 33 Output terminal

Claims (2)

(57) [Claims] An input first signal is converted into a first delay time, a second delay time larger than the first delay time,
Means for generating second to fifth signals delayed by a third delay time greater than the second delay time and a fourth delay time greater than the third delay time; and Means for generating a sixth signal that is an edge enhancement component from a signal obtained by subtracting the second signal from the signal and a signal obtained by subtracting the fourth signal from the third signal; and the third signal. Means for subtracting the first signal from the first signal to generate a seventh signal; means for subtracting the fifth signal from the third signal to generate an eighth signal; and the seventh signal. Means for generating a ninth signal by taking the maximum value of the signal and the eighth signal; and generating a tenth signal obtained by inverting the signal by taking the minimum value of the seventh signal and the eighth signal. Means for taking the maximum value of the ninth signal and the tenth signal to generate an eleventh signal; Means for generating a twelfth signal of the negative component only of the minimum value of said ninth signal and said tenth signal, the first by subtracting the twelfth signal from said eleventh signal
Means for generating a third signal; and multiplying the sixth signal by the thirteenth signal to generate a fourteenth signal.
And a means for adding the fourteenth signal and the third signal to generate a fifteenth signal which is a contour-corrected output signal. Contour correction circuit. 2. The method according to claim 1, wherein the first signal is converted into a first delay time, a second delay time larger than the first delay time,
Means for generating second to fifth signals delayed by a third delay time greater than the second delay time and a fourth delay time greater than the third delay time; and Means for generating a sixth signal which is an edge enhancement component from a signal obtained by subtracting the second signal from the signal and a signal obtained by subtracting the fourth signal from the third signal; and the first signal Means for generating a seventh signal by taking the maximum value between the first signal and the fifth signal; means for generating an eighth signal by taking the minimum value between the first signal and the fifth signal. Means for subtracting the third signal from the seventh signal to generate a ninth signal; means for subtracting the eighth signal from the third signal to generate a tenth signal. Means for taking a maximum value of the ninth signal and the tenth signal to generate an eleventh signal; Means for generating a twelfth signal consisting only of the negative component of the minimum value between the signal No. 9 and the signal No. 10;
Means for generating a third signal; and multiplying the sixth signal by the thirteenth signal to generate a fourteenth signal.
And a means for adding the fourteenth signal and the third signal to generate a fifteenth signal which is a contour-corrected output signal. Contour correction circuit.