JPH01194577A - Noise reducing circuit - Google Patents

Abstract

PURPOSE:To enable the high S/N improvement factor of a signal to be achieved while reducing an after image phenomenon or the deterioration of resolution by non linear processing a movement component and a noise component at every band. CONSTITUTION:This circuit is constituted with an A/D converter 30, subtracters 32, 40 and 48, a field memory 34, a low-pass filter (an LPF) 36, limitters 38 and 42, an adder 44, a coefficient multiplier 46 and a D/A converter 50. Then, the movement component, the low-band component of noise and the high-band component of the noise are separated and individually non-linear-processed. Thus, even the S/N of the signal having much noise can be improved without the occurrence of the afterimage phenomenon or the deterioration of the resolution.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a circuit for reducing noise in a video signal, and more specifically, to a circuit for reducing noise in a video signal, and more specifically to a circuit for reducing noise in a video signal, and more specifically, for use in video equipment such as a video camera and a video tape recorder. Regarding suitable noise reduction circuits.

[Conventional technology]

As a video signal noise reduction circuit, a cyclic noise reducer using a field memory is known.

Its configuration is shown in FIG. The input video signal is converted into a digital signal by the A/D converter 10, and the subtracter 12 calculates the difference between the input video signal and the video signal one field period ago supplied from the field memo 1J14. Subtractor 12
The difference signal outputted by passes through a limiter 16 having input/output characteristics shown in FIG. 3, and is applied to a coefficient multiplier 18. The coefficient multiplier 18 is a circuit that multiplies the input signal by a coefficient K (OAK≦1). The subtracter 20 is the A/D converter 1
The output of the coefficient multiplier 18 is subtracted from the output of 0. The output of subtractor 20 is applied to field memory 14 and D/A converter 22.

Field memory 14 functions as a delay element for one field period, as described above, and D/A converter 22 converts the digital video signal back to an analog signal. D/
The output of A converter 22 becomes a noise reduction output.

In the illustrated circuit, the limiter 16 substantially reduces the multiplication coefficients in the limiter 16 and the coefficient multiplier 18 as the amplitude of the input to the limiter 16 becomes larger, so that it is a kind of motion adaptive type.

[Problem to be solved by the invention]

However, in the above conventional example, it is not possible to simultaneously reduce the afterimage phenomenon and resolution deterioration and improve the S/N ratio.
By reducing the threshold value TH of the limiter 16, it is possible to reduce the afterimage phenomenon and resolution deterioration, but with a noisy signal, the S/
N The degree of improvement decreases.

On the other hand, if the threshold value TH is increased, the degree of S/N improvement will be improved, but there will be problems such as afterimage phenomenon and deterioration of resolution.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a noise reduction circuit that reduces the afterimage phenomenon and deterioration of resolution and has a high degree of S/N improvement.

[Means to solve the problem]

The noise reduction circuit according to the present invention includes a subtracting means for calculating the difference between an input video signal and a video signal obtained a predetermined period before the input video signal, and a band dividing means for dividing the output of the subtracting means into a plurality of bands. means, nonlinear processing means for performing nonlinear processing for each band by the band dividing means, addition means for adding the sum of outputs of the nonlinear processing means and the input video signal or the video signal of a predetermined period before, and the addition means. and delay means for delaying the output for the predetermined period.

[Effect]

Since the motion component and the noise component are nonlinearly processed for each band by the band division means and nonlinear processing means, it is possible to take measures to prevent afterimage phenomena and resolution deterioration and to improve the original S/N ratio separately. Therefore, a high degree of S/N improvement can be achieved while reducing the afterimage phenomenon and deterioration of resolution.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a configuration block diagram of an embodiment of the present invention. In FIG. 1, an input video signal is converted into a digital signal by an A/D converter 30, and a subtracter 32 as a subtracting means calculates the difference between the input video signal and the video signal from one field period before, which is supplied from a field memory 34. Be taken. The difference signal output from the subtracter 32 is passed through a low pass filter (L
PF) 36 to a limiter 38. The difference signal output from the subtracter 32 includes a motion component and a noise component, but the high frequency component of the noise is removed by the LPF 36, and therefore the motion component and the low frequency component of the noise are input to the limiter 38. . The limiter 38 is set at a low limit level to the extent that no afterimage phenomenon or deterioration of resolution occurs. The input/output characteristics of the limiter 38 are shown in FIG.

The output of the LPF 36 is also applied to the subtracter 40.
0 calculates the difference between the input and output of the LPF 36 and applies it to the limiter 42. Since the difference signal output from the subtracter 40 is a high-frequency component of noise, the limiter 42 sets its limit level TH2 (>THI) large so that the S/N can be improved even with a noisy signal. It is. The input/output characteristics of the limiter 42 are shown in FIG.

Adder 44 adds the output of limiter 38 and the output of limiter 42. A coefficient multiplier 46 multiplies the output signal of the adder 44 by a coefficient K (0<K≦1). A subtracter 48 serving as an addition means subtracts the output of the coefficient multiplier 46 from the output of the A/D converter 30. The output of subtractor 48 is applied to field memory 34 and D/A converter 50. Field memory 34 is field memory 14
Similarly, it functions as a delay element for one field period. Additionally, the D/A converter 50 converts the digital video signal back into an analog signal. The output of the D/A converter 50 becomes a noise reduction output.

In the circuit of the above embodiment, the input video signal is output as is for the low frequency component that contains many motion components even if it is at a relatively low level, and the high frequency component that contains many noise components is output as is. Even if the component is at a relatively high level, the average level of the signal before the previous field is output, which reduces the afterimage phenomenon and reduces the large S
/N improvement can be obtained.

In the illustrated embodiment, the field memory 34 stores 1
Although the video signal before the frame period was used, the frame
The video signal of one frame before may be used by memory.

Furthermore, as shown in FIG. 6, coefficients K I, K z (0< K I, K
Coefficient multipliers 52 and 54 for multiplying by z≦1) may be provided, and the outputs thereof may be added by an adder 56 and applied to the subtracter 48. In this modified example, two coefficient multipliers 5
2.54 is used, which has the disadvantage of increasing the number of parts and becoming expensive, but it is possible to further improve the S/N without causing image retention or deterioration of resolution.

In the above two examples, for convenience of explanation, the coefficient multiplier 46,
52.54 was provided independently, but of course the limiter 38.4
It may be replaced by a circuit element integrated into 2.

FIG. 7 shows yet another embodiment of the invention. The input video signal digitized by the A/D converter 30 is supplied to a subtracter 62 as a subtraction means, together with a signal delayed by one field period by a field memory 74.
These differential signals are obtained. The difference signal output from the fIi multiplier 62 is band-divided by the LPF 64 and the subtracter 66, and the low frequency component output from the LPF 64 is stored in the memory.
The high-frequency components output from the subtracter 66 are supplied to the table 68 and the memory table 70 as address signals, respectively.

FIG. 8 shows the input/output characteristics of memory table 68.70. p indicates the characteristics of memory table 68 and q indicates the characteristics of memory table 70.

The low frequency component contains many motion components, so
In table 68, the gain is set to a large value starting from a low level (THI), and the high frequency components are considered to be noise.
The gain is reduced up to 2).

The outputs of these memory tables 68, 70 are output to adder 72.
The output of the adder 72 is added to the output of the field memory 74 by an adder 74 serving as an adding means.

The output of the adder 76 is a signal similar to that of the subtracter 48 in FIG. 1, and is a noise-reduced output.

It goes without saying that the embodiment shown in FIG. 7 also provides the same effects as the embodiments shown in FIGS. 1 and 6.

In addition, although the above explanation took a digital processing circuit as an example,
Of course, it goes without saying that analog processing circuits can also produce similar effects.

〔Effect of the invention〕

As can be easily understood from the above description, according to the present invention, motion components and low-frequency components of noise and high-frequency components of noise are separated and separately nonlinearly processed, so that noisy signals can be easily processed. However, the S/N ratio can be improved without causing an afterimage phenomenon or deterioration of resolution.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of the embodiment of the present invention, FIG. 2 is a block diagram of the configuration of the conventional example, and FIG. 3 is the limiter 16 of FIG.
4 is an input/output characteristic diagram of the limiter 38 in FIG. 1, FIG. 5 is an input/output characteristic diagram of the limiter 42 in FIG. 1, and FIG. 6 is a configuration of a modified embodiment of the present invention. Block diagram, FIG. 7 is a configuration block diagram of still another embodiment of the present invention, FIG.
The figure is a characteristic diagram of memory table 68, 70 of FIG. 30-A/D converter 32, 40, 48.62...
-Subtractor 34.74--Field memory 36
-LPF 38.42--Limiter 44,56゜72.76--Adder 46,52.54--Coefficient multiplier 50-D/A converter 68, 70-Memory ° table

Claims (1)

[Claims] subtracting means for calculating the difference between an input video signal and a video signal a predetermined period before the input video signal; a band dividing means for dividing the output of the subtracting means into a plurality of bands; and a band by the band dividing means. a nonlinear processing means that performs nonlinear processing for each time; an addition means that adds the sum of the outputs of the nonlinear processing means and the input video signal or a video signal before a predetermined period; and a delay that delays the output of the addition means for the predetermined period. A noise reduction circuit comprising: means.