JPS6328335B2 - - Google Patents
Info
- Publication number
- JPS6328335B2 JPS6328335B2 JP55119332A JP11933280A JPS6328335B2 JP S6328335 B2 JPS6328335 B2 JP S6328335B2 JP 55119332 A JP55119332 A JP 55119332A JP 11933280 A JP11933280 A JP 11933280A JP S6328335 B2 JPS6328335 B2 JP S6328335B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- resist
- etching
- semiconductor substrate
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005530 etching Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 11
- 238000001312 dry etching Methods 0.000 claims description 6
- 150000003377 silicon compounds Chemical class 0.000 claims description 4
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 239000004020 conductor Substances 0.000 description 18
- 239000010408 film Substances 0.000 description 17
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 15
- 229910052782 aluminium Inorganic materials 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 229910004298 SiO 2 Inorganic materials 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 239000010409 thin film Substances 0.000 description 8
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910018182 Al—Cu Inorganic materials 0.000 description 1
- 229910016006 MoSi Inorganic materials 0.000 description 1
- -1 MoSi 2 Chemical class 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法、より詳しくは
シリコン等の半導体基板上において絶縁膜中に埋
込まれ表面が平坦化された電極構造を得る方法に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for obtaining an electrode structure on a semiconductor substrate made of silicon or the like, which is embedded in an insulating film and whose surface is flattened.
半導体集積回路の集積度が高まるにつれて、多
層配線構造が形成されるようになつてきている。
その場合に、ある層のパターンの凹凸は隣接する
次の層に悪影響を及ぼし、隣接する層に段差が生
じ、微細パターンが形成されえないだけでなく、
場合によつてはパターンが断線することもある。 As the degree of integration of semiconductor integrated circuits increases, multilayer wiring structures are being formed.
In that case, the unevenness of the pattern on one layer will have a negative effect on the next layer, creating a step difference in the adjacent layer, and not only will it not be possible to form a fine pattern.
In some cases, the pattern may be disconnected.
かかる例を第１図の断面説明図にみると、シリ
コン等の半導体基板１上の例えばアルミニウム導
体層２の上に、絶縁層３を介在せしめて第２層の
アルミニウム導体層５を配置したい場合、アルミ
ニウム層２が図示の如き形状で配置されると絶縁
層３には図に見られる如き段差Ｂが形成され、そ
の上のアルミニウム層５を形成すると段部Ａが作
られ、アルミニウム層５は段部Ａで断線するおそ
れがある。 Looking at such an example in the cross-sectional explanatory diagram of FIG. 1, when it is desired to arrange a second aluminum conductor layer 5 on, for example, an aluminum conductor layer 2 on a semiconductor substrate 1 made of silicon or the like, with an insulating layer 3 interposed therebetween. When the aluminum layer 2 is arranged in the shape shown in the figure, a step B as shown in the figure is formed in the insulating layer 3, and when the aluminum layer 5 is formed on it, a step A is created, and the aluminum layer 5 is There is a risk of wire breakage at step A.
この問題を解決するために、絶縁層の間に埋め
込まれた如き状態に導体パターンを形成すること
が考えられた。それによると、第２図の断面説明
図に示されるように、先ずシリコン基板１上に導
電層にを形成し、それをパターニングした後に
（同図ａ）導体上のレジスト４は残したままにし
ておいて、レジストを含む基板の全表面上に一酸
化シリコン（SiO）または二酸化シリコン
（SiO2）膜３を蒸着またはスパツターによつて形
成し、（同図ｂ）次にアセトンまたはアツシヤー
を用いてレジストを灰化することによつてレジス
トとその上のSiO2膜３を除去するものである。
かくして形成された導体と絶縁膜の構造は、同図
ｃに示す如きのもので、シリコン基板１上の導体
２は、SiO2層３の間に埋め込まれた如くに配置
され、その表面は平坦になつている。 In order to solve this problem, it has been considered to form a conductor pattern embedded between insulating layers. According to this, as shown in the cross-sectional explanatory diagram of Fig. 2, a conductive layer is first formed on a silicon substrate 1, and after patterning it (Fig. 2a), the resist 4 on the conductor is left. Then, a silicon monoxide (SiO) or silicon dioxide (SiO 2 ) film 3 is formed on the entire surface of the substrate including the resist by vapor deposition or sputtering (Fig. By ashing the resist, the resist and the SiO 2 film 3 thereon are removed.
The structure of the conductor and insulating film thus formed is as shown in figure c, in which the conductor 2 on the silicon substrate 1 is placed so as to be buried between the SiO 2 layers 3, and its surface is flat. It's getting old.
上記の技術における問題はレジストの剥離であ
る。例えばSiO2膜３がスパツタリング法により
形成されるとき、第２図ｂに点線で示す如き
SiO2のバリによつてレジスト４が完全に覆われ
てレジストが除去されないことになる。また、蒸
着がある角度でなされたとき、第２図ｄに示すよ
うに、レジストの一方側のみにSiO2膜が形成さ
れ、レジストをアツシヤーで灰化したときに、導
体の表面が平坦に形成されない。 A problem with the above techniques is resist peeling. For example, when the SiO 2 film 3 is formed by the sputtering method, as shown by the dotted line in FIG.
The resist 4 is completely covered by the SiO 2 burr and cannot be removed. Furthermore, when the vapor deposition is carried out at a certain angle, a SiO 2 film is formed only on one side of the resist, as shown in Figure 2d, and when the resist is ashed with an assher, the surface of the conductor becomes flat. Not done.
この技術的課題を解決するために、本出願人は
薄膜パターン形式方法なる発明を完成した（昭和
52年特許願第9003号、昭和53年８月19日に特開昭
53−94771号として公開）。該発明は、第５図ａ〜
ｆを参照すると、基板３１上に導体パターン形成
用薄膜、例えばAl−Cu膜３２を付着させ〔第５
図ａ〕、この薄膜３２上にレジスト・パターン３
３を形成し〔同図ｂ〕、このレジスト・パターン
３３をマスクとして前記薄膜３２をエツチングし
て所望の導体パターンを形成した後〔同図ｃ〕、
前記レジスト・パターンを残したまま絶縁材料、
例えばSiO2３４を蒸着し〔同図ｅ〕、しかる後レ
ジスト・パターン３３を除去することによつて平
面化し〔同図ｆ〕、この平面上に別のパターンを
配置する新規な発明であつて、前記薄膜をエツチ
ング法によつてパターンに形成した後、この薄膜
パターンの幅がレジスト・パターンの幅より細く
なるようにサイド・エツチングを行い〔同図ｄ〕、
かつ、絶縁材料を蒸着するとき前記薄膜パターン
の膜厚により僅かに薄く膜を形成する方法に関す
る。かくの如くサイド・エツチングを施し、絶縁
材料の膜厚の調整をなした実施例の構造は第３図
に示す如きもので、１１はシリコン基板、１２は
金（Au）−クロム（Cr）膜からなる導体パター
ン、１３はSiO2からなる絶縁膜、１４はレジス
ト膜をそれぞれ示す。 In order to solve this technical problem, the applicant completed an invention called a thin film pattern method (Showa
Patent Application No. 9003 of 1952, published in Japanese Unexamined Patent Publication No. 9003 on August 19, 1978.
53-94771). The invention is shown in FIG.
Referring to f, a thin film for forming a conductor pattern, for example, an Al-Cu film 32 is deposited on the substrate 31 [fifth
Figure a], a resist pattern 3 is formed on this thin film 32.
After etching the thin film 32 using the resist pattern 33 as a mask to form a desired conductor pattern [FIG. 3c],
insulating material while leaving the resist pattern;
For example, this is a novel invention in which SiO 2 34 is vapor-deposited [Fig. e], then the resist pattern 33 is removed to make it planar [Fig. f], and another pattern is placed on this plane. , after forming the thin film into a pattern by an etching method, side etching is performed so that the width of the thin film pattern is narrower than the width of the resist pattern [FIG. d];
The present invention also relates to a method of forming a film slightly thinner than the thickness of the thin film pattern when depositing an insulating material. The structure of the embodiment in which side etching is performed and the thickness of the insulating material is adjusted as described above is as shown in FIG. 3, where 11 is a silicon substrate, 12 is a gold (Au)-chromium (Cr) film. 13 is an insulating film made of SiO 2 , and 14 is a resist film.
前記した発明の実施に際しては、サイド・エツ
チングにより導体パターン１２の過度のエツチン
グによつてレジスト膜１４が剥がれ落ちることを
回避するためのエツチング時間、第３図に見られ
るSiO2膜１３と導体１２との間の空隙の制御お
よび導体幅が細ることに特に注意しなければなら
ない。また、最近の集積回路の微細化に合致すべ
くドライ・エツチングがより多く用いられるが、
それによるとサイド・エツチングは難しい作業で
ある。また、SiO2の蒸着前にアツシヤーが使え
ないのでシリコン基板１１表面や導体パターン１
２側面に吸着している水分等をプラズマで遊離す
ることができず、絶縁膜１３とシリコン基板１１
表面あるいは導体パターン１２側面との間で良好
な密着性が得られない。 In carrying out the invention described above, the etching time is set to prevent the resist film 14 from peeling off due to excessive etching of the conductor pattern 12 due to side etching, and the SiO 2 film 13 and the conductor 12 shown in FIG. Particular attention must be paid to controlling the air gap between the conductor and narrowing the conductor width. In addition, dry etching is increasingly used to meet the recent miniaturization of integrated circuits.
According to them, side etching is a difficult task. In addition, since an assher cannot be used before the SiO 2 evaporation, the surface of the silicon substrate 11 or the conductor pattern 1
2. Moisture or the like adsorbed on the two sides cannot be released by plasma, and the insulating film 13 and silicon substrate 11
Good adhesion cannot be obtained between the surface or the side surface of the conductor pattern 12.
また、導体例えばアルミニウムをドライ・エツ
チングした後に絶縁膜を成長させ（例えばSiO2
の蒸着）、リフトオフによつてアルミニウムを埋
め込みその表面の平坦化を得るという従来技術に
おいては、ドライ・エツチングの後に三塩化ホウ
素（BCl3）が残存するという問題がある。とこ
ろで、このBCl3をなくすためにアツシヤーを用
いると、リフトオフのためのレジストが酸化され
てなくなつてしまう。本発明は、以上に記載した
技術的課題の解決を提供するものであり、以下そ
れを添付図面を例に参照して説明する。 Alternatively, after dry etching a conductor such as aluminum, an insulating film is grown (e.g. SiO 2
In the conventional technique of embedding aluminum and obtaining a planarized surface by lift-off, there is a problem in that boron trichloride (BCl 3 ) remains after dry etching. By the way, if an atsher is used to eliminate this BCl 3 , the resist for lift-off will be oxidized and disappear. The present invention provides a solution to the technical problems described above, and will be explained below with reference to the accompanying drawings.
第４図ａ〜ｅは本発明の工程を示す断面説明図
である。同図ａに示されるように、表面に二酸化
シリコン等の絶縁膜が形成されたシリコン基板２
１上に、電極材料例えばアルミニウム（Al）（ま
たはアルミニウム（Al）−銅（Cu）もしくはその
他の適当な材料）層２２を公知の真空蒸着法また
はスパツタリング法で例えば1μｍの厚さに形成
した後にその上に多結晶（ポリ）シリコン層２３
を同じく真空蒸着またはスパツタリングで0.1μｍ
の厚さに形成する。この層の材料はMoSi2の如き
シリコン化合物でもよく、以下ポリシリコン層と
あるはSi化合物層を含む。ポリシリコン層２３の
上にレジスト・パターン２４を公知の方法で1μ
ｍの厚さに形成し、このレジスト・パターンをマ
スクとして前記２層すなわちポリシリコン層と電
極材料層を連続してエツチングする。同図ａには
ポリシリコン層の上にレジスト・パターン２４が
配置された構造が、また同図ｂには前記のエツチ
ングを終了した後の構造が示される。ここで、ア
ルミニウム層とポリシリコン層のエツチングは例
えば三塩化ホウ素（BCl3）を用いて連続して行
うとよい。次にアセトンまたはアツシヤーでレジ
スト２４を灰化し、剥離し、また残つた水分を除
去する。続いて同図ｄに示されるように全面に
SiOx（例えばSiO2）を被着してSiOx層２５を形
成し、四弗化炭素（CF4）＋O2（O2は５％）の雰
囲気でドライエツチングし、全面エツチングを施
す。この全面エツチングによつて絶縁層と電極の
表面が平坦化されなだらかな表面が得られる。す
なわちポリシリコンはSiOxよりもエツチング速
度が速いのでポリシリコン層２３上のSiOx層２
５は容易にリフトオフにより除去される。このと
きの構造は同図ｅに示される。図において、
SiOx膜２５とアルミニウム層２２との間に隙間
が見られるがそれは樹脂材料で埋めてもよく、ま
たはその上にフオスフオ・シリケート・グラス
（PSG）の層を形成してもよい。 FIGS. 4a to 4e are cross-sectional explanatory views showing the steps of the present invention. As shown in Figure a, a silicon substrate 2 has an insulating film such as silicon dioxide formed on its surface.
1, an electrode material such as aluminum (Al) (or aluminum (Al)-copper (Cu) or other suitable material) layer 22 is formed to a thickness of 1 μm, for example, by a known vacuum evaporation method or sputtering method. On top of that is a polycrystalline (poly)silicon layer 23.
0.1μm by vacuum evaporation or sputtering
Form to a thickness of . The material of this layer may be a silicon compound such as MoSi 2 , and hereinafter referred to as a polysilicon layer includes a Si compound layer. A resist pattern 24 with a thickness of 1 μm is formed on the polysilicon layer 23 by a known method.
m thick, and using this resist pattern as a mask, the two layers, namely the polysilicon layer and the electrode material layer, are successively etched. Figure a shows a structure in which a resist pattern 24 is placed on the polysilicon layer, and figure b shows the structure after the above-mentioned etching has been completed. Here, the aluminum layer and the polysilicon layer may be etched successively using, for example, boron trichloride (BCl 3 ). Next, the resist 24 is ashed with acetone or assher, peeled off, and the remaining moisture is removed. Then, as shown in Figure d,
A SiOx layer 25 is formed by depositing SiOx (for example, SiO 2 ), and dry etching is performed in an atmosphere of carbon tetrafluoride (CF 4 )+O 2 (O 2 is 5%) to perform etching on the entire surface. This entire surface etching flattens the surfaces of the insulating layer and the electrode, resulting in a smooth surface. In other words, since polysilicon has a faster etching speed than SiOx, the SiOx layer 2 on the polysilicon layer 23
5 is easily removed by lift-off. The structure at this time is shown in figure e. In the figure,
A gap is seen between the SiOx film 25 and the aluminum layer 22, which may be filled with a resin material, or a layer of phosphorus silicate glass (PSG) may be formed thereon.
しかる後、前記アルミニウム層２２の表出部に
接してSiOx層２５上に延在する上層配線層（図
示せず）を形成する。かかる上記配線層はアルミ
ニウム層２２とSiOx層２５との間に段差がない
ためほぼ平坦に形成され、断線等を生じない。 Thereafter, an upper wiring layer (not shown) is formed so as to be in contact with the exposed portion of the aluminum layer 22 and extend on the SiOx layer 25. Since there is no step between the aluminum layer 22 and the SiOx layer 25, the wiring layer is formed substantially flat and does not cause disconnection or the like.
上記にした本発明による方法の利点は、先ずド
ライ・エツチング後に例えばBCl3の如き有機物
の存在がなく、アツシヤーを用いるので形成され
た層の密着性を向上させることができる点にあ
る。またポリシリコンとSiOxとのエツチング速
度比の大なるエツチヤントガスを用いバリのない
平坦化が可能となる。更にアルミニウム層とポリ
シリコン層を蒸着によつて被着形成するために、
多くの基板のバツチ処理が可能になる。またレジ
ストを用いてのリフトオフ工程を伴わないので
SiOx層の加熱蒸着が可能になつて密着性が向上
する。またレジストパターンに過誤があつてポジ
テイブ・レジストを現像液で除去し再度第１層の
レジストを形成しようとするとき、アルミニウム
層はポリシリコン層で覆われているのでアルカリ
性の現像液に浸されず、第１層のレジスト再生が
容易である。さらに全面エツチングによるリフト
オフであるので表面がなめらかに平坦化されるこ
とである。また、本発明の方法はレジストによる
リフトオフでないので、レジストはそのままにし
ておいてもよい。 The advantages of the method according to the invention described above are that, after the dry etching, there is no presence of organic substances, such as BCl 3 , and the use of an atsher improves the adhesion of the formed layer. Further, by using an etchant gas with a high etching rate ratio between polysilicon and SiOx, flattening without burrs can be achieved. Furthermore, in order to deposit an aluminum layer and a polysilicon layer by vapor deposition,
Batch processing of many substrates becomes possible. In addition, it does not involve a lift-off process using resist.
It becomes possible to heat the SiOx layer and improve adhesion. In addition, when an error occurs in the resist pattern and the positive resist is removed with a developer and the first layer of resist is to be formed again, the aluminum layer is covered with a polysilicon layer, so it will not be immersed in the alkaline developer. , the first layer resist can be easily reproduced. Furthermore, since lift-off is performed by etching the entire surface, the surface is smooth and flattened. Furthermore, since the method of the present invention does not involve lift-off using the resist, the resist may be left as is.
第１図は従来技術による２層配線構造を示す断
面説明図、第２図は従来技術のリフトオフ法によ
る導体表面平坦化の工程を示す断面説明図、第３
図は従来技術による薄膜パターン形成方法の実施
例を示す断面説明図、第４図は本発明の方法を実
施する工程を示す断面説明図、第５図ａ〜ｆは従
来例の断面図である。
１，１１，２１……シリコン基板、４，１４，
２４……レジスト・パターン、２，５，１２，２
２……Al導体、２１……Si層、３，１３……
SiO2層、２５……SiOx層。
Fig. 1 is a cross-sectional explanatory diagram showing a two-layer wiring structure according to the conventional technology, Fig. 2 is a cross-sectional explanatory diagram showing the process of flattening the conductor surface by the conventional lift-off method,
The figure is an explanatory cross-sectional view showing an example of a thin film pattern forming method according to the prior art, FIG. 4 is an explanatory cross-sectional view showing the steps of implementing the method of the present invention, and FIGS. . 1, 11, 21...Silicon substrate, 4, 14,
24...Resist pattern, 2, 5, 12, 2
2...Al conductor, 21...Si layer, 3,13...
2 layers of SiO, 25...SiOx layer.
Claims (1)
坦な配線層を、前記半導体基板上に形成された前
記配線層とほぼ同じ厚さの絶縁層にはさみ込まれ
た状態で形成する半導体装置の製造方法におい
て、 半導体基板上に配線層を形成し、前記配線層上
に多結晶シリコンまたはシリコン化合物を形成す
る工程と、 これら２層をその上に形成されたレジストのパ
ターンをマスクとして三塩化ホウ素を用いてエツ
チングする工程と、 アツシヤーによりレジストを剥離すると同時
に、前工程により残存する三塩化ホウ素を除去
し、また残存する水分を除去する工程と、 前記２層を含む半導体基板上に絶縁層を前記配
線層の厚みとほぼ同じ厚さに形成する工程と、 前記多結晶シリコン層またはシリコン化合物層
のエツチング速度が絶縁層のエツチング速度より
速くなるようなガスを用いてドライエツチングを
行い、半導体基板上の絶縁層を残して前記多結晶
シリコン化合物層とその上に形成された絶縁膜を
除去する工程とを有することを特徴とする半導体
装置の製造方法。[Claims] 1. A wiring layer with a flat surface formed in a predetermined area on a semiconductor substrate is sandwiched between an insulating layer formed on the semiconductor substrate and having approximately the same thickness as the wiring layer. A method for manufacturing a semiconductor device includes the steps of forming a wiring layer on a semiconductor substrate, forming polycrystalline silicon or a silicon compound on the wiring layer, and patterning a resist formed on these two layers. a step of etching using boron trichloride as a mask; a step of peeling off the resist with an atsher, simultaneously removing the boron trichloride remaining in the previous step, and removing remaining moisture; and a semiconductor substrate including the two layers. forming an insulating layer on the wiring layer to a thickness that is approximately the same as the wiring layer; and dry etching using a gas such that the etching rate of the polycrystalline silicon layer or silicon compound layer is faster than the etching rate of the insulating layer. A method for manufacturing a semiconductor device, comprising the steps of: removing the polycrystalline silicon compound layer and the insulating film formed thereon, leaving an insulating layer on the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11933280A JPS5743418A (en) | 1980-08-29 | 1980-08-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11933280A JPS5743418A (en) | 1980-08-29 | 1980-08-29 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5743418A JPS5743418A (en) | 1982-03-11 |
| JPS6328335B2 true JPS6328335B2 (en) | 1988-06-08 |
Family
ID=14758851
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11933280A Granted JPS5743418A (en) | 1980-08-29 | 1980-08-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5743418A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5051257A (en) * | 1973-09-05 | 1975-05-08 |
-
1980
- 1980-08-29 JP JP11933280A patent/JPS5743418A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5051257A (en) * | 1973-09-05 | 1975-05-08 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5743418A (en) | 1982-03-11 |
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