JPS63283144A - Bump for semiconductor element - Google Patents
Bump for semiconductor elementInfo
- Publication number
- JPS63283144A JPS63283144A JP62119421A JP11942187A JPS63283144A JP S63283144 A JPS63283144 A JP S63283144A JP 62119421 A JP62119421 A JP 62119421A JP 11942187 A JP11942187 A JP 11942187A JP S63283144 A JPS63283144 A JP S63283144A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- mum
- fine particles
- conductive resin
- resin composite
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 229920005989 resin Polymers 0.000 claims abstract description 13
- 239000011347 resin Substances 0.000 claims abstract description 13
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000000843 powder Substances 0.000 claims description 9
- 239000011342 resin composition Substances 0.000 claims description 8
- 230000003746 surface roughness Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 26
- 239000011248 coating agent Substances 0.000 abstract description 8
- 238000000576 coating method Methods 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 229910052737 gold Inorganic materials 0.000 abstract description 4
- 239000010931 gold Substances 0.000 abstract description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 3
- 239000000203 mixture Substances 0.000 abstract description 3
- NIXOWILDQLNWCW-UHFFFAOYSA-M Acrylate Chemical compound [O-]C(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-M 0.000 abstract description 2
- 150000003949 imides Chemical class 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 229910052703 rhodium Inorganic materials 0.000 abstract description 2
- 239000000805 composite resin Substances 0.000 abstract 4
- 239000010419 fine particle Substances 0.000 abstract 4
- 239000004593 Epoxy Substances 0.000 abstract 1
- 239000002923 metal particle Substances 0.000 abstract 1
- 229910052763 palladium Inorganic materials 0.000 abstract 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 238000007747 plating Methods 0.000 description 5
- 230000002950 deficient Effects 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 208000025174 PANDAS Diseases 0.000 description 2
- 208000021155 Paediatric autoimmune neuropsychiatric disorders associated with streptococcal infection Diseases 0.000 description 2
- 240000004718 Panda Species 0.000 description 2
- 235000016496 Panda oleosa Nutrition 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000003973 paint Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920003002 synthetic resin Polymers 0.000 description 2
- 239000000057 synthetic resin Substances 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000009472 formulation Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000008642 heat stress Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- KCTAWXVAICEBSD-UHFFFAOYSA-N prop-2-enoyloxy prop-2-eneperoxoate Chemical compound C=CC(=O)OOOC(=O)C=C KCTAWXVAICEBSD-UHFFFAOYSA-N 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13018—Shape in side view comprising protrusions or indentations
- H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13199—Material of the matrix
- H01L2224/1329—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
- H01L2224/13299—Base material
- H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13344—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
- H01L2224/13299—Base material
- H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13355—Nickel [Ni] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
- H01L2224/13299—Base material
- H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13363—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/13364—Palladium [Pd] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
- H01L2224/13299—Base material
- H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13363—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/13373—Rhodium [Rh] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
- H01L2224/13399—Coating material
- H01L2224/134—Coating material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13438—Coating material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13444—Gold [Au] as principal constituent
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は液晶表示パネル等の駆動用半導体装置に係り、
液晶表示パネル上へ容易に実装できる半導体素子のバン
プに関する。[Detailed Description of the Invention] Industrial Application Field The present invention relates to a semiconductor device for driving a liquid crystal display panel, etc.
The present invention relates to bumps for semiconductor devices that can be easily mounted on liquid crystal display panels.
従来の技術
透明電極ｃ以下工τ０という）が形成された２枚のガラ
ス板を、電極面を対向させて配置してなる液晶表示パネ
ルの引出し電極に、直接駆動用半導体素子（以下ＬＳＩ
チップという）を実装する方法として、現在２つの方法
が提案式れている。Conventional technology A direct drive semiconductor element (hereinafter referred to as LSI
There are currently two proposed methods for mounting the chip.
その一つは、半田バンプによる７リツプチツプ方式、他
の一つはワイヤボンディング方式である。One is a 7-lip chip method using solder bumps, and the other is a wire bonding method.
前者の方式はＬＳＩチップのアルミ電極パッドに半田バ
ンプを形成し、ＩＴＯ上はＮ１−ムｕ、Ｏｒ−五Ｕなど
でメタライジング処理をし、前記ＬＳＩチンブをフェイ
スダウンにより位置合せした後、半田のりフローにより
接続するものである。ワイヤボンディング方式は前者と
同様にＩＴＯｉメタライジング処理し、ムＵ線またはム
！線にエフＬＳＩチップとＩＴＯを接続するものである
。前者の半田バンプは通常、ＬＳＩウェハーの製造プロ
セスが完成した後、ウェハー全面にＯｒまたはＴ１など
を蒸着し、さらにＯｕ 、 Ｐａ 、＾ｕ、ｐｔのいず
れかを蒸着する。この金属層の上に７オトレジスト金塗
布し、アルミパッド上のみを除去した後、半田メッキを
必要量メッキする。その後不要な金属層をエツチングで
除去し、半田バンプを得るものである。The former method involves forming solder bumps on the aluminum electrode pads of the LSI chip, metallizing the ITO with N1-mu, Or-5U, etc., aligning the LSI chip face down, and then soldering. It is connected by glue flow. The wire bonding method uses ITOi metallizing treatment like the former, and uses MuU wire or Mu! This is to connect the F LSI chip and ITO to the wire. For the former type of solder bump, usually after the LSI wafer manufacturing process is completed, Or or T1 is deposited on the entire surface of the wafer, and then one of Ou, Pa, ^u, and pt is deposited. On this metal layer, a gold resist is applied, and after removing only the top of the aluminum pad, the necessary amount of solder plating is applied. Thereafter, unnecessary metal layers are removed by etching to obtain solder bumps.
発明が解決しようとする問題点
この様に、ＩＴＯの引出し電極上へＬＳＩチップを実装
する方式は、前述の通り現在では２つの方式が提案され
ているが、いずれの方式とも工τＯ上にメタライジング
処理を施さなければならないことと、ＬＳＩチップには
特殊なバンプを形成しなければならない等、複雑なプロ
セスが必要であると共にこのプロセスを実施するために
は高額な設備投資を伴ない、製品の歩留低下やコストア
ップ等、多くの問題点を有する。また近年、液晶表示パ
ネルの大型化に伴い、複数個のＬＳＩチップを同一パネ
ル上に実装しなければならず、１個のＬＳＩチップでも
不良となれば、パネル全体が不良となってしまう。すな
わち、前述の方式では不良ＬＳＩチップの交換が不可能
に近く、また交換が可能としても多大の時間を要し、製
品コストのアップをまねく結果となる。Problems to be Solved by the Invention As mentioned above, two methods have been proposed at present for mounting an LSI chip on an ITO extraction electrode, but both methods require a metallization process on the τO. Complex processes are required, such as the need to undergo rising treatment and the need to form special bumps on LSI chips, and implementing this process requires a large amount of capital investment, resulting in poor product quality. There are many problems such as decreased yield and increased cost. Furthermore, in recent years, as liquid crystal display panels have become larger, a plurality of LSI chips must be mounted on the same panel, and if even one LSI chip becomes defective, the entire panel becomes defective. That is, in the above-mentioned method, it is almost impossible to replace a defective LSI chip, and even if replacement is possible, it takes a lot of time, resulting in an increase in product cost.
また、ワイヤボンディング方式によるＬＳＩチップの実
装においても前記方式と同様の問題点が残る。すなわち
、大型液晶パネルにおいてはワイヤ数が１０００〜２ｏ
ｏＯ本にもお：び、１箇所のボンディングミスが生じて
も交換しなければならない結果となり、その交換作業に
多大の時間を要する。ま几ワイヤボンディング方式はＬ
ＳＩチップのアルミ電極パッドを全面覆うことができず
、湿度の介在によりアルミの腐食が発生する危険性もあ
り、信頼性面でも問題点が残る。Furthermore, the same problems as those of the above-mentioned method remain even when mounting an LSI chip using the wire bonding method. In other words, in a large LCD panel, the number of wires is 1000 to 2000.
Also, even if a bonding error occurs in one place, it will have to be replaced, and the replacement work will take a lot of time. The wire bonding method is L.
It is not possible to completely cover the aluminum electrode pad of the SI chip, and there is a risk that the aluminum will corrode due to the presence of humidity, and problems remain in terms of reliability.
本発明は以上、述べたような問題点を解決するものであ
る。The present invention solves the above-mentioned problems.
問題点を解決するための手段
上記問題点を解決するために本発明は、半導体素子のア
ルミパッド上のバンプが感光性樹脂と導電性粉体から々
る導電性樹脂組成物からなυ、液晶表示パネルのＩＴＯ
引出し電極はメタライジング処理することなく、上記Ｌ
ＳＩチップを接着剤を介し、フェイスダウンで信頼性良
く、実装することが可能となるものである。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention proposes that the bumps on the aluminum pads of the semiconductor element be made of a conductive resin composition consisting of a photosensitive resin and conductive powder, and a liquid crystal display. Display panel ITO
The extraction electrode is not metallized and the above L
This makes it possible to reliably mount an SI chip face-down using an adhesive.
作用
以上の構成に、Ｂ、ＬＳＩチップのアルミパッド上に導
電性樹脂バンプを形成することにより、Ｉ’ｌ’Ｏ上に
メタライジング処理することなく、接着剤を介し熱圧着
するのみで確実な接続が可能となり、取付け、取外しが
容易となる。B. By forming conductive resin bumps on the aluminum pads of the LSI chip, it is possible to securely bond the I'l'O by thermocompression only with an adhesive, without metalizing the I'l'O. Connection is possible, and installation and removal are easy.
実施例
本発明による半導体素子用バンプは、導電性樹脂組成物
により形成されるもので、樹脂組成物は感光性を有する
樹脂、例えばエポキシアクリレート系樹脂、アクリレー
ト基を有するイミド樹脂などが使用できる。結合剤とな
る樹脂に感光性を持たせることは、ＬＳＩチップにバン
プを形成するプロセスにおいてファインパターンを作ら
なければならないことと、プロセスが簡素化できること
にある。すなわち本発明によるバンプはフォトリソ工程
により形成するものである。また導電性粉体としてはニ
ッケル粉あるいはニッケル粉に金メッキを施したものや
、ムｕ 、 Ｐｄ 、 Ｒｈなどの貴金属粉を単独また
は複合して用いることができる。これらの金属粉として
平均粒径が０．２〜２．０μｍの範囲のものを用いると
前述のようなバンプ表面の凹凸が形成され導電性の面で
良好な結果が得られる。上記ニッケル粉に０．１〜１０
ｗｔ％のムＵメッキを施しても良く、この場合は更に電
気的な安定性が得られる。ムＵメッキがＱ、１ ｗｔ％
以下であると導電性の点でメッキの効果がなくニッケル
粉と同程度となり、また感光性樹脂中に分散させたとき
均一な分散が困難となる。またＩＱｗｔ％以上になると
導電性、耐酸化性の点で優れたものとなるが経済的に不
利となり、適宜調整することが必要である。また上記ニ
ッケル粉は樹脂組成物１００重量部に対し、５０〜１２
０重量部の範囲で配合することができる。ニッケル粉が
６０重量部以下になると導電性が悪くなると共に、バン
プ表面が平滑となりＩＴＯ上への良好な接続に対し不利
となってくる。また１２０重量部以上になると塗料化し
たときの性状（粘性、チクソトロピー）が悪く均一な塗
膜を得ることが困難となると同時に透光性が悪くなり光
群像度が充分得られなくなる。EXAMPLE The bump for a semiconductor device according to the present invention is formed from a conductive resin composition, and the resin composition can be a photosensitive resin such as an epoxy acrylate resin or an imide resin having an acrylate group. The reason for imparting photosensitivity to the resin used as the binder is that a fine pattern must be created in the process of forming bumps on an LSI chip, and the process can be simplified. That is, the bump according to the present invention is formed by a photolithography process. Further, as the conductive powder, nickel powder, nickel powder plated with gold, and noble metal powders such as Mu, Pd, and Rh can be used alone or in combination. If these metal powders have an average particle diameter in the range of 0.2 to 2.0 μm, the bump surface will be uneven as described above, and good results will be obtained in terms of conductivity. 0.1 to 10 to the above nickel powder
It is also possible to apply U plating of wt%, and in this case, even more electrical stability can be obtained. MuU plating is Q, 1 wt%
If it is below, the plating effect will be ineffective in terms of conductivity and it will be on the same level as nickel powder, and when it is dispersed in a photosensitive resin, it will be difficult to disperse it uniformly. Moreover, if it exceeds IQwt%, it will be excellent in terms of conductivity and oxidation resistance, but it will be economically disadvantageous, so it is necessary to adjust it appropriately. Further, the above nickel powder is 50 to 12 parts by weight per 100 parts by weight of the resin composition.
It can be blended in a range of 0 parts by weight. When the amount of nickel powder is less than 60 parts by weight, the conductivity deteriorates and the bump surface becomes smooth, which is disadvantageous for good connection to ITO. If the amount exceeds 120 parts by weight, the properties (viscosity, thixotropy) of the paint will be poor, making it difficult to obtain a uniform coating, and at the same time, the light transmittance will be poor, making it impossible to obtain a sufficient degree of optical grouping.
また、導電粉であるニッケル粉は前述の通りバンプ表面
の凹凸を形成することと、導電性の面から樹枝状のもの
が良い。樹枝状粉は電解法により作られるもので、これ
を使用することによって粒子同士のからみ合いが生じ、
電気的に接触点が多く導電性が改善される。ま之、塗膜
表面は凹凸が適度に生じ、本発明の目的でもあるＩＴＯ
との接触が良好となるものである。Further, as the conductive powder, nickel powder is preferably dendritic in order to form unevenness on the bump surface as described above, and in terms of conductivity. Dendritic powder is made by electrolytic method, and by using it, particles become entangled with each other.
There are many electrical contact points and conductivity is improved. However, the surface of the coating film has moderate unevenness, which is the purpose of the present invention.
This provides good contact with the
図に本発明の実施例による半導体素子用バンプを示す。The figure shows a bump for a semiconductor device according to an embodiment of the present invention.
感光性樹脂組成物と導電性粉体からなる導電性樹脂組成
物は半導体素子が形成されたシリコンウェハー４上へ全
面コーティングし、その厚みが６μｍ以上になるよう粘
度やコーティング条件を決める。厚みが６μｍ以下にな
るような条件を選ぶとバンプ１表面の凹凸ａが小さくな
ることと、ＩＴＯ上へ熱圧着したときの垂直方向の歪量
が少なく信頼性面で不安定となってくる。５μｍ以上で
あれば上記問題はなく安定した接続が得られる。また厚
みの上限としては３０μｍまでが好ましく、これ以上に
なると垂直方向の抵抗値が高くなり、実装後の電圧損失
が大きく実用的でない。A conductive resin composition composed of a photosensitive resin composition and conductive powder is coated on the entire surface of the silicon wafer 4 on which semiconductor elements are formed, and the viscosity and coating conditions are determined so that the thickness thereof becomes 6 μm or more. If conditions are selected such that the thickness is 6 μm or less, the unevenness a on the surface of the bump 1 will be small and the amount of distortion in the vertical direction when thermocompression bonded onto ITO will be small, resulting in instability in terms of reliability. If the thickness is 5 μm or more, the above problem will not occur and a stable connection can be obtained. Further, the upper limit of the thickness is preferably up to 30 μm; if it exceeds this value, the resistance value in the vertical direction becomes high and the voltage loss after mounting becomes large, making it impractical.
一方、バンプ表面の凹凸ａは１μｍ以上が好ましく、こ
れ以下になると、熱圧着時に１個のＬＳＩチップ内のバ
ンプ高さのばらつきを吸収することができず、接続不良
のバンプが生ずる。凹凸ａの上限は特になく、バンプ厚
みまでの凹凸ａでも接続は可能であるが、実用上、１μ
ｍ前後が好ましい結果となる。On the other hand, the unevenness a on the bump surface is preferably 1 μm or more; if it is less than this, variations in bump height within one LSI chip cannot be absorbed during thermocompression bonding, resulting in bumps with poor connections. There is no particular upper limit for the unevenness a, and it is possible to connect even if the unevenness a is up to the thickness of the bump, but in practical terms, 1μ
A preferable result is around m.
次に本発明により形成されたバンプ付ＬＳＩチップ１Ｉ
Ｔｏ上へメタライズすることなく実装する方法について
述べる。これまで一般に用いられている方法は例えば合
成樹脂（熱可塑性樹脂またはＢステージとなり得る熱硬
化性樹脂）中に導電性粉体を均一に分散させ、シート状
にした、いわゆる異方導電性接着剤（水平方向に絶縁性
を示し、垂直方向に導電性を示す）’１ＩＴｏ上あるい
はＬＳＩチップ上へ仮止めし、ＬＳＩチップの裏面から
加圧、加熱することにエフバンブとＩＴＯ間に導電性粉
体の粒子が挾み込まれ垂直方向に導通する。前記合成樹
脂は冷却すると固着または硬化によリガラス上へＬＳＩ
チップが強固に接続される。本発明によるバンプを使用
すれば前述のような異方導電性接着剤を使用しなくとも
接続は可能である。すなわち絶縁性樹脂であっても熱圧
着時にバンプとＩＴＯ間に介在する極く薄い絶縁被膜全
ＬｓＩチップ上のバンプ表面の凸部によって突き破り、
凸部で電気的接触、凹部に介在する樹脂により固着が十
分おこなわれることによって、ＩＴＯと直接信頼性の高
い接続がとれる。バンプ表面に凹凸がなく平滑な場合は
絶縁被膜が間に介在することにより導通不良となる。Next, a bumped LSI chip 1I formed according to the present invention
A method of mounting without metalizing on To will be described. The method commonly used so far is, for example, by uniformly dispersing conductive powder in a synthetic resin (thermoplastic resin or thermosetting resin that can be B-staged) and forming it into a sheet using a so-called anisotropic conductive adhesive. (Exhibiting insulating properties in the horizontal direction and conductive properties in the vertical direction) '1 Temporarily fixed on ITo or LSI chip, and applying pressure and heat from the back side of the LSI chip. particles are intercalated and conduction occurs in the vertical direction. When the synthetic resin is cooled, it solidifies or hardens and is transferred onto the glass to form an LSI.
The chip is firmly connected. If the bump according to the present invention is used, connection can be made without using an anisotropic conductive adhesive as described above. In other words, even if the insulating resin is used, the very thin insulating coating interposed between the bump and the ITO during thermocompression bonding is pierced by the convex portion of the bump surface on the entire LsI chip.
A direct and reliable connection with ITO can be achieved by electrical contact at the convex portions and sufficient adhesion by the resin interposed in the concave portions. If the bump surface is smooth and has no irregularities, poor conductivity will occur due to the presence of an insulating film between the bumps.
（以下余 白）
表１に本発明による導電性樹脂組成物の配合を示す。各
実施例の組成物はセラミック三本ロール機により混練し
均質な塗料とした。これら各塗料をシリコンウェハー上
ヘスピンナーにより大体６μｍ、ＩＱμｍ、３０μｍの
厚みになるよう塗布した。アルミパッドは１００μｍ角
のものを使用し、塗布面積がアルミパッド面積より大き
くなるようマスクを設計、使用した。全面コーティング
されたウェハー上へ上記マスクを位置合せし紫外光にエ
フ露光、現像しパンダを得た。さらにウエノ・−はチッ
プの所定寸法にダイシングしバンプ付ＬＳＩチップを得
た。このＬＳＩチップを異方導電性接着剤（（株）スリ
ーボンド製ＴＢ−ｓ３了０）を用い、ＩＴＯ上へ位置合
せし熱圧着した。熱圧着はＬＳＩチップ裏面よりほぼチ
ップサイズと同一＋７）加熱ツールにより１８０℃、１
０秒、 １ｓＫＶ′ａｆの条件で圧着した。それぞれの
実施例で１チツプ１ｏＯパツドのものｉｌｏチップ実施
し、そのときの接続不良（電気的オープン）数を表２に
示す。(The following is a blank space) Table 1 shows the formulation of the conductive resin composition according to the present invention. The compositions of each example were kneaded using a ceramic three-roll machine to form a homogeneous coating. Each of these paints was applied onto a silicon wafer using a spinner to a thickness of approximately 6 μm, IQ μm, and 30 μm. A 100 μm square aluminum pad was used, and a mask was designed and used so that the coating area was larger than the area of the aluminum pad. The above mask was positioned on the wafer coated on the entire surface, exposed to ultraviolet light, and developed to obtain a panda. Further, Ueno was diced into a predetermined chip size to obtain an LSI chip with bumps. This LSI chip was aligned and thermocompression bonded onto ITO using an anisotropic conductive adhesive (TB-s3ry0, manufactured by Three Bond Corporation). Thermocompression bonding is performed from the back side of the LSI chip at 180℃ using a heating tool (approximately the same size as the chip + 7).
The pressure bonding was carried out under the conditions of 0 seconds and 1 sKV'af. In each example, one chip with 100 pads was used, and the number of connection failures (electrical open) at that time is shown in Table 2.
表 ２
比較例１として、バンプ厚み３μｍとし、表面が平滑（
凹凸は０．３μｍ）なものを上記と同様て熱圧着した。Table 2 As Comparative Example 1, the bump thickness was 3 μm and the surface was smooth (
The unevenness was 0.3 μm) and thermocompression bonded in the same manner as above.
また比較例２としてバンプにムｕ＝２使用しその厚みが
１６μｍで表面粗さ０．２μｍのものを同様に圧着した
。その結果を表２に示す。Further, as Comparative Example 2, a bump having a thickness of 16 μm and a surface roughness of 0.2 μm was bonded in the same manner using mu=2. The results are shown in Table 2.
さらに、実施例５お工び６に示したＬＳＩチップを実際
の液晶表示パネルの引出し電極へ前述の異方導電性接着
剤を用い接続し、液晶表示パネルを動作させ、完全動作
することを確認し念。Furthermore, the LSI chip shown in Example 5 and Step 6 was connected to the extraction electrode of an actual liquid crystal display panel using the above-mentioned anisotropic conductive adhesive, the liquid crystal display panel was operated, and complete operation was confirmed. I regret it.
発明の効果
以上のように本発明による半導体素子用バンプは従来の
半田バンプのように蒸着、メッキ、エツチングなどの複
雑なプロセスと設備を必要とせず単なるフォトリソ工程
のみで形成できる。また、本発明にエフ得たパンダとそ
の実装方法は有機材料が構造体となっているため、熱ス
トレスなどによるガラスとシリコンの熱膨張係数の差を
吸収できるため、半田バンプのようなりラックの発生は
ない。さらにバンプ表面の凹凸により、熱圧着時に確実
な接続ができ複数個を同一パネル上へ実装する大型の液
晶表示パネルに対し、非常に大きな特徴を有するもので
ある。しかも、もし実装不良となった場合でも局部的に
加熱することにエフ簡単に取外すことができ、再度圧着
するという部分的補修が可能となり高価な液晶表示パネ
ルを廃棄することなく使用でき、製造上の効果大である
。Effects of the Invention As described above, bumps for semiconductor devices according to the present invention do not require complicated processes and equipment such as vapor deposition, plating, and etching unlike conventional solder bumps, and can be formed by a simple photolithography process. In addition, since the panda and its mounting method obtained from the present invention have a structure made of organic material, they can absorb the difference in thermal expansion coefficient between glass and silicon due to heat stress, etc. There have been no outbreaks. Furthermore, the unevenness of the bump surface allows reliable connection during thermocompression bonding, which is a very important feature for large-sized liquid crystal display panels in which a plurality of bumps are mounted on the same panel. Moreover, even if a mounting defect occurs, it can be easily removed by applying local heat, and it can be partially repaired by crimping it again, allowing it to be used without having to discard an expensive LCD panel. is highly effective.
図は本発明の実施例を示す断面図である。
１・・・・・・バンプ、２・・・・・・アルミパッド、
３・・・・・・絶縁膜、４・・・・・・シリコンウェハ
ー。The figure is a sectional view showing an embodiment of the present invention. 1...Bump, 2...Aluminum pad,
3... Insulating film, 4... Silicon wafer.
Claims (1)
導電性粉体からなる導電性樹脂組成物からなり、厚み５
μｍ以上で表面の凹凸が１μｍ以上であることを特徴と
する半導体素子用バンプ。The bump on the aluminum pad of the semiconductor element is made of a conductive resin composition consisting of a photosensitive resin and conductive powder, and has a thickness of 5.
A bump for a semiconductor device, characterized in that the bump has a surface roughness of 1 μm or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62119421A JPH0815154B2 (en) | 1987-05-15 | 1987-05-15 | Bump for semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62119421A JPH0815154B2 (en) | 1987-05-15 | 1987-05-15 | Bump for semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63283144A true JPS63283144A (en) | 1988-11-21 |
| JPH0815154B2 JPH0815154B2 (en) | 1996-02-14 |
Family
ID=14761041
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62119421A Expired - Fee Related JPH0815154B2 (en) | 1987-05-15 | 1987-05-15 | Bump for semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0815154B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5196371A (en) * | 1989-12-18 | 1993-03-23 | Epoxy Technology, Inc. | Flip chip bonding method using electrically conductive polymer bumps |
| US5879761A (en) * | 1989-12-18 | 1999-03-09 | Polymer Flip Chip Corporation | Method for forming electrically conductive polymer interconnects on electrical substrates |
| WO2005045919A1 (en) * | 2003-11-11 | 2005-05-19 | Toray Engineering Co.,Ltd. | Non-contact id card and manufacturing method thereof |
-
1987
- 1987-05-15 JP JP62119421A patent/JPH0815154B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5196371A (en) * | 1989-12-18 | 1993-03-23 | Epoxy Technology, Inc. | Flip chip bonding method using electrically conductive polymer bumps |
| US5879761A (en) * | 1989-12-18 | 1999-03-09 | Polymer Flip Chip Corporation | Method for forming electrically conductive polymer interconnects on electrical substrates |
| US5918364A (en) * | 1989-12-18 | 1999-07-06 | Polymer Flip Chip Corporation | Method of forming electrically conductive polymer interconnects on electrical substrates |
| WO2005045919A1 (en) * | 2003-11-11 | 2005-05-19 | Toray Engineering Co.,Ltd. | Non-contact id card and manufacturing method thereof |
| US7332798B2 (en) | 2003-11-11 | 2008-02-19 | Toray Engineering Company, Limited | Non-contact ID card and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0815154B2 (en) | 1996-02-14 |
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