JP5075569B2 - Wiring board and IC chip mounting method - Google Patents

Wiring board and IC chip mounting method Download PDF

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JP5075569B2
JP5075569B2 JP2007271026A JP2007271026A JP5075569B2 JP 5075569 B2 JP5075569 B2 JP 5075569B2 JP 2007271026 A JP2007271026 A JP 2007271026A JP 2007271026 A JP2007271026 A JP 2007271026A JP 5075569 B2 JP5075569 B2 JP 5075569B2
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connection
height
wiring board
chip
connection electrode
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JP2009099830A (en
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美佐夫 小西
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Dexerials Corp
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Sony Chemical and Information Device Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Description

本発明は、例えば液晶表示装置等の配線基板上へのICチップの実装技術に関する。   The present invention relates to a technique for mounting an IC chip on a wiring board such as a liquid crystal display device.

従来より、例えば液晶表示装置等の配線(ガラス)基板上にICチップを実装する手段として、異方導電性接着フィルムが用いられている(例えば、特許文献1参照)。   Conventionally, for example, an anisotropic conductive adhesive film has been used as means for mounting an IC chip on a wiring (glass) substrate such as a liquid crystal display device (see, for example, Patent Document 1).

この異方導電性接着フィルムを用いてCOG(Cip On Glass)方式によってICチップの実装を行うには、ICチップの接続端子(バンプ)と配線基板の接続電極との間に異方導電性接着フィルムを介在させ、熱圧着ヘッドによってICチップを加熱するとともに押圧することによって熱圧着を行う。   In order to mount an IC chip using this anisotropic conductive adhesive film by the COG (Cip On Glass) method, anisotropic conductive adhesion is performed between the connection terminals (bumps) of the IC chip and the connection electrodes of the wiring board. Thermocompression bonding is performed by interposing a film and heating and pressing the IC chip with a thermocompression bonding head.

しかし、従来、ICチップに設けられたバンプのうち、特定のバンプに関して接続不良が生ずる場合がある。
例えば、図8(a)に示すように、ICチップ101のチップ本体102縁部に設けられたバンプ103、104のうち、短辺側に設けられたバンプ(楕円A、B内)に接続不良が生ずる場合がある。
However, conventionally, a connection failure may occur with respect to a specific bump among the bumps provided on the IC chip.
For example, as shown in FIG. 8 (a), the bumps 103 and 104 provided on the edge of the chip body 102 of the IC chip 101 are poorly connected to the bumps (in the ellipses A and B) provided on the short side. May occur.

また、図8(b)に示すように、ICチップ201のチップ本体202長辺部に設けられたバンプ203〜205のうち、一方の長辺側においてバンプが千鳥状に設けられたICチップ201にあっては、外側のバンプ204(楕円C内)に接続不良が生ずる場合がある。
特開平8−7658号公報
Further, as shown in FIG. 8B, among the bumps 203 to 205 provided on the long side portion of the chip body 202 of the IC chip 201, the IC chip 201 in which the bumps are provided in a staggered manner on one long side. In such a case, connection failure may occur in the outer bump 204 (in the ellipse C).
JP-A-8-7658

本発明は、このような従来技術の課題を解決するためになされたもので、接続不良が発生せず導通信頼性を向上させることが可能な異方導電性接着剤を用いたICチップの接続技術を提供することを目的とする。   The present invention has been made to solve the above-described problems of the prior art, and it is possible to connect an IC chip using an anisotropic conductive adhesive capable of improving conduction reliability without causing a connection failure. The purpose is to provide technology.

上記目的を達成するためになされた請求項1記載の発明は、基板本体の接続側面上に複数の接続電極を有し、異方導電性接着剤によってICチップが実装される配線基板であって、前記複数の接続電極のうち、予め特定された領域の接続電極の高さが、他の接続電極の高さより高くされたものである。
請求項2記載の発明は、請求項1記載の発明において、前記基板本体の接続側面は長方形状に形成されるとともに前記複数の接続電極が当該基板本体の接続側面の縁部に設けられ、当該複数の接続電極のうち、前記接続側面の短辺側縁部に設けられた接続電極の高さが、前記接続側面の長辺側縁部に設けられた接続電極の高さより高くされたものである。
請求項3記載の発明は、請求項1記載の発明において、前記複数の接続電極が前記接続側面の縁部に沿って複数の列状に設けられ、当該複数列の接続電極のうち、当該接続側面の縁部外側に設けられた接続電極の高さが、当該接続側面の縁部内側に設けられた接続電極の高さより高くされたものである。
請求項4記載の発明は、請求項1乃至3のいずれか1項記載の発明において、前記予め特定された領域の接続電極の高さと、前記他の接続電極の高さとの差が、使用する異方導電性接着剤の導電粒子の粒径の5%〜95%であるものである。
請求項5記載の発明は、前記配線基板が液晶表示装置用のガラス基板であるものである。
請求項6記載の発明は、突起状の接続電極が形成されたICチップと、請求項1乃至5のいずれか1項記載の配線基板との間に異方導電性接着剤を配置し、加熱及び加圧を行うことにより、前記配線基板と前記ICチップを接着するとともに対応する電極同士を電気的に接続する工程を有するICチップの実装方法である。
In order to achieve the above object, the invention according to claim 1 is a wiring substrate having a plurality of connection electrodes on a connection side surface of a substrate body, on which an IC chip is mounted by an anisotropic conductive adhesive. Among the plurality of connection electrodes, the height of the connection electrode in the region specified in advance is set higher than the heights of the other connection electrodes.
The invention according to claim 2 is the invention according to claim 1, wherein the connection side surface of the substrate body is formed in a rectangular shape, and the plurality of connection electrodes are provided at the edge of the connection side surface of the substrate body. Among the plurality of connection electrodes, the height of the connection electrode provided at the short side edge of the connection side is higher than the height of the connection electrode provided at the long side edge of the connection side. is there.
According to a third aspect of the invention, in the first aspect of the invention, the plurality of connection electrodes are provided in a plurality of rows along the edge of the connection side surface, and the connection among the plurality of rows of connection electrodes. The height of the connection electrode provided outside the edge of the side surface is set higher than the height of the connection electrode provided inside the edge of the connection side surface.
According to a fourth aspect of the present invention, in the invention according to any one of the first to third aspects, a difference between a height of the connection electrode in the predetermined area and a height of the other connection electrode is used. It is 5% to 95% of the particle size of the conductive particles of the anisotropic conductive adhesive.
According to a fifth aspect of the present invention, the wiring board is a glass substrate for a liquid crystal display device.
According to a sixth aspect of the present invention, an anisotropic conductive adhesive is disposed between the IC chip on which the projecting connection electrode is formed and the wiring substrate according to any one of the first to fifth aspects, and heating is performed. And an IC chip mounting method including a step of bonding the wiring board and the IC chip and electrically connecting corresponding electrodes by applying pressure.

本発明の場合、基板本体の接続側面上に設けられた複数の接続電極のうち、予め特定された領域(例えば、長方形状の接続側面の短辺側縁部領域や、接続側面の縁部に沿って実装端子が複数の列状に設けられた場合の縁部外側領域)の接続電極の高さが、他の接続電極の高さより高くされていることから、異方導電性接着剤を用いて熱圧着を行った場合に、従来技術ではつぶれ状態が不十分であった特定の導電粒子を十分に圧縮することができる。
その結果、本発明によれば、ICチップの各実装端子上における導電粒子の圧縮状態を均一にすることができるので、種々のタイプのICチップにおいて、導通信頼性を向上させることができる。
特に、本発明によれば、径の大きな導電粒子を用いることなく導通信頼性を向上させることができるので、ファインピッチのバンプを有するICチップに有用となるものである。
In the case of the present invention, among the plurality of connection electrodes provided on the connection side surface of the substrate body, a region specified in advance (for example, a short side edge region of the rectangular connection side surface or an edge portion of the connection side surface) Since the height of the connection electrode in the outer region of the edge when the mounting terminals are provided in a plurality of rows along the mounting terminals is higher than the height of the other connection electrodes, an anisotropic conductive adhesive is used. Thus, when thermocompression bonding is performed, the specific conductive particles, which are not sufficiently crushed by the conventional technology, can be sufficiently compressed.
As a result, according to the present invention, since the compressed state of the conductive particles on each mounting terminal of the IC chip can be made uniform, the conduction reliability can be improved in various types of IC chips.
In particular, according to the present invention, since the conduction reliability can be improved without using conductive particles having a large diameter, it is useful for an IC chip having fine pitch bumps.

本発明によれば、接続不良が発生せず導通信頼性を向上させることができる異方導電性接着剤を用いたICチップの接続技術を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the connection technique of the IC chip using the anisotropic conductive adhesive which can improve conduction | electrical_connection reliability without generating a connection failure can be provided.

以下、本発明の実装方法の好ましい形態について図面を用いて説明する。
なお、後述するように、本発明に用いる異方導電性接着剤7は、絶縁性接着剤樹脂8中に導電粒子9が分散されているものであるが、その態様としては、ペースト状又はフィルム状のいずれにも適用することができる。
Hereinafter, preferred embodiments of the mounting method of the present invention will be described with reference to the drawings.
As will be described later, the anisotropic conductive adhesive 7 used in the present invention is one in which conductive particles 9 are dispersed in an insulating adhesive resin 8. It can be applied to any of the shapes.

図1(a)(b)は、本発明に用いるICチップ及び配線基板の例を示す概略図で、図1(a)は平面図、図1(b)は同配線基板の正面図である。また、図2(a)(b)及び図3(a)(b)は、本発明の原理を示す説明図である。   1A and 1B are schematic views showing examples of an IC chip and a wiring board used in the present invention. FIG. 1A is a plan view and FIG. 1B is a front view of the wiring board. . FIGS. 2A and 2B and FIGS. 3A and 3B are explanatory views showing the principle of the present invention.

図1(a)(b)に示すように、本発明に用いるICチップ1は、例えば長方体形状のチップ本体2を有し、その接続側面2aが長方形形状に形成されている。   As shown in FIGS. 1 (a) and 1 (b), an IC chip 1 used in the present invention has, for example, a rectangular-shaped chip body 2, and its connection side surface 2a is formed in a rectangular shape.

ICチップ1の接続側面2aの縁部(長辺及び短辺)には、接続電極として、バンプを用いた実装端子3、4、5が、所定のピッチをおいて複数個設けられている。   A plurality of mounting terminals 3, 4, and 5 using bumps as connection electrodes are provided at the edges (long side and short side) of the connection side surface 2 a of the IC chip 1 with a predetermined pitch.

本例の場合、実装端子3、4、5は、例えば図3(a)(b)に示すように、それぞれパターン状のAl(アルミニウム)からなる電極部20上に、Au(金)からなるバンプ40、50を形成することにより構成されている。なお、図3(a)(b)中、符号21は、パッシベーション膜である。   In the case of this example, the mounting terminals 3, 4, 5 are made of Au (gold) on electrode parts 20 made of patterned Al (aluminum), as shown in FIGS. 3A and 3B, for example. The bumps 40 and 50 are formed. In FIGS. 3A and 3B, reference numeral 21 denotes a passivation film.

ここで、Al電極部上にAuバンプを形成するには、例えば以下に説明する公知のめっき法(例えば特許2936680号公報参照)を用いることができる。
すなわち、めっき法では、Al配線(電極部)と絶縁膜が形成されたSi基板を用意し、この絶縁膜にAl配線を外部に接続するための開孔を形成し、その全面にTi(チタン)をスパッタしてTi膜を形成し、Pd(パラジウム)をスパッタしてPd膜を形成する。次いで、その上にレジストを被着しこれをパターニングすることによって、Auバンプ形成用の開孔を有するレジストマスクを形成する。
さらに、前述の開孔からPd膜の上にAuめっきを施してAuめっき層を形成し、その後、前述のレジストマスクを除去し、さらに金めっき層をマスクにしてPd膜とTi膜をエッチングする。これによりAl電極部上に形成されたAuバンプを得る。
Here, in order to form the Au bump on the Al electrode portion, for example, a known plating method described below (see, for example, Japanese Patent No. 2936680) can be used.
That is, in the plating method, an Si substrate on which an Al wiring (electrode part) and an insulating film are formed is prepared, an opening for connecting the Al wiring to the outside is formed in the insulating film, and Ti (titanium) is formed on the entire surface. ) Is sputtered to form a Ti film, and Pd (palladium) is sputtered to form a Pd film. Next, a resist is deposited thereon and patterned to form a resist mask having openings for forming Au bumps.
Further, Au plating is performed on the Pd film from the above-mentioned openings to form an Au plating layer, and then the above-described resist mask is removed, and the Pd film and Ti film are etched using the gold plating layer as a mask. . As a result, an Au bump formed on the Al electrode portion is obtained.

一方、本例の配線基板11は、例えばガラスからなる基板本体12を有し、その接続側面、即ち接続領域12aには、ICチップの実装端子3、4、5に対応する接続電極13、14、15が、所定のピッチをおいて複数個設けられている。
ここで、基板本体12の接続領域12aは長方形形状に形成され、その長辺側縁部に、接続電極13、15がそれぞれ設けられている。また、基板本体12の短辺側縁部には、接続電極14が設けられている。
On the other hand, the wiring substrate 11 of this example has a substrate body 12 made of, for example, glass, and connection electrodes 13 and 14 corresponding to the mounting terminals 3, 4 and 5 of the IC chip are provided on the connection side surface, that is, the connection region 12a. , 15 are provided at a predetermined pitch.
Here, the connection region 12a of the substrate body 12 is formed in a rectangular shape, and the connection electrodes 13 and 15 are provided on the long side edges thereof, respectively. A connection electrode 14 is provided on the short side edge of the substrate body 12.

ここで、配線基板11が液晶表示装置用のガラス基板である場合には、接続領域12aの一方の長辺側縁部の接続電極13及び短辺側縁部の接続電極14は、例えば、Alを用いたスパッタリング法及びフォトリソグラフィ法によるエッチングによって形成することができる。
また、他方の長辺側縁部の接続電極15は、ITOを用いたスパッタリング法及びフォトリソグラフィ法によるエッチングによって形成することができる。
Here, when the wiring substrate 11 is a glass substrate for a liquid crystal display device, the connection electrode 13 on one long side edge and the connection electrode 14 on the short side edge of the connection region 12a are, for example, Al. It can be formed by etching using sputtering and photolithography.
The connection electrode 15 on the other long side edge can be formed by sputtering using ITO and etching by photolithography.

本発明では、複数の接続電極のうち、予め特定された領域の接続電極の高さが、他の接続電極の高さより高くされている。   In the present invention, among the plurality of connection electrodes, the height of the connection electrode in the region specified in advance is set higher than the heights of the other connection electrodes.

本実施の形態においては、図1(a)(b)に示すように、配線基板11の接続領域12aの短辺側縁部(楕円C,Dで示す領域)に設けられた接続電極14の高さが、接続領域12aの長辺側縁部に設けられた接続電極13、15の高さより高くなるように構成されている。   In the present embodiment, as shown in FIGS. 1A and 1B, the connection electrodes 14 provided on the short side edges (regions indicated by ellipses C and D) of the connection region 12a of the wiring board 11 are provided. The height is configured to be higher than the height of the connection electrodes 13 and 15 provided on the long side edge of the connection region 12a.

本発明の場合、配線基板11の短辺側縁部の接続電極14の高さを長辺側縁部の接続電極13、15の高さより高くする方法は、特に限定されることはないが、製造工程の簡易さの観点からは、例えば図3(b)に示すように、接続電極14上に金属によるかさ上げ部14aを設けて電極部分を多層化することが好ましい。   In the case of the present invention, the method of making the height of the connection electrode 14 on the short side edge of the wiring board 11 higher than the height of the connection electrodes 13 and 15 on the long side edge is not particularly limited. From the viewpoint of simplicity of the manufacturing process, for example, as shown in FIG. 3B, it is preferable to provide a metal raised portion 14a on the connection electrode 14 to make the electrode portion multilayer.

この場合、かさ上げ部14aの形成方法としては、例えば、アルミニウムを用いたスパッタリング法及びフォトリソグラフィ法によるエッチングを採用することができる。   In this case, as a method of forming the raised portion 14a, for example, etching using aluminum and etching by photolithography can be employed.

そして、これにより、配線基板11の短辺側縁部の接続電極14の高さが、かさ上げ部14aの分だけ長辺側縁部の接続電極13、15の高さより高い配線基板11を得ることができる。   Thus, the wiring substrate 11 is obtained in which the height of the connection electrode 14 at the short side edge of the wiring substrate 11 is higher than the height of the connection electrodes 13 and 15 at the long side edge by the raised portion 14a. be able to.

以下、本発明の原理を図2(a)(b)及び図3(a)(b)を用いて説明する。ここでは、上記配線基板11上に上記ICチップ1を実装する場合を考える。また、長辺側縁部の接続電極13、15のうち、一方の接続電極15を例にとって説明する。   The principle of the present invention will be described below with reference to FIGS. 2 (a) and 2 (b) and FIGS. 3 (a) and 3 (b). Here, a case where the IC chip 1 is mounted on the wiring board 11 is considered. Also, one of the connection electrodes 13 and 15 on the long side edge will be described as an example.

配線基板11の実装時には、図2(a)に示すように、配線基板11とICチップ1との間に、異方導電性接着剤7を配置して熱圧着を行うが、その際、ICチップ1側から加熱及び加圧を行う。   When the wiring board 11 is mounted, as shown in FIG. 2A, the anisotropic conductive adhesive 7 is disposed between the wiring board 11 and the IC chip 1 and thermocompression bonding is performed. Heating and pressing are performed from the chip 1 side.

この場合、ICチップ1の到達温度は200〜250℃程度となるが、配線基板11側の到達温度は100〜150℃程度とICチップ1に比べて低いため、加熱時にはICチップ1の方が延びた状態となっている。このため、実装後、冷却の際にICチップ1のチップ本体2の収縮が大きく、例えば、図2(b)に示すように、配線基板11よりICチップ1の反りが大きくなり、結果として、実装部分全体に反りが発生する。   In this case, the reached temperature of the IC chip 1 is about 200 to 250 ° C., but the reached temperature on the wiring board 11 side is about 100 to 150 ° C., which is lower than that of the IC chip 1. It is in an extended state. For this reason, the shrinkage of the chip body 2 of the IC chip 1 is large after cooling after mounting, for example, as shown in FIG. 2B, the warp of the IC chip 1 becomes larger than the wiring substrate 11, and as a result, Warpage occurs in the entire mounting part.

この状態では、ICチップ1の接続側面2aの縁部のうち短辺側縁部2bに応力が加わりやすいので、図3(a)に示すように、異方導電性接着剤7の導電粒子9bに対する押圧力が他の領域(本例では長辺側縁部)の導電粒子9に比べて小さく導電粒子9bの変形(圧縮)率が不足する傾向にある。   In this state, stress is easily applied to the short side edge 2b of the edges of the connection side surface 2a of the IC chip 1, so that the conductive particles 9b of the anisotropic conductive adhesive 7 as shown in FIG. Is smaller than the conductive particles 9 in other regions (long side edge in this example), and the deformation (compression) rate of the conductive particles 9b tends to be insufficient.

そこで、図3(b)に示すように、配線基板11の接続領域12aの短辺側縁部12bにおいて、接続電極14上にかさ上げ部14aを設けることにより、接続電極14の高さを、接続領域12aの長辺側縁部の接続電極15の高さより高くする。   Therefore, as shown in FIG. 3B, by providing a raised portion 14a on the connection electrode 14 at the short side edge portion 12b of the connection region 12a of the wiring board 11, the height of the connection electrode 14 is increased. The height is higher than the height of the connection electrode 15 at the long side edge of the connection region 12a.

これにより、ICチップ1及び配線基板11間において接続領域12aの短辺部側縁部の実装端子4及び接続電極14間の間隔を、長辺部側縁部の接続電極15及び実装端子5間の間隔と同等にすることができるので、ICチップ1の接続側面2aの縁部の各実装端子部分において導電粒子9に対して均一の力で押圧して圧縮率を均一にすることができる。   Thereby, between the IC chip 1 and the wiring board 11, the space | interval between the mounting terminal 4 and the connection electrode 14 of the short side part side edge of the connection area | region 12a is set between the connection electrode 15 and the mounting terminal 5 of the long side part side edge. Therefore, the compression rate can be made uniform by pressing the conductive particles 9 with a uniform force at each mounting terminal portion at the edge of the connection side surface 2a of the IC chip 1.

本発明の場合、配線基板11における、長辺部側縁部の接続電極13及び15と、短辺部側縁部の接続電極14の高さの差は、特に限定されることはないが、導電粒子9の圧縮状態を均一にして導通信頼性を向上させる観点からは、導電粒子9の粒径の5%〜95%とすることが好ましく、より好ましくは、30%〜60%である。   In the case of the present invention, the difference in height between the connection electrodes 13 and 15 on the long side portion side edge and the connection electrode 14 on the short side portion side edge in the wiring board 11 is not particularly limited. From the viewpoint of making the compressed state of the conductive particles 9 uniform and improving the conduction reliability, it is preferably 5% to 95% of the particle size of the conductive particles 9, and more preferably 30% to 60%.

具体的には、例えば、導電粒子9の粒径が3μm〜5μmである場合において、接続電極13及び15と、接続電極14の高さの差を、0.5μm〜3μmとすることができる。   Specifically, for example, when the particle diameter of the conductive particles 9 is 3 μm to 5 μm, the height difference between the connection electrodes 13 and 15 and the connection electrode 14 can be set to 0.5 μm to 3 μm.

この場合、導電粒子9の弾性率が、100kgf/mm2〜1000kgf/mm2の範囲にある場合により効果的である。 In this case, the elastic modulus of the conductive particles 9 is more effective when a range of 100kgf / mm 2 ~1000kgf / mm 2 .

図4(a)(b)、図5(a)(b)及び図6(a)(b)は、本発明の他の実施の形態を示すものであり、以下、上記実施の形態と同一の部分については同一の符号を付しその詳細な説明を省略する。   4 (a) (b), FIG. 5 (a) (b) and FIG. 6 (a) (b) show other embodiments of the present invention. These parts are denoted by the same reference numerals, and detailed description thereof is omitted.

図4(a)(b)に示すように、本実施の形態に用いるICチップ1Aは、チップ本体2の接続側面2aの長辺側縁部に、接続電極としての実装端子3、4A、5が設けられている。   As shown in FIGS. 4A and 4B, the IC chip 1A used in the present embodiment has mounting terminals 3, 4A, 5 as connection electrodes on the long side edge of the connection side surface 2a of the chip body 2. Is provided.

そして、ICチップ1Aの接続側面2aの長辺側縁部の一方において、この長辺側縁部に沿って2列の実装端子3、4Aが千鳥状に配列されている。   Then, on one of the long side edges of the connection side surface 2a of the IC chip 1A, two rows of mounting terminals 3 and 4A are arranged in a staggered pattern along the long side edge.

一方、本実施の形態の配線基板11Aは、チップ本体12の接続領域12aの長辺側縁部に、上述したICチップ1Aの実装端子3、4A、5にそれぞれ対応する接続電極13、14A、15が設けられている。   On the other hand, the wiring board 11A of the present embodiment has connection electrodes 13, 14A, corresponding to the mounting terminals 3, 4A, 5 of the IC chip 1A described above, on the long side edge of the connection region 12a of the chip body 12, respectively. 15 is provided.

ここでは、配線基板11Aの接続領域12aの長辺側縁部の一方において、この長辺側縁部に沿って2列の接続電極13、14Aが千鳥状に配列されている。   Here, on one of the long side edges of the connection region 12a of the wiring board 11A, two rows of connection electrodes 13 and 14A are arranged in a staggered pattern along the long side edge.

そして、これら接続電極13、14A、15のうち、接続領域12aの一方の長辺側縁部外側に設けられた接続電極14A(図4(a)の楕円Eで示す領域)の高さが、この長辺側縁部内側に設けられた接続電極13、15の高さより高くなるように構成されている。   And among these connection electrodes 13, 14 </ b> A, 15, the height of the connection electrode 14 </ b> A (a region indicated by an ellipse E in FIG. 4A) provided outside one long side edge of the connection region 12 a is It is comprised so that it may become higher than the height of the connection electrodes 13 and 15 provided inside this long side edge part.

この場合、配線基板11Aの接続領域12aの長辺側縁部外側の接続電極14Aの高さを長辺側縁部内側の接続電極13の高さより高くする方法は、上記実施の形態と同様の方法を採用することができる。
すなわち、本発明の場合、特に限定されるものではないが、製造工程の簡易さの観点からは、図4(b)及び6(b)に示すように、接続電極14A上に金属によるかさ上げ部14aを設けて電極部分を多層化することが好ましい。
In this case, the method of making the height of the connection electrode 14A outside the long side edge of the connection region 12a of the wiring board 11A higher than the height of the connection electrode 13 inside the long side edge is the same as in the above embodiment. The method can be adopted.
That is, in the case of the present invention, although not particularly limited, from the viewpoint of simplicity of the manufacturing process, as shown in FIGS. 4B and 6B, raising the connection electrode 14A with a metal. It is preferable to provide the part 14a to make the electrode part multilayer.

なお、本実施の形態の場合、配線基板11Aの接続領域12aの短辺側縁部には、接続電極は設けられていない。   In the present embodiment, no connection electrode is provided on the short side edge of the connection region 12a of the wiring board 11A.

このような2列の接続電極13、14Aが長辺側縁部に沿って千鳥状に配列されている配線基板11Aにおいて、実装時にICチップ1A側から加熱及び加圧を行うと、図5(a)(b)に示すように、チップ本体2の中央部分が長辺側縁部と比較して沈み込む傾向がある。   In the wiring substrate 11A in which the two rows of connection electrodes 13 and 14A are arranged in a zigzag pattern along the long side edge, when heating and pressurization are performed from the IC chip 1A side during mounting, FIG. a) As shown in (b), the central portion of the chip body 2 tends to sink compared to the long side edge.

このため、ICチップ1Aの実装後において、チップ本体2の中央部分と長辺側縁部との高さに差が生ずる。この差は、2列の実装端子3、4Aが設けられた側の長辺側縁部2cにおいて、特に大きくなる(数μm程度)。   For this reason, after mounting the IC chip 1A, a difference occurs in the height between the central portion of the chip body 2 and the long side edge. This difference is particularly large (approximately several μm) at the long side edge 2c on the side where the two rows of mounting terminals 3 and 4A are provided.

ここで、図6(a)に示すように、配線基板11Aの接続電極13、14Aの高さが等しい場合には、この長辺側縁部外側の接続電極14Aの導電粒子9cに対する押圧力が、他の領域の導電粒子9に比べて小さくなり、この導電粒子9cの変形(圧縮)率が不足する。   Here, as shown in FIG. 6A, when the heights of the connection electrodes 13 and 14A of the wiring board 11A are equal, the pressing force on the conductive particles 9c of the connection electrodes 14A on the outer edge of the long side is reduced. The conductive particles 9 are smaller than the other conductive particles 9, and the deformation (compression) rate of the conductive particles 9c is insufficient.

そこで、本実施の形態では、図6(b)に示すように、配線基板11Aの接続領域12aの長辺側縁部12c外側における接続電極14Aの高さを、その上にかさ上げ部14aを設けることによって長辺側縁部2c内側の接続電極13の高さより高くする。   Therefore, in the present embodiment, as shown in FIG. 6B, the height of the connection electrode 14A outside the long side edge 12c of the connection region 12a of the wiring board 11A is set, and the raised portion 14a is formed thereon. By providing, it is made higher than the height of the connection electrode 13 inside the long side edge 2c.

これにより上記実施の形態と同様に、ICチップ1A及び配線基板11A間において、実装端子4A及び接続電極14A間の間隔を、実装端子5及び接続電極15間の間隔と同等にすることができるので、配線基板11Aの縁部の各実装端子部分において導電粒子9に対して均一の力で押圧して圧縮率を均一にすることができる。   As a result, as in the above embodiment, the distance between the mounting terminal 4A and the connection electrode 14A can be made equal to the distance between the mounting terminal 5 and the connection electrode 15 between the IC chip 1A and the wiring board 11A. The compression rate can be made uniform by pressing the conductive particles 9 with a uniform force at each mounting terminal portion at the edge of the wiring board 11A.

本発明の場合、配線基板11Aにおける、接続電極14Aと、接続電極13及び15との高さの差は、特に限定されることはないが、導電粒子9の圧縮状態を均一にして導通信頼性を向上させる観点からは、接続電極14Aと、接続電極13及び15との高さの差を、導電粒子9の粒径の5%〜95%とすることが好ましい。   In the case of the present invention, the difference in height between the connection electrode 14A and the connection electrodes 13 and 15 in the wiring board 11A is not particularly limited. From the viewpoint of improving the resistance, the difference in height between the connection electrode 14A and the connection electrodes 13 and 15 is preferably 5% to 95% of the particle diameter of the conductive particles 9.

具体的には、例えば、導電粒子9の粒径が3μm〜5μmである場合において、接続電極14Aと、13及び15との差を、0.5μm〜3μmとすることができる。   Specifically, for example, when the particle diameter of the conductive particles 9 is 3 μm to 5 μm, the difference between the connection electrode 14A and 13 and 15 can be 0.5 μm to 3 μm.

この場合、導電粒子9の弾性率が、100kgf/mm2〜1000kgf/mm2の範囲にある場合により効果的である。 In this case, the elastic modulus of the conductive particles 9 is more effective when a range of 100kgf / mm 2 ~1000kgf / mm 2 .

なお、本発明は上述の実施の形態に限られることなく、種々の変更を行うことができる。
例えば、複数の接続電極のうち高さを高くする接続電極については、上述の実施の形態のように接続側面の縁部(短辺部又は長辺部)に配列されたものの全部には限られず、一部の接続電極であってもよい。
The present invention is not limited to the above-described embodiment, and various changes can be made.
For example, the connection electrodes that increase the height among the plurality of connection electrodes are not limited to all those arranged at the edge (short side or long side) of the connection side as in the above-described embodiment. Some of the connection electrodes may be used.

例えば、図7に示すように、接続領域2aの長辺側縁部に複数の接続電極3、5が形成されたICチップ1Bと、接続領域12aの長辺側縁部に複数の接続電極13が形成された配線基板11Bを用いた場合において、配線基板11Bにおける任意の(例えば、ICチップ1Bの高さの低い実装端子3B、5Bに対応する)接続電極13B、15Bの高さを、それぞれ他の接続電極13、15の高さより高くすることもできる。   For example, as shown in FIG. 7, an IC chip 1B in which a plurality of connection electrodes 3 and 5 are formed on the long side edge of the connection region 2a, and a plurality of connection electrodes 13 on the long side edge of the connection region 12a. When the wiring board 11B on which is formed is used, the height of any of the connection electrodes 13B and 15B (for example, corresponding to the mounting terminals 3B and 5B having a low height of the IC chip 1B) on the wiring board 11B is set respectively. It can be made higher than the height of the other connection electrodes 13 and 15.

また、チップ本体の接続側面の隅部分の接続電極の高さを他の領域の接続電極より高くするなどICチップに応じて種々の変更を行うことができる。   In addition, various changes can be made according to the IC chip, such as making the height of the connection electrodes at the corners of the connection side surface of the chip body higher than the connection electrodes in other regions.

さらに、特定の領域の接続電極の高さを高くする方法については、上述した接続電極上にかさ上げ部を設けて多層化する方法のほか、例えば、当初接続電極を厚く形成しておき、高さを高くする当該領域以外の領域の接続電極の表層部分をエッチング等によって除去してその領域の電極高さを低くするようにしてもよい。   Further, regarding the method of increasing the height of the connection electrode in a specific region, in addition to the above-described method of providing a raised portion on the connection electrode to form a multilayer, for example, the connection electrode is initially formed thick, The surface layer portion of the connection electrode in a region other than the region where the height is increased may be removed by etching or the like to reduce the electrode height in the region.

さらに、本発明は、液晶表示装置用のガラス配線基板のみならず、種々のタイプの配線基板に適用することができるものである。   Furthermore, the present invention can be applied not only to glass wiring boards for liquid crystal display devices but also to various types of wiring boards.

以下、本発明の実施例を比較例とともに詳細に説明する。   Examples of the present invention will be described below in detail together with comparative examples.

[異方導電性接着フィルムの作成]
絶縁性接着剤樹脂としてエポキシ樹脂(ジャパンエポキシレジン社製 EP828)30重量部、フェノキシ樹脂(InChem社製 PKHH)40重量部、エポキシ硬化剤(旭化成社製 HX3941HP)30重量部、導電粒子(積水化学社製 平均粒径3μm)25重量部を、溶剤としてトルエン/酢酸エチルを用いてミキサーで溶解混合させペーストとした。
[Creation of anisotropic conductive adhesive film]
As an insulating adhesive resin, 30 parts by weight of an epoxy resin (EP828 manufactured by Japan Epoxy Resin Co., Ltd.), 40 parts by weight of a phenoxy resin (PKHH manufactured by InChem), 30 parts by weight of an epoxy curing agent (HX3941HP manufactured by Asahi Kasei Co., Ltd.), conductive particles (Sekisui Chemical) 25 parts by weight of an average particle size of 3 μm manufactured by the company was dissolved and mixed with a mixer using toluene / ethyl acetate as a solvent to obtain a paste.

そして、剥離処理を施したPETフィルム上に、上述したペーストを塗布し、70℃に設定した電気オーブンで8分間加熱し、乾燥膜厚が20μmの異方導電性接着フィルムを作成した。   And the paste mentioned above was apply | coated on PET film which performed the peeling process, it heated for 8 minutes with the electric oven set to 70 degreeC, and the anisotropic conductive adhesive film whose dry film thickness is 20 micrometers was created.

<実施例1>
図4(a)(b)に示す千鳥足配列の実装端子を有するICチップ(1A)と、これに対応するように厚さ0.5mmの透明ガラス板上に千鳥足配列のAl接続電極を形成した長方形形状の配線基板(11A)を用いた。
<Example 1>
The IC chip (1A) having the staggered mounting terminals shown in FIGS. 4 (a) and 4 (b), and the staggered Al connection electrode formed on a transparent glass plate having a thickness of 0.5 mm so as to correspond thereto. A rectangular wiring board (11A) was used.

ここでは、配線基板(11A)の一方の長辺側縁部外側のAl接続電極(14A)の高さを配線膜の多層化により1μmとし、また当該長辺側縁部内側のAl接続電極(13)の高さを0.2μmとした。
一方、配線基板の他方の長辺側縁部側のITO接続電極(15)の高さ(厚さ)は、0.2μmとした。
Here, the height of the Al connection electrode (14A) on the outer side edge of one long side of the wiring board (11A) is set to 1 μm by multilayering of the wiring film, and the Al connection electrode ( The height of 13) was 0.2 μm.
On the other hand, the height (thickness) of the ITO connection electrode (15) on the other long side edge side of the wiring board was set to 0.2 μm.

なお、長辺側縁部外側及び内側の接続電極(14A)、(13)の幅は20μmとし、接続電極間ピッチは25μmとした。
一方、ICチップの実装端子については、すべて高さ15μmに形成した。
The widths of the connection electrodes (14A) and (13) on the outer and inner side edges of the long side were 20 μm, and the pitch between the connection electrodes was 25 μm.
On the other hand, all the IC chip mounting terminals were formed to a height of 15 μm.

<比較例1>
配線基板の長辺側縁部外側の接続電極(14A)の高さを0.2μmとして接続電極の高さを全て同一にし、それ以外は、実施例1と同一の構成の配線基板を用いた。
<Comparative Example 1>
The height of the connection electrode (14A) on the outer edge of the long side of the wiring board was set to 0.2 μm, and all the heights of the connection electrodes were made the same. Otherwise, the wiring board having the same configuration as in Example 1 was used. .

<実施例2>
図1(a)(b)に示すストレート配列の実装端子を有するICチップ(1)と、これに対応するように厚さ0.5mmの透明ガラス板上にストレート配列のAl接続電極を形成した配線基板(11)を用いた。
ここでは、配線基板(11)の短辺側縁部のAl接続電極(14)の高さを配線膜の多層化により1μmとした。
一方、配線基板の長辺側縁部側のAl接続電極(13)、ITO接続電極(15)の高さは、それぞれ0.2μmとした。
<Example 2>
An IC chip (1) having mounting terminals in a straight arrangement shown in FIGS. 1 (a) and 1 (b), and an Al connection electrode in a straight arrangement were formed on a transparent glass plate having a thickness of 0.5 mm so as to correspond to this. A wiring board (11) was used.
Here, the height of the Al connection electrode (14) at the short side edge of the wiring board (11) is set to 1 μm by multilayering the wiring film.
On the other hand, the heights of the Al connection electrode (13) and the ITO connection electrode (15) on the long side edge portion side of the wiring board were each 0.2 μm.

本実施例の場合、短辺側縁部の接続電極(14)及び長辺側縁部の接続電極(13、15)の幅は30μmとし、接続電極間ピッチは50μmとした。   In the case of this example, the width of the connection electrode (14) on the short side edge and the connection electrode (13, 15) on the long side edge was 30 μm, and the pitch between the connection electrodes was 50 μm.

<比較例2>
長辺側縁部及び短辺側縁部側の接続電極(13、14、15)の高さを0.2μmとして接続電極の高さを全て同一にし、それ以外は、実施例2と同一の構成の配線基板を用いた。
<実施例3>
図7に示すストレート配列の実装端子を有するICチップ(1B)と、これに対応するするように厚さ0.5mmの透明ガラス板上にストレート配列のAl接続電極を形成した配線基板(11B)を用いた。
ここでは、ICチップ(1B)の特定の実装端子(3B、5B)の高さを14μmとし、他の実装端子(3、5)の高さより1μm低く形成した。
一方、配線基板(11B)については、ICチップ(1B)の高さを低く形成した実装端子(3B、5B)に対応する両長辺側縁部のAl接続電極(13B、15B)の高さを、配線膜の多層化により1μmとした。
一方、配線基板の長辺側縁部側の他のAl接続電極(13)、また、ITO接続電極(15)の高さは、それぞれ0.2μmとした。
<Comparative example 2>
The height of the connection electrodes (13, 14, 15) on the long side edge portion and the short side edge portion side is set to 0.2 μm so that all the connection electrode heights are the same. A wiring board having a configuration was used.
<Example 3>
An IC chip (1B) having mounting terminals arranged in a straight line shown in FIG. 7 and a wiring board (11B) in which Al connection electrodes arranged in a straight line are formed on a transparent glass plate having a thickness of 0.5 mm so as to correspond thereto. Was used.
Here, the height of the specific mounting terminals (3B, 5B) of the IC chip (1B) is 14 μm, and is 1 μm lower than the heights of the other mounting terminals (3, 5).
On the other hand, for the wiring board (11B), the heights of the Al connection electrodes (13B, 15B) at both long side edges corresponding to the mounting terminals (3B, 5B) formed with a low height of the IC chip (1B). Was made 1 μm by multilayering the wiring film.
On the other hand, the heights of the other Al connection electrode (13) and the ITO connection electrode (15) on the side of the long side edge of the wiring board were each 0.2 μm.

本実施例の場合、配線基板の接続電極(13、15)の幅は30μmとし、接続電極間ピッチは50μmとした。   In the case of this example, the width of the connection electrodes (13, 15) of the wiring board was 30 μm, and the pitch between the connection electrodes was 50 μm.

<比較例3>
両長辺側縁部の接続電極(13、15)の高さを0.2μmとして接続電極の高さを全て同一にし、それ以外は、実施例2と同一の構成の配線基板を用いた。
<Comparative Example 3>
The height of the connection electrodes (13, 15) on both long side edges was set to 0.2 μm, and the heights of all the connection electrodes were the same. Otherwise, a wiring substrate having the same configuration as in Example 2 was used.

[評価]
異方導電性接着フィルムとして上述したものを用い、上述した各配線基板上に各ICチップを熱圧着した。
[Evaluation]
What was mentioned above as an anisotropic conductive adhesive film was used, and each IC chip was thermocompression-bonded on each wiring board mentioned above.

この場合、圧着条件は、温度200℃、圧力30MPa、時間10秒とし、さらに、温度85℃、相対湿度85%の条件下で500時間のエージングを行い、各実装端子間の導通試験を行った。その結果を表1、2、3に示す。   In this case, the pressure bonding conditions were a temperature of 200 ° C., a pressure of 30 MPa, and a time of 10 seconds. Further, aging was performed for 500 hours under the conditions of a temperature of 85 ° C. and a relative humidity of 85%, and a continuity test between the mounting terminals was performed. . The results are shown in Tables 1, 2, and 3.

一方、熱圧着後のICチップ内における導電粒子のつぶれ状態を顕微鏡を用いて目視観察した。   On the other hand, the collapsed state of the conductive particles in the IC chip after thermocompression bonding was visually observed using a microscope.

この場合、導電粒子が均一につぶれているものを「○」、実装端子間において導電粒子のつぶれ状態が不均一で、つぶれ状態が十分でない導電粒子が存在するものを「×」とした。   In this case, the case where the conductive particles are uniformly crushed is indicated by “◯”, and the state where the conductive particles are not uniformly crushed between the mounting terminals and the state where the conductive particles are not sufficiently crushed is indicated by “X”.

Figure 0005075569
Figure 0005075569

Figure 0005075569
Figure 0005075569

Figure 0005075569
Figure 0005075569

[評価結果]
実施例1、実施例2及び実施例3については、エージング後において、8Ω以下の抵抗上昇に制御されており、長辺側縁部外側(実施例1)、短辺側(実施例2)及び低バンプを形成した実施例3の実装端子間における導通が長期間安定していることがわかる。
[Evaluation results]
About Example 1, Example 2, and Example 3, after aging, it is controlled by the resistance rise of 8 ohms or less, the long side edge part outer side (Example 1), the short side (Example 2), and It can be seen that the conduction between the mounting terminals of Example 3 in which the low bumps are formed is stable for a long time.

また、導電粒子のつぶれ状態についても、各実装端子及び接続電極間において均一につぶれていることが確認された。   Further, it was confirmed that the conductive particles were uniformly crushed between the mounting terminals and the connection electrodes.

一方、比較例1については、エージング後において34Ωの抵抗上昇が見られ、また、長辺側縁部外側の実装端子上において、導電粒子のつぶれ具合が十分でない部分が存在した。   On the other hand, in Comparative Example 1, a resistance increase of 34Ω was observed after aging, and there were portions where the degree of collapse of the conductive particles was not sufficient on the mounting terminals outside the long side edge.

さらに、比較例2については、エージング後において39Ωの抵抗上昇が見られ、また、短辺側縁部の実装端子上において、導電粒子のつぶれ具合が十分でない部分が存在した。
さらにまた、比較例3については、エージング後において42Ωの抵抗上昇が見られ、また、高さを低くした実装端子上において、導電粒子のつぶれ具合が十分でない部分が存在した。
以上より、本発明の効果を実証することができた。
Further, in Comparative Example 2, a resistance increase of 39Ω was observed after aging, and there were portions where the conductive particles were not sufficiently crushed on the mounting terminals on the short side edge.
Furthermore, in Comparative Example 3, a resistance increase of 42Ω was observed after aging, and there was a portion where the degree of collapse of the conductive particles was not sufficient on the mounting terminal whose height was lowered.
From the above, the effect of the present invention could be verified.

(a):本発明に用いるICチップ及び配線基板の例を示す概略平面図である。(b):同配線基板の正面図である。(A): It is a schematic plan view which shows the example of the IC chip and wiring board used for this invention. (B): It is a front view of the wiring board. (a)(b):本発明の原理を示す説明図である。(A) (b): It is explanatory drawing which shows the principle of this invention. (a)(b):本発明の原理を示す説明図である。(A) (b): It is explanatory drawing which shows the principle of this invention. (a):本発明に用いるICチップ及び配線基板の他の例を示す概略平面図である。(b):同配線基板の側面図である。(A): It is a schematic plan view which shows the other example of the IC chip and wiring board used for this invention. (B): It is a side view of the same wiring board. (a)(b):本発明の原理を示す説明図である。(A) (b): It is explanatory drawing which shows the principle of this invention. (a)(b):本発明の原理を示す説明図である。(A) (b): It is explanatory drawing which shows the principle of this invention. 本発明に用いるICチップ及び配線基板の他の例を示す概略平面図である。It is a schematic plan view which shows the other example of the IC chip and wiring board used for this invention. (a):従来例に係るICチップの外観構成を示す概略平面図である。(b):他の従来例に係るICチップの外観構成を示す概略平面図である。(A): It is a schematic plan view which shows the external appearance structure of the IC chip which concerns on a prior art example. (B): It is a schematic plan view which shows the external appearance structure of the IC chip based on another prior art example.

符号の説明Explanation of symbols

1 ICチップ
2 チップ本体
2a 接続側面
2b 短辺側縁部
3,4 実装端子
7 異方導電性接着剤
9 導電粒子
11 配線基板
12 基板本体
12a 接続領域
DESCRIPTION OF SYMBOLS 1 IC chip 2 Chip body 2a Connection side surface 2b Short side edge 3,4 Mounting terminal 7 Anisotropic conductive adhesive 9 Conductive particle 11 Wiring board 12 Substrate body 12a Connection area

Claims (6)

基板本体の接続側面上に複数の接続電極を有し、異方導電性接着剤によってICチップが実装される配線基板であって、
前記複数の接続電極のうち、予め特定された領域の接続電極の高さが、他の接続電極の高さより高くされた配線基板。
A wiring board having a plurality of connection electrodes on a connection side surface of a substrate body, and an IC chip is mounted by an anisotropic conductive adhesive,
A wiring board in which a height of a connection electrode in a predetermined region among the plurality of connection electrodes is higher than a height of another connection electrode.
前記基板本体の接続側面は長方形状に形成されるとともに前記複数の接続電極が当該基板本体の接続側面の縁部に設けられ、当該複数の接続電極のうち、前記接続側面の短辺側縁部に設けられた接続電極の高さが、前記接続側面の長辺側縁部に設けられた接続電極の高さより高くされた請求項1記載の配線基板。   The connection side surface of the substrate body is formed in a rectangular shape, and the plurality of connection electrodes are provided at the edge portion of the connection side surface of the substrate body, and the short side edge portion of the connection side surface among the plurality of connection electrodes. The wiring board according to claim 1, wherein a height of the connection electrode provided on the connection side is set higher than a height of the connection electrode provided on a long side edge of the connection side surface. 前記複数の接続電極が前記接続側面の縁部に沿って複数の列状に設けられ、当該複数列の接続電極のうち、当該接続側面の縁部外側に設けられた接続電極の高さが、当該接続側面の縁部内側に設けられた接続電極の高さより高くされた請求項1記載の配線基板。   The plurality of connection electrodes are provided in a plurality of rows along the edge of the connection side surface, and among the connection electrodes of the plurality of rows, the height of the connection electrode provided outside the edge of the connection side surface is The wiring board according to claim 1, wherein the wiring board is made higher than a height of a connection electrode provided inside an edge of the connection side surface. 前記予め特定された領域の接続電極の高さと、前記他の接続電極の高さとの差が、使用する異方導電性接着剤の導電粒子の粒径の5%〜95%である請求項1乃至3のいずれか1項記載の配線基板。   The difference between the height of the connection electrode in the predetermined region and the height of the other connection electrode is 5% to 95% of the particle size of the conductive particles of the anisotropic conductive adhesive to be used. 4. The wiring board according to any one of items 1 to 3. 前記配線基板が液晶表示装置用のガラス基板である請求項1乃至4のいずれか1項記載の配線基板。   The wiring substrate according to any one of claims 1 to 4, wherein the wiring substrate is a glass substrate for a liquid crystal display device. 突起状の接続電極が形成されたICチップと、請求項1乃至5のいずれか1項記載の配線基板との間に異方導電性接着剤を配置し、
加熱及び加圧を行うことにより、前記配線基板と前記ICチップを接着するとともに対応する電極同士を電気的に接続する工程を有するICチップの実装方法。
An anisotropic conductive adhesive is disposed between the IC chip on which the projecting connection electrode is formed and the wiring substrate according to any one of claims 1 to 5,
An IC chip mounting method including a step of bonding the wiring board and the IC chip and electrically connecting corresponding electrodes by heating and pressing.
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